1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * smc91x.c 4 * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices. 5 * 6 * Copyright (C) 1996 by Erik Stahlman 7 * Copyright (C) 2001 Standard Microsystems Corporation 8 * Developed by Simple Network Magic Corporation 9 * Copyright (C) 2003 Monta Vista Software, Inc. 10 * Unified SMC91x driver by Nicolas Pitre 11 * 12 * Arguments: 13 * io = for the base address 14 * irq = for the IRQ 15 * nowait = 0 for normal wait states, 1 eliminates additional wait states 16 * 17 * original author: 18 * Erik Stahlman <erik@vt.edu> 19 * 20 * hardware multicast code: 21 * Peter Cammaert <pc@denkart.be> 22 * 23 * contributors: 24 * Daris A Nevil <dnevil@snmc.com> 25 * Nicolas Pitre <nico@fluxnic.net> 26 * Russell King <rmk@arm.linux.org.uk> 27 * 28 * History: 29 * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet 30 * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ" 31 * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111 32 * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111 33 * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111 34 * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support 35 * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races, 36 * more bus abstraction, big cleanup, etc. 37 * 29/09/03 Russell King - add driver model support 38 * - ethtool support 39 * - convert to use generic MII interface 40 * - add link up/down notification 41 * - don't try to handle full negotiation in 42 * smc_phy_configure 43 * - clean up (and fix stack overrun) in PHY 44 * MII read/write functions 45 * 22/09/04 Nicolas Pitre big update (see commit log for details) 46 */ 47static const char version[] = 48 "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>"; 49 50/* Debugging level */ 51#ifndef SMC_DEBUG 52#define SMC_DEBUG 0 53#endif 54 55 56#include <linux/module.h> 57#include <linux/kernel.h> 58#include <linux/sched.h> 59#include <linux/delay.h> 60#include <linux/gpio/consumer.h> 61#include <linux/interrupt.h> 62#include <linux/irq.h> 63#include <linux/errno.h> 64#include <linux/ioport.h> 65#include <linux/crc32.h> 66#include <linux/platform_device.h> 67#include <linux/spinlock.h> 68#include <linux/ethtool.h> 69#include <linux/mii.h> 70#include <linux/workqueue.h> 71#include <linux/of.h> 72#include <linux/of_device.h> 73 74#include <linux/netdevice.h> 75#include <linux/etherdevice.h> 76#include <linux/skbuff.h> 77 78#include <asm/io.h> 79 80#include "smc91x.h" 81 82#if defined(CONFIG_ASSABET_NEPONSET) 83#include <mach/assabet.h> 84#include <mach/neponset.h> 85#endif 86 87#ifndef SMC_NOWAIT 88# define SMC_NOWAIT 0 89#endif 90static int nowait = SMC_NOWAIT; 91module_param(nowait, int, 0400); 92MODULE_PARM_DESC(nowait, "set to 1 for no wait state"); 93 94/* 95 * Transmit timeout, default 5 seconds. 96 */ 97static int watchdog = 1000; 98module_param(watchdog, int, 0400); 99MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 100 101MODULE_DESCRIPTION("SMC 91C9x/91C1xxx Ethernet driver"); 102MODULE_LICENSE("GPL"); 103MODULE_ALIAS("platform:smc91x"); 104 105/* 106 * The internal workings of the driver. If you are changing anything 107 * here with the SMC stuff, you should have the datasheet and know 108 * what you are doing. 109 */ 110#define CARDNAME "smc91x" 111 112/* 113 * Use power-down feature of the chip 114 */ 115#define POWER_DOWN 1 116 117/* 118 * Wait time for memory to be free. This probably shouldn't be 119 * tuned that much, as waiting for this means nothing else happens 120 * in the system 121 */ 122#define MEMORY_WAIT_TIME 16 123 124/* 125 * The maximum number of processing loops allowed for each call to the 126 * IRQ handler. 127 */ 128#define MAX_IRQ_LOOPS 8 129 130/* 131 * This selects whether TX packets are sent one by one to the SMC91x internal 132 * memory and throttled until transmission completes. This may prevent 133 * RX overruns a litle by keeping much of the memory free for RX packets 134 * but to the expense of reduced TX throughput and increased IRQ overhead. 135 * Note this is not a cure for a too slow data bus or too high IRQ latency. 136 */ 137#define THROTTLE_TX_PKTS 0 138 139/* 140 * The MII clock high/low times. 2x this number gives the MII clock period 141 * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!) 142 */ 143#define MII_DELAY 1 144 145#define DBG(n, dev, fmt, ...) \ 146 do { \ 147 if (SMC_DEBUG >= (n)) \ 148 netdev_dbg(dev, fmt, ##__VA_ARGS__); \ 149 } while (0) 150 151#define PRINTK(dev, fmt, ...) \ 152 do { \ 153 if (SMC_DEBUG > 0) \ 154 netdev_info(dev, fmt, ##__VA_ARGS__); \ 155 else \ 156 netdev_dbg(dev, fmt, ##__VA_ARGS__); \ 157 } while (0) 158 159#if SMC_DEBUG > 3 160static void PRINT_PKT(u_char *buf, int length) 161{ 162 int i; 163 int remainder; 164 int lines; 165 166 lines = length / 16; 167 remainder = length % 16; 168 169 for (i = 0; i < lines ; i ++) { 170 int cur; 171 printk(KERN_DEBUG); 172 for (cur = 0; cur < 8; cur++) { 173 u_char a, b; 174 a = *buf++; 175 b = *buf++; 176 pr_cont("%02x%02x ", a, b); 177 } 178 pr_cont("\n"); 179 } 180 printk(KERN_DEBUG); 181 for (i = 0; i < remainder/2 ; i++) { 182 u_char a, b; 183 a = *buf++; 184 b = *buf++; 185 pr_cont("%02x%02x ", a, b); 186 } 187 pr_cont("\n"); 188} 189#else 190static inline void PRINT_PKT(u_char *buf, int length) { } 191#endif 192 193 194/* this enables an interrupt in the interrupt mask register */ 195#define SMC_ENABLE_INT(lp, x) do { \ 196 unsigned char mask; \ 197 unsigned long smc_enable_flags; \ 198 spin_lock_irqsave(&lp->lock, smc_enable_flags); \ 199 mask = SMC_GET_INT_MASK(lp); \ 200 mask |= (x); \ 201 SMC_SET_INT_MASK(lp, mask); \ 202 spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \ 203} while (0) 204 205/* this disables an interrupt from the interrupt mask register */ 206#define SMC_DISABLE_INT(lp, x) do { \ 207 unsigned char mask; \ 208 unsigned long smc_disable_flags; \ 209 spin_lock_irqsave(&lp->lock, smc_disable_flags); \ 210 mask = SMC_GET_INT_MASK(lp); \ 211 mask &= ~(x); \ 212 SMC_SET_INT_MASK(lp, mask); \ 213 spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \ 214} while (0) 215 216/* 217 * Wait while MMU is busy. This is usually in the order of a few nanosecs 218 * if at all, but let's avoid deadlocking the system if the hardware 219 * decides to go south. 220 */ 221#define SMC_WAIT_MMU_BUSY(lp) do { \ 222 if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \ 223 unsigned long timeout = jiffies + 2; \ 224 while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \ 225 if (time_after(jiffies, timeout)) { \ 226 netdev_dbg(dev, "timeout %s line %d\n", \ 227 __FILE__, __LINE__); \ 228 break; \ 229 } \ 230 cpu_relax(); \ 231 } \ 232 } \ 233} while (0) 234 235 236/* 237 * this does a soft reset on the device 238 */ 239static void smc_reset(struct net_device *dev) 240{ 241 struct smc_local *lp = netdev_priv(dev); 242 void __iomem *ioaddr = lp->base; 243 unsigned int ctl, cfg; 244 struct sk_buff *pending_skb; 245 246 DBG(2, dev, "%s\n", __func__); 247 248 /* Disable all interrupts, block TX tasklet */ 249 spin_lock_irq(&lp->lock); 250 SMC_SELECT_BANK(lp, 2); 251 SMC_SET_INT_MASK(lp, 0); 252 pending_skb = lp->pending_tx_skb; 253 lp->pending_tx_skb = NULL; 254 spin_unlock_irq(&lp->lock); 255 256 /* free any pending tx skb */ 257 if (pending_skb) { 258 dev_kfree_skb(pending_skb); 259 dev->stats.tx_errors++; 260 dev->stats.tx_aborted_errors++; 261 } 262 263 /* 264 * This resets the registers mostly to defaults, but doesn't 265 * affect EEPROM. That seems unnecessary 266 */ 267 SMC_SELECT_BANK(lp, 0); 268 SMC_SET_RCR(lp, RCR_SOFTRST); 269 270 /* 271 * Setup the Configuration Register 272 * This is necessary because the CONFIG_REG is not affected 273 * by a soft reset 274 */ 275 SMC_SELECT_BANK(lp, 1); 276 277 cfg = CONFIG_DEFAULT; 278 279 /* 280 * Setup for fast accesses if requested. If the card/system 281 * can't handle it then there will be no recovery except for 282 * a hard reset or power cycle 283 */ 284 if (lp->cfg.flags & SMC91X_NOWAIT) 285 cfg |= CONFIG_NO_WAIT; 286 287 /* 288 * Release from possible power-down state 289 * Configuration register is not affected by Soft Reset 290 */ 291 cfg |= CONFIG_EPH_POWER_EN; 292 293 SMC_SET_CONFIG(lp, cfg); 294 295 /* this should pause enough for the chip to be happy */ 296 /* 297 * elaborate? What does the chip _need_? --jgarzik 298 * 299 * This seems to be undocumented, but something the original 300 * driver(s) have always done. Suspect undocumented timing 301 * info/determined empirically. --rmk 302 */ 303 udelay(1); 304 305 /* Disable transmit and receive functionality */ 306 SMC_SELECT_BANK(lp, 0); 307 SMC_SET_RCR(lp, RCR_CLEAR); 308 SMC_SET_TCR(lp, TCR_CLEAR); 309 310 SMC_SELECT_BANK(lp, 1); 311 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE; 312 313 /* 314 * Set the control register to automatically release successfully 315 * transmitted packets, to make the best use out of our limited 316 * memory 317 */ 318 if(!THROTTLE_TX_PKTS) 319 ctl |= CTL_AUTO_RELEASE; 320 else 321 ctl &= ~CTL_AUTO_RELEASE; 322 SMC_SET_CTL(lp, ctl); 323 324 /* Reset the MMU */ 325 SMC_SELECT_BANK(lp, 2); 326 SMC_SET_MMU_CMD(lp, MC_RESET); 327 SMC_WAIT_MMU_BUSY(lp); 328} 329 330/* 331 * Enable Interrupts, Receive, and Transmit 332 */ 333static void smc_enable(struct net_device *dev) 334{ 335 struct smc_local *lp = netdev_priv(dev); 336 void __iomem *ioaddr = lp->base; 337 int mask; 338 339 DBG(2, dev, "%s\n", __func__); 340 341 /* see the header file for options in TCR/RCR DEFAULT */ 342 SMC_SELECT_BANK(lp, 0); 343 SMC_SET_TCR(lp, lp->tcr_cur_mode); 344 SMC_SET_RCR(lp, lp->rcr_cur_mode); 345 346 SMC_SELECT_BANK(lp, 1); 347 SMC_SET_MAC_ADDR(lp, dev->dev_addr); 348 349 /* now, enable interrupts */ 350 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; 351 if (lp->version >= (CHIP_91100 << 4)) 352 mask |= IM_MDINT; 353 SMC_SELECT_BANK(lp, 2); 354 SMC_SET_INT_MASK(lp, mask); 355 356 /* 357 * From this point the register bank must _NOT_ be switched away 358 * to something else than bank 2 without proper locking against 359 * races with any tasklet or interrupt handlers until smc_shutdown() 360 * or smc_reset() is called. 361 */ 362} 363 364/* 365 * this puts the device in an inactive state 366 */ 367static void smc_shutdown(struct net_device *dev) 368{ 369 struct smc_local *lp = netdev_priv(dev); 370 void __iomem *ioaddr = lp->base; 371 struct sk_buff *pending_skb; 372 373 DBG(2, dev, "%s: %s\n", CARDNAME, __func__); 374 375 /* no more interrupts for me */ 376 spin_lock_irq(&lp->lock); 377 SMC_SELECT_BANK(lp, 2); 378 SMC_SET_INT_MASK(lp, 0); 379 pending_skb = lp->pending_tx_skb; 380 lp->pending_tx_skb = NULL; 381 spin_unlock_irq(&lp->lock); 382 dev_kfree_skb(pending_skb); 383 384 /* and tell the card to stay away from that nasty outside world */ 385 SMC_SELECT_BANK(lp, 0); 386 SMC_SET_RCR(lp, RCR_CLEAR); 387 SMC_SET_TCR(lp, TCR_CLEAR); 388 389#ifdef POWER_DOWN 390 /* finally, shut the chip down */ 391 SMC_SELECT_BANK(lp, 1); 392 SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN); 393#endif 394} 395 396/* 397 * This is the procedure to handle the receipt of a packet. 398 */ 399static inline void smc_rcv(struct net_device *dev) 400{ 401 struct smc_local *lp = netdev_priv(dev); 402 void __iomem *ioaddr = lp->base; 403 unsigned int packet_number, status, packet_len; 404 405 DBG(3, dev, "%s\n", __func__); 406 407 packet_number = SMC_GET_RXFIFO(lp); 408 if (unlikely(packet_number & RXFIFO_REMPTY)) { 409 PRINTK(dev, "smc_rcv with nothing on FIFO.\n"); 410 return; 411 } 412 413 /* read from start of packet */ 414 SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC); 415 416 /* First two words are status and packet length */ 417 SMC_GET_PKT_HDR(lp, status, packet_len); 418 packet_len &= 0x07ff; /* mask off top bits */ 419 DBG(2, dev, "RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n", 420 packet_number, status, packet_len, packet_len); 421 422 back: 423 if (unlikely(packet_len < 6 || status & RS_ERRORS)) { 424 if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) { 425 /* accept VLAN packets */ 426 status &= ~RS_TOOLONG; 427 goto back; 428 } 429 if (packet_len < 6) { 430 /* bloody hardware */ 431 netdev_err(dev, "fubar (rxlen %u status %x\n", 432 packet_len, status); 433 status |= RS_TOOSHORT; 434 } 435 SMC_WAIT_MMU_BUSY(lp); 436 SMC_SET_MMU_CMD(lp, MC_RELEASE); 437 dev->stats.rx_errors++; 438 if (status & RS_ALGNERR) 439 dev->stats.rx_frame_errors++; 440 if (status & (RS_TOOSHORT | RS_TOOLONG)) 441 dev->stats.rx_length_errors++; 442 if (status & RS_BADCRC) 443 dev->stats.rx_crc_errors++; 444 } else { 445 struct sk_buff *skb; 446 unsigned char *data; 447 unsigned int data_len; 448 449 /* set multicast stats */ 450 if (status & RS_MULTICAST) 451 dev->stats.multicast++; 452 453 /* 454 * Actual payload is packet_len - 6 (or 5 if odd byte). 455 * We want skb_reserve(2) and the final ctrl word 456 * (2 bytes, possibly containing the payload odd byte). 457 * Furthermore, we add 2 bytes to allow rounding up to 458 * multiple of 4 bytes on 32 bit buses. 459 * Hence packet_len - 6 + 2 + 2 + 2. 460 */ 461 skb = netdev_alloc_skb(dev, packet_len); 462 if (unlikely(skb == NULL)) { 463 SMC_WAIT_MMU_BUSY(lp); 464 SMC_SET_MMU_CMD(lp, MC_RELEASE); 465 dev->stats.rx_dropped++; 466 return; 467 } 468 469 /* Align IP header to 32 bits */ 470 skb_reserve(skb, 2); 471 472 /* BUG: the LAN91C111 rev A never sets this bit. Force it. */ 473 if (lp->version == 0x90) 474 status |= RS_ODDFRAME; 475 476 /* 477 * If odd length: packet_len - 5, 478 * otherwise packet_len - 6. 479 * With the trailing ctrl byte it's packet_len - 4. 480 */ 481 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6); 482 data = skb_put(skb, data_len); 483 SMC_PULL_DATA(lp, data, packet_len - 4); 484 485 SMC_WAIT_MMU_BUSY(lp); 486 SMC_SET_MMU_CMD(lp, MC_RELEASE); 487 488 PRINT_PKT(data, packet_len - 4); 489 490 skb->protocol = eth_type_trans(skb, dev); 491 netif_rx(skb); 492 dev->stats.rx_packets++; 493 dev->stats.rx_bytes += data_len; 494 } 495} 496 497#ifdef CONFIG_SMP 498/* 499 * On SMP we have the following problem: 500 * 501 * A = smc_hardware_send_pkt() 502 * B = smc_hard_start_xmit() 503 * C = smc_interrupt() 504 * 505 * A and B can never be executed simultaneously. However, at least on UP, 506 * it is possible (and even desirable) for C to interrupt execution of 507 * A or B in order to have better RX reliability and avoid overruns. 508 * C, just like A and B, must have exclusive access to the chip and 509 * each of them must lock against any other concurrent access. 510 * Unfortunately this is not possible to have C suspend execution of A or 511 * B taking place on another CPU. On UP this is no an issue since A and B 512 * are run from softirq context and C from hard IRQ context, and there is 513 * no other CPU where concurrent access can happen. 514 * If ever there is a way to force at least B and C to always be executed 515 * on the same CPU then we could use read/write locks to protect against 516 * any other concurrent access and C would always interrupt B. But life 517 * isn't that easy in a SMP world... 518 */ 519#define smc_special_trylock(lock, flags) \ 520({ \ 521 int __ret; \ 522 local_irq_save(flags); \ 523 __ret = spin_trylock(lock); \ 524 if (!__ret) \ 525 local_irq_restore(flags); \ 526 __ret; \ 527}) 528#define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags) 529#define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags) 530#else 531#define smc_special_trylock(lock, flags) ((void)flags, true) 532#define smc_special_lock(lock, flags) do { flags = 0; } while (0) 533#define smc_special_unlock(lock, flags) do { flags = 0; } while (0) 534#endif 535 536/* 537 * This is called to actually send a packet to the chip. 538 */ 539static void smc_hardware_send_pkt(struct tasklet_struct *t) 540{ 541 struct smc_local *lp = from_tasklet(lp, t, tx_task); 542 struct net_device *dev = lp->dev; 543 void __iomem *ioaddr = lp->base; 544 struct sk_buff *skb; 545 unsigned int packet_no, len; 546 unsigned char *buf; 547 unsigned long flags; 548 549 DBG(3, dev, "%s\n", __func__); 550 551 if (!smc_special_trylock(&lp->lock, flags)) { 552 netif_stop_queue(dev); 553 tasklet_schedule(&lp->tx_task); 554 return; 555 } 556 557 skb = lp->pending_tx_skb; 558 if (unlikely(!skb)) { 559 smc_special_unlock(&lp->lock, flags); 560 return; 561 } 562 lp->pending_tx_skb = NULL; 563 564 packet_no = SMC_GET_AR(lp); 565 if (unlikely(packet_no & AR_FAILED)) { 566 netdev_err(dev, "Memory allocation failed.\n"); 567 dev->stats.tx_errors++; 568 dev->stats.tx_fifo_errors++; 569 smc_special_unlock(&lp->lock, flags); 570 goto done; 571 } 572 573 /* point to the beginning of the packet */ 574 SMC_SET_PN(lp, packet_no); 575 SMC_SET_PTR(lp, PTR_AUTOINC); 576 577 buf = skb->data; 578 len = skb->len; 579 DBG(2, dev, "TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n", 580 packet_no, len, len, buf); 581 PRINT_PKT(buf, len); 582 583 /* 584 * Send the packet length (+6 for status words, length, and ctl. 585 * The card will pad to 64 bytes with zeroes if packet is too small. 586 */ 587 SMC_PUT_PKT_HDR(lp, 0, len + 6); 588 589 /* send the actual data */ 590 SMC_PUSH_DATA(lp, buf, len & ~1); 591 592 /* Send final ctl word with the last byte if there is one */ 593 SMC_outw(lp, ((len & 1) ? (0x2000 | buf[len - 1]) : 0), ioaddr, 594 DATA_REG(lp)); 595 596 /* 597 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will 598 * have the effect of having at most one packet queued for TX 599 * in the chip's memory at all time. 600 * 601 * If THROTTLE_TX_PKTS is not set then the queue is stopped only 602 * when memory allocation (MC_ALLOC) does not succeed right away. 603 */ 604 if (THROTTLE_TX_PKTS) 605 netif_stop_queue(dev); 606 607 /* queue the packet for TX */ 608 SMC_SET_MMU_CMD(lp, MC_ENQUEUE); 609 smc_special_unlock(&lp->lock, flags); 610 611 netif_trans_update(dev); 612 dev->stats.tx_packets++; 613 dev->stats.tx_bytes += len; 614 615 SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT); 616 617done: if (!THROTTLE_TX_PKTS) 618 netif_wake_queue(dev); 619 620 dev_consume_skb_any(skb); 621} 622 623/* 624 * Since I am not sure if I will have enough room in the chip's ram 625 * to store the packet, I call this routine which either sends it 626 * now, or set the card to generates an interrupt when ready 627 * for the packet. 628 */ 629static netdev_tx_t 630smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) 631{ 632 struct smc_local *lp = netdev_priv(dev); 633 void __iomem *ioaddr = lp->base; 634 unsigned int numPages, poll_count, status; 635 unsigned long flags; 636 637 DBG(3, dev, "%s\n", __func__); 638 639 BUG_ON(lp->pending_tx_skb != NULL); 640 641 /* 642 * The MMU wants the number of pages to be the number of 256 bytes 643 * 'pages', minus 1 (since a packet can't ever have 0 pages :)) 644 * 645 * The 91C111 ignores the size bits, but earlier models don't. 646 * 647 * Pkt size for allocating is data length +6 (for additional status 648 * words, length and ctl) 649 * 650 * If odd size then last byte is included in ctl word. 651 */ 652 numPages = ((skb->len & ~1) + (6 - 1)) >> 8; 653 if (unlikely(numPages > 7)) { 654 netdev_warn(dev, "Far too big packet error.\n"); 655 dev->stats.tx_errors++; 656 dev->stats.tx_dropped++; 657 dev_kfree_skb_any(skb); 658 return NETDEV_TX_OK; 659 } 660 661 smc_special_lock(&lp->lock, flags); 662 663 /* now, try to allocate the memory */ 664 SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages); 665 666 /* 667 * Poll the chip for a short amount of time in case the 668 * allocation succeeds quickly. 669 */ 670 poll_count = MEMORY_WAIT_TIME; 671 do { 672 status = SMC_GET_INT(lp); 673 if (status & IM_ALLOC_INT) { 674 SMC_ACK_INT(lp, IM_ALLOC_INT); 675 break; 676 } 677 } while (--poll_count); 678 679 smc_special_unlock(&lp->lock, flags); 680 681 lp->pending_tx_skb = skb; 682 if (!poll_count) { 683 /* oh well, wait until the chip finds memory later */ 684 netif_stop_queue(dev); 685 DBG(2, dev, "TX memory allocation deferred.\n"); 686 SMC_ENABLE_INT(lp, IM_ALLOC_INT); 687 } else { 688 /* 689 * Allocation succeeded: push packet to the chip's own memory 690 * immediately. 691 */ 692 smc_hardware_send_pkt(&lp->tx_task); 693 } 694 695 return NETDEV_TX_OK; 696} 697 698/* 699 * This handles a TX interrupt, which is only called when: 700 * - a TX error occurred, or 701 * - CTL_AUTO_RELEASE is not set and TX of a packet completed. 702 */ 703static void smc_tx(struct net_device *dev) 704{ 705 struct smc_local *lp = netdev_priv(dev); 706 void __iomem *ioaddr = lp->base; 707 unsigned int saved_packet, packet_no, tx_status; 708 unsigned int pkt_len __always_unused; 709 710 DBG(3, dev, "%s\n", __func__); 711 712 /* If the TX FIFO is empty then nothing to do */ 713 packet_no = SMC_GET_TXFIFO(lp); 714 if (unlikely(packet_no & TXFIFO_TEMPTY)) { 715 PRINTK(dev, "smc_tx with nothing on FIFO.\n"); 716 return; 717 } 718 719 /* select packet to read from */ 720 saved_packet = SMC_GET_PN(lp); 721 SMC_SET_PN(lp, packet_no); 722 723 /* read the first word (status word) from this packet */ 724 SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ); 725 SMC_GET_PKT_HDR(lp, tx_status, pkt_len); 726 DBG(2, dev, "TX STATUS 0x%04x PNR 0x%02x\n", 727 tx_status, packet_no); 728 729 if (!(tx_status & ES_TX_SUC)) 730 dev->stats.tx_errors++; 731 732 if (tx_status & ES_LOSTCARR) 733 dev->stats.tx_carrier_errors++; 734 735 if (tx_status & (ES_LATCOL | ES_16COL)) { 736 PRINTK(dev, "%s occurred on last xmit\n", 737 (tx_status & ES_LATCOL) ? 738 "late collision" : "too many collisions"); 739 dev->stats.tx_window_errors++; 740 if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) { 741 netdev_info(dev, "unexpectedly large number of bad collisions. Please check duplex setting.\n"); 742 } 743 } 744 745 /* kill the packet */ 746 SMC_WAIT_MMU_BUSY(lp); 747 SMC_SET_MMU_CMD(lp, MC_FREEPKT); 748 749 /* Don't restore Packet Number Reg until busy bit is cleared */ 750 SMC_WAIT_MMU_BUSY(lp); 751 SMC_SET_PN(lp, saved_packet); 752 753 /* re-enable transmit */ 754 SMC_SELECT_BANK(lp, 0); 755 SMC_SET_TCR(lp, lp->tcr_cur_mode); 756 SMC_SELECT_BANK(lp, 2); 757} 758 759 760/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ 761 762static void smc_mii_out(struct net_device *dev, unsigned int val, int bits) 763{ 764 struct smc_local *lp = netdev_priv(dev); 765 void __iomem *ioaddr = lp->base; 766 unsigned int mii_reg, mask; 767 768 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); 769 mii_reg |= MII_MDOE; 770 771 for (mask = 1 << (bits - 1); mask; mask >>= 1) { 772 if (val & mask) 773 mii_reg |= MII_MDO; 774 else 775 mii_reg &= ~MII_MDO; 776 777 SMC_SET_MII(lp, mii_reg); 778 udelay(MII_DELAY); 779 SMC_SET_MII(lp, mii_reg | MII_MCLK); 780 udelay(MII_DELAY); 781 } 782} 783 784static unsigned int smc_mii_in(struct net_device *dev, int bits) 785{ 786 struct smc_local *lp = netdev_priv(dev); 787 void __iomem *ioaddr = lp->base; 788 unsigned int mii_reg, mask, val; 789 790 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); 791 SMC_SET_MII(lp, mii_reg); 792 793 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { 794 if (SMC_GET_MII(lp) & MII_MDI) 795 val |= mask; 796 797 SMC_SET_MII(lp, mii_reg); 798 udelay(MII_DELAY); 799 SMC_SET_MII(lp, mii_reg | MII_MCLK); 800 udelay(MII_DELAY); 801 } 802 803 return val; 804} 805 806/* 807 * Reads a register from the MII Management serial interface 808 */ 809static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg) 810{ 811 struct smc_local *lp = netdev_priv(dev); 812 void __iomem *ioaddr = lp->base; 813 unsigned int phydata; 814 815 SMC_SELECT_BANK(lp, 3); 816 817 /* Idle - 32 ones */ 818 smc_mii_out(dev, 0xffffffff, 32); 819 820 /* Start code (01) + read (10) + phyaddr + phyreg */ 821 smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); 822 823 /* Turnaround (2bits) + phydata */ 824 phydata = smc_mii_in(dev, 18); 825 826 /* Return to idle state */ 827 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); 828 829 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 830 __func__, phyaddr, phyreg, phydata); 831 832 SMC_SELECT_BANK(lp, 2); 833 return phydata; 834} 835 836/* 837 * Writes a register to the MII Management serial interface 838 */ 839static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, 840 int phydata) 841{ 842 struct smc_local *lp = netdev_priv(dev); 843 void __iomem *ioaddr = lp->base; 844 845 SMC_SELECT_BANK(lp, 3); 846 847 /* Idle - 32 ones */ 848 smc_mii_out(dev, 0xffffffff, 32); 849 850 /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */ 851 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); 852 853 /* Return to idle state */ 854 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); 855 856 DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 857 __func__, phyaddr, phyreg, phydata); 858 859 SMC_SELECT_BANK(lp, 2); 860} 861 862/* 863 * Finds and reports the PHY address 864 */ 865static void smc_phy_detect(struct net_device *dev) 866{ 867 struct smc_local *lp = netdev_priv(dev); 868 int phyaddr; 869 870 DBG(2, dev, "%s\n", __func__); 871 872 lp->phy_type = 0; 873 874 /* 875 * Scan all 32 PHY addresses if necessary, starting at 876 * PHY#1 to PHY#31, and then PHY#0 last. 877 */ 878 for (phyaddr = 1; phyaddr < 33; ++phyaddr) { 879 unsigned int id1, id2; 880 881 /* Read the PHY identifiers */ 882 id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1); 883 id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2); 884 885 DBG(3, dev, "phy_id1=0x%x, phy_id2=0x%x\n", 886 id1, id2); 887 888 /* Make sure it is a valid identifier */ 889 if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && 890 id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { 891 /* Save the PHY's address */ 892 lp->mii.phy_id = phyaddr & 31; 893 lp->phy_type = id1 << 16 | id2; 894 break; 895 } 896 } 897} 898 899/* 900 * Sets the PHY to a configuration as determined by the user 901 */ 902static int smc_phy_fixed(struct net_device *dev) 903{ 904 struct smc_local *lp = netdev_priv(dev); 905 void __iomem *ioaddr = lp->base; 906 int phyaddr = lp->mii.phy_id; 907 int bmcr, cfg1; 908 909 DBG(3, dev, "%s\n", __func__); 910 911 /* Enter Link Disable state */ 912 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); 913 cfg1 |= PHY_CFG1_LNKDIS; 914 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); 915 916 /* 917 * Set our fixed capabilities 918 * Disable auto-negotiation 919 */ 920 bmcr = 0; 921 922 if (lp->ctl_rfduplx) 923 bmcr |= BMCR_FULLDPLX; 924 925 if (lp->ctl_rspeed == 100) 926 bmcr |= BMCR_SPEED100; 927 928 /* Write our capabilities to the phy control register */ 929 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); 930 931 /* Re-Configure the Receive/Phy Control register */ 932 SMC_SELECT_BANK(lp, 0); 933 SMC_SET_RPC(lp, lp->rpc_cur_mode); 934 SMC_SELECT_BANK(lp, 2); 935 936 return 1; 937} 938 939/** 940 * smc_phy_reset - reset the phy 941 * @dev: net device 942 * @phy: phy address 943 * 944 * Issue a software reset for the specified PHY and 945 * wait up to 100ms for the reset to complete. We should 946 * not access the PHY for 50ms after issuing the reset. 947 * 948 * The time to wait appears to be dependent on the PHY. 949 * 950 * Must be called with lp->lock locked. 951 */ 952static int smc_phy_reset(struct net_device *dev, int phy) 953{ 954 struct smc_local *lp = netdev_priv(dev); 955 unsigned int bmcr; 956 int timeout; 957 958 smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET); 959 960 for (timeout = 2; timeout; timeout--) { 961 spin_unlock_irq(&lp->lock); 962 msleep(50); 963 spin_lock_irq(&lp->lock); 964 965 bmcr = smc_phy_read(dev, phy, MII_BMCR); 966 if (!(bmcr & BMCR_RESET)) 967 break; 968 } 969 970 return bmcr & BMCR_RESET; 971} 972 973/** 974 * smc_phy_powerdown - powerdown phy 975 * @dev: net device 976 * 977 * Power down the specified PHY 978 */ 979static void smc_phy_powerdown(struct net_device *dev) 980{ 981 struct smc_local *lp = netdev_priv(dev); 982 unsigned int bmcr; 983 int phy = lp->mii.phy_id; 984 985 if (lp->phy_type == 0) 986 return; 987 988 /* We need to ensure that no calls to smc_phy_configure are 989 pending. 990 */ 991 cancel_work_sync(&lp->phy_configure); 992 993 bmcr = smc_phy_read(dev, phy, MII_BMCR); 994 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN); 995} 996 997/** 998 * smc_phy_check_media - check the media status and adjust TCR 999 * @dev: net device 1000 * @init: set true for initialisation 1001 * 1002 * Select duplex mode depending on negotiation state. This 1003 * also updates our carrier state. 1004 */ 1005static void smc_phy_check_media(struct net_device *dev, int init) 1006{ 1007 struct smc_local *lp = netdev_priv(dev); 1008 void __iomem *ioaddr = lp->base; 1009 1010 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { 1011 /* duplex state has changed */ 1012 if (lp->mii.full_duplex) { 1013 lp->tcr_cur_mode |= TCR_SWFDUP; 1014 } else { 1015 lp->tcr_cur_mode &= ~TCR_SWFDUP; 1016 } 1017 1018 SMC_SELECT_BANK(lp, 0); 1019 SMC_SET_TCR(lp, lp->tcr_cur_mode); 1020 } 1021} 1022 1023/* 1024 * Configures the specified PHY through the MII management interface 1025 * using Autonegotiation. 1026 * Calls smc_phy_fixed() if the user has requested a certain config. 1027 * If RPC ANEG bit is set, the media selection is dependent purely on 1028 * the selection by the MII (either in the MII BMCR reg or the result 1029 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection 1030 * is controlled by the RPC SPEED and RPC DPLX bits. 1031 */ 1032static void smc_phy_configure(struct work_struct *work) 1033{ 1034 struct smc_local *lp = 1035 container_of(work, struct smc_local, phy_configure); 1036 struct net_device *dev = lp->dev; 1037 void __iomem *ioaddr = lp->base; 1038 int phyaddr = lp->mii.phy_id; 1039 int my_phy_caps; /* My PHY capabilities */ 1040 int my_ad_caps; /* My Advertised capabilities */ 1041 1042 DBG(3, dev, "smc_program_phy()\n"); 1043 1044 spin_lock_irq(&lp->lock); 1045 1046 /* 1047 * We should not be called if phy_type is zero. 1048 */ 1049 if (lp->phy_type == 0) 1050 goto smc_phy_configure_exit; 1051 1052 if (smc_phy_reset(dev, phyaddr)) { 1053 netdev_info(dev, "PHY reset timed out\n"); 1054 goto smc_phy_configure_exit; 1055 } 1056 1057 /* 1058 * Enable PHY Interrupts (for register 18) 1059 * Interrupts listed here are disabled 1060 */ 1061 smc_phy_write(dev, phyaddr, PHY_MASK_REG, 1062 PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | 1063 PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | 1064 PHY_INT_SPDDET | PHY_INT_DPLXDET); 1065 1066 /* Configure the Receive/Phy Control register */ 1067 SMC_SELECT_BANK(lp, 0); 1068 SMC_SET_RPC(lp, lp->rpc_cur_mode); 1069 1070 /* If the user requested no auto neg, then go set his request */ 1071 if (lp->mii.force_media) { 1072 smc_phy_fixed(dev); 1073 goto smc_phy_configure_exit; 1074 } 1075 1076 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */ 1077 my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR); 1078 1079 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { 1080 netdev_info(dev, "Auto negotiation NOT supported\n"); 1081 smc_phy_fixed(dev); 1082 goto smc_phy_configure_exit; 1083 } 1084 1085 my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */ 1086 1087 if (my_phy_caps & BMSR_100BASE4) 1088 my_ad_caps |= ADVERTISE_100BASE4; 1089 if (my_phy_caps & BMSR_100FULL) 1090 my_ad_caps |= ADVERTISE_100FULL; 1091 if (my_phy_caps & BMSR_100HALF) 1092 my_ad_caps |= ADVERTISE_100HALF; 1093 if (my_phy_caps & BMSR_10FULL) 1094 my_ad_caps |= ADVERTISE_10FULL; 1095 if (my_phy_caps & BMSR_10HALF) 1096 my_ad_caps |= ADVERTISE_10HALF; 1097 1098 /* Disable capabilities not selected by our user */ 1099 if (lp->ctl_rspeed != 100) 1100 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF); 1101 1102 if (!lp->ctl_rfduplx) 1103 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); 1104 1105 /* Update our Auto-Neg Advertisement Register */ 1106 smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps); 1107 lp->mii.advertising = my_ad_caps; 1108 1109 /* 1110 * Read the register back. Without this, it appears that when 1111 * auto-negotiation is restarted, sometimes it isn't ready and 1112 * the link does not come up. 1113 */ 1114 smc_phy_read(dev, phyaddr, MII_ADVERTISE); 1115 1116 DBG(2, dev, "phy caps=%x\n", my_phy_caps); 1117 DBG(2, dev, "phy advertised caps=%x\n", my_ad_caps); 1118 1119 /* Restart auto-negotiation process in order to advertise my caps */ 1120 smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); 1121 1122 smc_phy_check_media(dev, 1); 1123 1124smc_phy_configure_exit: 1125 SMC_SELECT_BANK(lp, 2); 1126 spin_unlock_irq(&lp->lock); 1127} 1128 1129/* 1130 * smc_phy_interrupt 1131 * 1132 * Purpose: Handle interrupts relating to PHY register 18. This is 1133 * called from the "hard" interrupt handler under our private spinlock. 1134 */ 1135static void smc_phy_interrupt(struct net_device *dev) 1136{ 1137 struct smc_local *lp = netdev_priv(dev); 1138 int phyaddr = lp->mii.phy_id; 1139 int phy18; 1140 1141 DBG(2, dev, "%s\n", __func__); 1142 1143 if (lp->phy_type == 0) 1144 return; 1145 1146 for(;;) { 1147 smc_phy_check_media(dev, 0); 1148 1149 /* Read PHY Register 18, Status Output */ 1150 phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG); 1151 if ((phy18 & PHY_INT_INT) == 0) 1152 break; 1153 } 1154} 1155 1156/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/ 1157 1158static void smc_10bt_check_media(struct net_device *dev, int init) 1159{ 1160 struct smc_local *lp = netdev_priv(dev); 1161 void __iomem *ioaddr = lp->base; 1162 unsigned int old_carrier, new_carrier; 1163 1164 old_carrier = netif_carrier_ok(dev) ? 1 : 0; 1165 1166 SMC_SELECT_BANK(lp, 0); 1167 new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0; 1168 SMC_SELECT_BANK(lp, 2); 1169 1170 if (init || (old_carrier != new_carrier)) { 1171 if (!new_carrier) { 1172 netif_carrier_off(dev); 1173 } else { 1174 netif_carrier_on(dev); 1175 } 1176 if (netif_msg_link(lp)) 1177 netdev_info(dev, "link %s\n", 1178 new_carrier ? "up" : "down"); 1179 } 1180} 1181 1182static void smc_eph_interrupt(struct net_device *dev) 1183{ 1184 struct smc_local *lp = netdev_priv(dev); 1185 void __iomem *ioaddr = lp->base; 1186 unsigned int ctl; 1187 1188 smc_10bt_check_media(dev, 0); 1189 1190 SMC_SELECT_BANK(lp, 1); 1191 ctl = SMC_GET_CTL(lp); 1192 SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE); 1193 SMC_SET_CTL(lp, ctl); 1194 SMC_SELECT_BANK(lp, 2); 1195} 1196 1197/* 1198 * This is the main routine of the driver, to handle the device when 1199 * it needs some attention. 1200 */ 1201static irqreturn_t smc_interrupt(int irq, void *dev_id) 1202{ 1203 struct net_device *dev = dev_id; 1204 struct smc_local *lp = netdev_priv(dev); 1205 void __iomem *ioaddr = lp->base; 1206 int status, mask, timeout, card_stats; 1207 int saved_pointer; 1208 1209 DBG(3, dev, "%s\n", __func__); 1210 1211 spin_lock(&lp->lock); 1212 1213 /* A preamble may be used when there is a potential race 1214 * between the interruptible transmit functions and this 1215 * ISR. */ 1216 SMC_INTERRUPT_PREAMBLE; 1217 1218 saved_pointer = SMC_GET_PTR(lp); 1219 mask = SMC_GET_INT_MASK(lp); 1220 SMC_SET_INT_MASK(lp, 0); 1221 1222 /* set a timeout value, so I don't stay here forever */ 1223 timeout = MAX_IRQ_LOOPS; 1224 1225 do { 1226 status = SMC_GET_INT(lp); 1227 1228 DBG(2, dev, "INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", 1229 status, mask, 1230 ({ int meminfo; SMC_SELECT_BANK(lp, 0); 1231 meminfo = SMC_GET_MIR(lp); 1232 SMC_SELECT_BANK(lp, 2); meminfo; }), 1233 SMC_GET_FIFO(lp)); 1234 1235 status &= mask; 1236 if (!status) 1237 break; 1238 1239 if (status & IM_TX_INT) { 1240 /* do this before RX as it will free memory quickly */ 1241 DBG(3, dev, "TX int\n"); 1242 smc_tx(dev); 1243 SMC_ACK_INT(lp, IM_TX_INT); 1244 if (THROTTLE_TX_PKTS) 1245 netif_wake_queue(dev); 1246 } else if (status & IM_RCV_INT) { 1247 DBG(3, dev, "RX irq\n"); 1248 smc_rcv(dev); 1249 } else if (status & IM_ALLOC_INT) { 1250 DBG(3, dev, "Allocation irq\n"); 1251 tasklet_hi_schedule(&lp->tx_task); 1252 mask &= ~IM_ALLOC_INT; 1253 } else if (status & IM_TX_EMPTY_INT) { 1254 DBG(3, dev, "TX empty\n"); 1255 mask &= ~IM_TX_EMPTY_INT; 1256 1257 /* update stats */ 1258 SMC_SELECT_BANK(lp, 0); 1259 card_stats = SMC_GET_COUNTER(lp); 1260 SMC_SELECT_BANK(lp, 2); 1261 1262 /* single collisions */ 1263 dev->stats.collisions += card_stats & 0xF; 1264 card_stats >>= 4; 1265 1266 /* multiple collisions */ 1267 dev->stats.collisions += card_stats & 0xF; 1268 } else if (status & IM_RX_OVRN_INT) { 1269 DBG(1, dev, "RX overrun (EPH_ST 0x%04x)\n", 1270 ({ int eph_st; SMC_SELECT_BANK(lp, 0); 1271 eph_st = SMC_GET_EPH_STATUS(lp); 1272 SMC_SELECT_BANK(lp, 2); eph_st; })); 1273 SMC_ACK_INT(lp, IM_RX_OVRN_INT); 1274 dev->stats.rx_errors++; 1275 dev->stats.rx_fifo_errors++; 1276 } else if (status & IM_EPH_INT) { 1277 smc_eph_interrupt(dev); 1278 } else if (status & IM_MDINT) { 1279 SMC_ACK_INT(lp, IM_MDINT); 1280 smc_phy_interrupt(dev); 1281 } else if (status & IM_ERCV_INT) { 1282 SMC_ACK_INT(lp, IM_ERCV_INT); 1283 PRINTK(dev, "UNSUPPORTED: ERCV INTERRUPT\n"); 1284 } 1285 } while (--timeout); 1286 1287 /* restore register states */ 1288 SMC_SET_PTR(lp, saved_pointer); 1289 SMC_SET_INT_MASK(lp, mask); 1290 spin_unlock(&lp->lock); 1291 1292#ifndef CONFIG_NET_POLL_CONTROLLER 1293 if (timeout == MAX_IRQ_LOOPS) 1294 PRINTK(dev, "spurious interrupt (mask = 0x%02x)\n", 1295 mask); 1296#endif 1297 DBG(3, dev, "Interrupt done (%d loops)\n", 1298 MAX_IRQ_LOOPS - timeout); 1299 1300 /* 1301 * We return IRQ_HANDLED unconditionally here even if there was 1302 * nothing to do. There is a possibility that a packet might 1303 * get enqueued into the chip right after TX_EMPTY_INT is raised 1304 * but just before the CPU acknowledges the IRQ. 1305 * Better take an unneeded IRQ in some occasions than complexifying 1306 * the code for all cases. 1307 */ 1308 return IRQ_HANDLED; 1309} 1310 1311#ifdef CONFIG_NET_POLL_CONTROLLER 1312/* 1313 * Polling receive - used by netconsole and other diagnostic tools 1314 * to allow network i/o with interrupts disabled. 1315 */ 1316static void smc_poll_controller(struct net_device *dev) 1317{ 1318 disable_irq(dev->irq); 1319 smc_interrupt(dev->irq, dev); 1320 enable_irq(dev->irq); 1321} 1322#endif 1323 1324/* Our watchdog timed out. Called by the networking layer */ 1325static void smc_timeout(struct net_device *dev, unsigned int txqueue) 1326{ 1327 struct smc_local *lp = netdev_priv(dev); 1328 void __iomem *ioaddr = lp->base; 1329 int status, mask, eph_st, meminfo, fifo; 1330 1331 DBG(2, dev, "%s\n", __func__); 1332 1333 spin_lock_irq(&lp->lock); 1334 status = SMC_GET_INT(lp); 1335 mask = SMC_GET_INT_MASK(lp); 1336 fifo = SMC_GET_FIFO(lp); 1337 SMC_SELECT_BANK(lp, 0); 1338 eph_st = SMC_GET_EPH_STATUS(lp); 1339 meminfo = SMC_GET_MIR(lp); 1340 SMC_SELECT_BANK(lp, 2); 1341 spin_unlock_irq(&lp->lock); 1342 PRINTK(dev, "TX timeout (INT 0x%02x INTMASK 0x%02x MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n", 1343 status, mask, meminfo, fifo, eph_st); 1344 1345 smc_reset(dev); 1346 smc_enable(dev); 1347 1348 /* 1349 * Reconfiguring the PHY doesn't seem like a bad idea here, but 1350 * smc_phy_configure() calls msleep() which calls schedule_timeout() 1351 * which calls schedule(). Hence we use a work queue. 1352 */ 1353 if (lp->phy_type != 0) 1354 schedule_work(&lp->phy_configure); 1355 1356 /* We can accept TX packets again */ 1357 netif_trans_update(dev); /* prevent tx timeout */ 1358 netif_wake_queue(dev); 1359} 1360 1361/* 1362 * This routine will, depending on the values passed to it, 1363 * either make it accept multicast packets, go into 1364 * promiscuous mode (for TCPDUMP and cousins) or accept 1365 * a select set of multicast packets 1366 */ 1367static void smc_set_multicast_list(struct net_device *dev) 1368{ 1369 struct smc_local *lp = netdev_priv(dev); 1370 void __iomem *ioaddr = lp->base; 1371 unsigned char multicast_table[8]; 1372 int update_multicast = 0; 1373 1374 DBG(2, dev, "%s\n", __func__); 1375 1376 if (dev->flags & IFF_PROMISC) { 1377 DBG(2, dev, "RCR_PRMS\n"); 1378 lp->rcr_cur_mode |= RCR_PRMS; 1379 } 1380 1381/* BUG? I never disable promiscuous mode if multicasting was turned on. 1382 Now, I turn off promiscuous mode, but I don't do anything to multicasting 1383 when promiscuous mode is turned on. 1384*/ 1385 1386 /* 1387 * Here, I am setting this to accept all multicast packets. 1388 * I don't need to zero the multicast table, because the flag is 1389 * checked before the table is 1390 */ 1391 else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) { 1392 DBG(2, dev, "RCR_ALMUL\n"); 1393 lp->rcr_cur_mode |= RCR_ALMUL; 1394 } 1395 1396 /* 1397 * This sets the internal hardware table to filter out unwanted 1398 * multicast packets before they take up memory. 1399 * 1400 * The SMC chip uses a hash table where the high 6 bits of the CRC of 1401 * address are the offset into the table. If that bit is 1, then the 1402 * multicast packet is accepted. Otherwise, it's dropped silently. 1403 * 1404 * To use the 6 bits as an offset into the table, the high 3 bits are 1405 * the number of the 8 bit register, while the low 3 bits are the bit 1406 * within that register. 1407 */ 1408 else if (!netdev_mc_empty(dev)) { 1409 struct netdev_hw_addr *ha; 1410 1411 /* table for flipping the order of 3 bits */ 1412 static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7}; 1413 1414 /* start with a table of all zeros: reject all */ 1415 memset(multicast_table, 0, sizeof(multicast_table)); 1416 1417 netdev_for_each_mc_addr(ha, dev) { 1418 int position; 1419 1420 /* only use the low order bits */ 1421 position = crc32_le(~0, ha->addr, 6) & 0x3f; 1422 1423 /* do some messy swapping to put the bit in the right spot */ 1424 multicast_table[invert3[position&7]] |= 1425 (1<<invert3[(position>>3)&7]); 1426 } 1427 1428 /* be sure I get rid of flags I might have set */ 1429 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); 1430 1431 /* now, the table can be loaded into the chipset */ 1432 update_multicast = 1; 1433 } else { 1434 DBG(2, dev, "~(RCR_PRMS|RCR_ALMUL)\n"); 1435 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); 1436 1437 /* 1438 * since I'm disabling all multicast entirely, I need to 1439 * clear the multicast list 1440 */ 1441 memset(multicast_table, 0, sizeof(multicast_table)); 1442 update_multicast = 1; 1443 } 1444 1445 spin_lock_irq(&lp->lock); 1446 SMC_SELECT_BANK(lp, 0); 1447 SMC_SET_RCR(lp, lp->rcr_cur_mode); 1448 if (update_multicast) { 1449 SMC_SELECT_BANK(lp, 3); 1450 SMC_SET_MCAST(lp, multicast_table); 1451 } 1452 SMC_SELECT_BANK(lp, 2); 1453 spin_unlock_irq(&lp->lock); 1454} 1455 1456 1457/* 1458 * Open and Initialize the board 1459 * 1460 * Set up everything, reset the card, etc.. 1461 */ 1462static int 1463smc_open(struct net_device *dev) 1464{ 1465 struct smc_local *lp = netdev_priv(dev); 1466 1467 DBG(2, dev, "%s\n", __func__); 1468 1469 /* Setup the default Register Modes */ 1470 lp->tcr_cur_mode = TCR_DEFAULT; 1471 lp->rcr_cur_mode = RCR_DEFAULT; 1472 lp->rpc_cur_mode = RPC_DEFAULT | 1473 lp->cfg.leda << RPC_LSXA_SHFT | 1474 lp->cfg.ledb << RPC_LSXB_SHFT; 1475 1476 /* 1477 * If we are not using a MII interface, we need to 1478 * monitor our own carrier signal to detect faults. 1479 */ 1480 if (lp->phy_type == 0) 1481 lp->tcr_cur_mode |= TCR_MON_CSN; 1482 1483 /* reset the hardware */ 1484 smc_reset(dev); 1485 smc_enable(dev); 1486 1487 /* Configure the PHY, initialize the link state */ 1488 if (lp->phy_type != 0) 1489 smc_phy_configure(&lp->phy_configure); 1490 else { 1491 spin_lock_irq(&lp->lock); 1492 smc_10bt_check_media(dev, 1); 1493 spin_unlock_irq(&lp->lock); 1494 } 1495 1496 netif_start_queue(dev); 1497 return 0; 1498} 1499 1500/* 1501 * smc_close 1502 * 1503 * this makes the board clean up everything that it can 1504 * and not talk to the outside world. Caused by 1505 * an 'ifconfig ethX down' 1506 */ 1507static int smc_close(struct net_device *dev) 1508{ 1509 struct smc_local *lp = netdev_priv(dev); 1510 1511 DBG(2, dev, "%s\n", __func__); 1512 1513 netif_stop_queue(dev); 1514 netif_carrier_off(dev); 1515 1516 /* clear everything */ 1517 smc_shutdown(dev); 1518 tasklet_kill(&lp->tx_task); 1519 smc_phy_powerdown(dev); 1520 return 0; 1521} 1522 1523/* 1524 * Ethtool support 1525 */ 1526static int 1527smc_ethtool_get_link_ksettings(struct net_device *dev, 1528 struct ethtool_link_ksettings *cmd) 1529{ 1530 struct smc_local *lp = netdev_priv(dev); 1531 1532 if (lp->phy_type != 0) { 1533 spin_lock_irq(&lp->lock); 1534 mii_ethtool_get_link_ksettings(&lp->mii, cmd); 1535 spin_unlock_irq(&lp->lock); 1536 } else { 1537 u32 supported = SUPPORTED_10baseT_Half | 1538 SUPPORTED_10baseT_Full | 1539 SUPPORTED_TP | SUPPORTED_AUI; 1540 1541 if (lp->ctl_rspeed == 10) 1542 cmd->base.speed = SPEED_10; 1543 else if (lp->ctl_rspeed == 100) 1544 cmd->base.speed = SPEED_100; 1545 1546 cmd->base.autoneg = AUTONEG_DISABLE; 1547 cmd->base.port = 0; 1548 cmd->base.duplex = lp->tcr_cur_mode & TCR_SWFDUP ? 1549 DUPLEX_FULL : DUPLEX_HALF; 1550 1551 ethtool_convert_legacy_u32_to_link_mode( 1552 cmd->link_modes.supported, supported); 1553 } 1554 1555 return 0; 1556} 1557 1558static int 1559smc_ethtool_set_link_ksettings(struct net_device *dev, 1560 const struct ethtool_link_ksettings *cmd) 1561{ 1562 struct smc_local *lp = netdev_priv(dev); 1563 int ret; 1564 1565 if (lp->phy_type != 0) { 1566 spin_lock_irq(&lp->lock); 1567 ret = mii_ethtool_set_link_ksettings(&lp->mii, cmd); 1568 spin_unlock_irq(&lp->lock); 1569 } else { 1570 if (cmd->base.autoneg != AUTONEG_DISABLE || 1571 cmd->base.speed != SPEED_10 || 1572 (cmd->base.duplex != DUPLEX_HALF && 1573 cmd->base.duplex != DUPLEX_FULL) || 1574 (cmd->base.port != PORT_TP && cmd->base.port != PORT_AUI)) 1575 return -EINVAL; 1576 1577// lp->port = cmd->base.port; 1578 lp->ctl_rfduplx = cmd->base.duplex == DUPLEX_FULL; 1579 1580// if (netif_running(dev)) 1581// smc_set_port(dev); 1582 1583 ret = 0; 1584 } 1585 1586 return ret; 1587} 1588 1589static void 1590smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1591{ 1592 strscpy(info->driver, CARDNAME, sizeof(info->driver)); 1593 strscpy(info->version, version, sizeof(info->version)); 1594 strscpy(info->bus_info, dev_name(dev->dev.parent), 1595 sizeof(info->bus_info)); 1596} 1597 1598static int smc_ethtool_nwayreset(struct net_device *dev) 1599{ 1600 struct smc_local *lp = netdev_priv(dev); 1601 int ret = -EINVAL; 1602 1603 if (lp->phy_type != 0) { 1604 spin_lock_irq(&lp->lock); 1605 ret = mii_nway_restart(&lp->mii); 1606 spin_unlock_irq(&lp->lock); 1607 } 1608 1609 return ret; 1610} 1611 1612static u32 smc_ethtool_getmsglevel(struct net_device *dev) 1613{ 1614 struct smc_local *lp = netdev_priv(dev); 1615 return lp->msg_enable; 1616} 1617 1618static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level) 1619{ 1620 struct smc_local *lp = netdev_priv(dev); 1621 lp->msg_enable = level; 1622} 1623 1624static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word) 1625{ 1626 u16 ctl; 1627 struct smc_local *lp = netdev_priv(dev); 1628 void __iomem *ioaddr = lp->base; 1629 1630 spin_lock_irq(&lp->lock); 1631 /* load word into GP register */ 1632 SMC_SELECT_BANK(lp, 1); 1633 SMC_SET_GP(lp, word); 1634 /* set the address to put the data in EEPROM */ 1635 SMC_SELECT_BANK(lp, 2); 1636 SMC_SET_PTR(lp, addr); 1637 /* tell it to write */ 1638 SMC_SELECT_BANK(lp, 1); 1639 ctl = SMC_GET_CTL(lp); 1640 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE)); 1641 /* wait for it to finish */ 1642 do { 1643 udelay(1); 1644 } while (SMC_GET_CTL(lp) & CTL_STORE); 1645 /* clean up */ 1646 SMC_SET_CTL(lp, ctl); 1647 SMC_SELECT_BANK(lp, 2); 1648 spin_unlock_irq(&lp->lock); 1649 return 0; 1650} 1651 1652static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word) 1653{ 1654 u16 ctl; 1655 struct smc_local *lp = netdev_priv(dev); 1656 void __iomem *ioaddr = lp->base; 1657 1658 spin_lock_irq(&lp->lock); 1659 /* set the EEPROM address to get the data from */ 1660 SMC_SELECT_BANK(lp, 2); 1661 SMC_SET_PTR(lp, addr | PTR_READ); 1662 /* tell it to load */ 1663 SMC_SELECT_BANK(lp, 1); 1664 SMC_SET_GP(lp, 0xffff); /* init to known */ 1665 ctl = SMC_GET_CTL(lp); 1666 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD)); 1667 /* wait for it to finish */ 1668 do { 1669 udelay(1); 1670 } while (SMC_GET_CTL(lp) & CTL_RELOAD); 1671 /* read word from GP register */ 1672 *word = SMC_GET_GP(lp); 1673 /* clean up */ 1674 SMC_SET_CTL(lp, ctl); 1675 SMC_SELECT_BANK(lp, 2); 1676 spin_unlock_irq(&lp->lock); 1677 return 0; 1678} 1679 1680static int smc_ethtool_geteeprom_len(struct net_device *dev) 1681{ 1682 return 0x23 * 2; 1683} 1684 1685static int smc_ethtool_geteeprom(struct net_device *dev, 1686 struct ethtool_eeprom *eeprom, u8 *data) 1687{ 1688 int i; 1689 int imax; 1690 1691 DBG(1, dev, "Reading %d bytes at %d(0x%x)\n", 1692 eeprom->len, eeprom->offset, eeprom->offset); 1693 imax = smc_ethtool_geteeprom_len(dev); 1694 for (i = 0; i < eeprom->len; i += 2) { 1695 int ret; 1696 u16 wbuf; 1697 int offset = i + eeprom->offset; 1698 if (offset > imax) 1699 break; 1700 ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf); 1701 if (ret != 0) 1702 return ret; 1703 DBG(2, dev, "Read 0x%x from 0x%x\n", wbuf, offset >> 1); 1704 data[i] = (wbuf >> 8) & 0xff; 1705 data[i+1] = wbuf & 0xff; 1706 } 1707 return 0; 1708} 1709 1710static int smc_ethtool_seteeprom(struct net_device *dev, 1711 struct ethtool_eeprom *eeprom, u8 *data) 1712{ 1713 int i; 1714 int imax; 1715 1716 DBG(1, dev, "Writing %d bytes to %d(0x%x)\n", 1717 eeprom->len, eeprom->offset, eeprom->offset); 1718 imax = smc_ethtool_geteeprom_len(dev); 1719 for (i = 0; i < eeprom->len; i += 2) { 1720 int ret; 1721 u16 wbuf; 1722 int offset = i + eeprom->offset; 1723 if (offset > imax) 1724 break; 1725 wbuf = (data[i] << 8) | data[i + 1]; 1726 DBG(2, dev, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1); 1727 ret = smc_write_eeprom_word(dev, offset >> 1, wbuf); 1728 if (ret != 0) 1729 return ret; 1730 } 1731 return 0; 1732} 1733 1734 1735static const struct ethtool_ops smc_ethtool_ops = { 1736 .get_drvinfo = smc_ethtool_getdrvinfo, 1737 1738 .get_msglevel = smc_ethtool_getmsglevel, 1739 .set_msglevel = smc_ethtool_setmsglevel, 1740 .nway_reset = smc_ethtool_nwayreset, 1741 .get_link = ethtool_op_get_link, 1742 .get_eeprom_len = smc_ethtool_geteeprom_len, 1743 .get_eeprom = smc_ethtool_geteeprom, 1744 .set_eeprom = smc_ethtool_seteeprom, 1745 .get_link_ksettings = smc_ethtool_get_link_ksettings, 1746 .set_link_ksettings = smc_ethtool_set_link_ksettings, 1747}; 1748 1749static const struct net_device_ops smc_netdev_ops = { 1750 .ndo_open = smc_open, 1751 .ndo_stop = smc_close, 1752 .ndo_start_xmit = smc_hard_start_xmit, 1753 .ndo_tx_timeout = smc_timeout, 1754 .ndo_set_rx_mode = smc_set_multicast_list, 1755 .ndo_validate_addr = eth_validate_addr, 1756 .ndo_set_mac_address = eth_mac_addr, 1757#ifdef CONFIG_NET_POLL_CONTROLLER 1758 .ndo_poll_controller = smc_poll_controller, 1759#endif 1760}; 1761 1762/* 1763 * smc_findirq 1764 * 1765 * This routine has a simple purpose -- make the SMC chip generate an 1766 * interrupt, so an auto-detect routine can detect it, and find the IRQ, 1767 */ 1768/* 1769 * does this still work? 1770 * 1771 * I just deleted auto_irq.c, since it was never built... 1772 * --jgarzik 1773 */ 1774static int smc_findirq(struct smc_local *lp) 1775{ 1776 void __iomem *ioaddr = lp->base; 1777 int timeout = 20; 1778 unsigned long cookie; 1779 1780 DBG(2, lp->dev, "%s: %s\n", CARDNAME, __func__); 1781 1782 cookie = probe_irq_on(); 1783 1784 /* 1785 * What I try to do here is trigger an ALLOC_INT. This is done 1786 * by allocating a small chunk of memory, which will give an interrupt 1787 * when done. 1788 */ 1789 /* enable ALLOCation interrupts ONLY */ 1790 SMC_SELECT_BANK(lp, 2); 1791 SMC_SET_INT_MASK(lp, IM_ALLOC_INT); 1792 1793 /* 1794 * Allocate 512 bytes of memory. Note that the chip was just 1795 * reset so all the memory is available 1796 */ 1797 SMC_SET_MMU_CMD(lp, MC_ALLOC | 1); 1798 1799 /* 1800 * Wait until positive that the interrupt has been generated 1801 */ 1802 do { 1803 int int_status; 1804 udelay(10); 1805 int_status = SMC_GET_INT(lp); 1806 if (int_status & IM_ALLOC_INT) 1807 break; /* got the interrupt */ 1808 } while (--timeout); 1809 1810 /* 1811 * there is really nothing that I can do here if timeout fails, 1812 * as autoirq_report will return a 0 anyway, which is what I 1813 * want in this case. Plus, the clean up is needed in both 1814 * cases. 1815 */ 1816 1817 /* and disable all interrupts again */ 1818 SMC_SET_INT_MASK(lp, 0); 1819 1820 /* and return what I found */ 1821 return probe_irq_off(cookie); 1822} 1823 1824/* 1825 * Function: smc_probe(unsigned long ioaddr) 1826 * 1827 * Purpose: 1828 * Tests to see if a given ioaddr points to an SMC91x chip. 1829 * Returns a 0 on success 1830 * 1831 * Algorithm: 1832 * (1) see if the high byte of BANK_SELECT is 0x33 1833 * (2) compare the ioaddr with the base register's address 1834 * (3) see if I recognize the chip ID in the appropriate register 1835 * 1836 * Here I do typical initialization tasks. 1837 * 1838 * o Initialize the structure if needed 1839 * o print out my vanity message if not done so already 1840 * o print out what type of hardware is detected 1841 * o print out the ethernet address 1842 * o find the IRQ 1843 * o set up my private data 1844 * o configure the dev structure with my subroutines 1845 * o actually GRAB the irq. 1846 * o GRAB the region 1847 */ 1848static int smc_probe(struct net_device *dev, void __iomem *ioaddr, 1849 unsigned long irq_flags) 1850{ 1851 struct smc_local *lp = netdev_priv(dev); 1852 int retval; 1853 unsigned int val, revision_register; 1854 const char *version_string; 1855 u8 addr[ETH_ALEN]; 1856 1857 DBG(2, dev, "%s: %s\n", CARDNAME, __func__); 1858 1859 /* First, see if the high byte is 0x33 */ 1860 val = SMC_CURRENT_BANK(lp); 1861 DBG(2, dev, "%s: bank signature probe returned 0x%04x\n", 1862 CARDNAME, val); 1863 if ((val & 0xFF00) != 0x3300) { 1864 if ((val & 0xFF) == 0x33) { 1865 netdev_warn(dev, 1866 "%s: Detected possible byte-swapped interface at IOADDR %p\n", 1867 CARDNAME, ioaddr); 1868 } 1869 retval = -ENODEV; 1870 goto err_out; 1871 } 1872 1873 /* 1874 * The above MIGHT indicate a device, but I need to write to 1875 * further test this. 1876 */ 1877 SMC_SELECT_BANK(lp, 0); 1878 val = SMC_CURRENT_BANK(lp); 1879 if ((val & 0xFF00) != 0x3300) { 1880 retval = -ENODEV; 1881 goto err_out; 1882 } 1883 1884 /* 1885 * well, we've already written once, so hopefully another 1886 * time won't hurt. This time, I need to switch the bank 1887 * register to bank 1, so I can access the base address 1888 * register 1889 */ 1890 SMC_SELECT_BANK(lp, 1); 1891 val = SMC_GET_BASE(lp); 1892 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; 1893 if (((unsigned long)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) { 1894 netdev_warn(dev, "%s: IOADDR %p doesn't match configuration (%x).\n", 1895 CARDNAME, ioaddr, val); 1896 } 1897 1898 /* 1899 * check if the revision register is something that I 1900 * recognize. These might need to be added to later, 1901 * as future revisions could be added. 1902 */ 1903 SMC_SELECT_BANK(lp, 3); 1904 revision_register = SMC_GET_REV(lp); 1905 DBG(2, dev, "%s: revision = 0x%04x\n", CARDNAME, revision_register); 1906 version_string = chip_ids[ (revision_register >> 4) & 0xF]; 1907 if (!version_string || (revision_register & 0xff00) != 0x3300) { 1908 /* I don't recognize this chip, so... */ 1909 netdev_warn(dev, "%s: IO %p: Unrecognized revision register 0x%04x, Contact author.\n", 1910 CARDNAME, ioaddr, revision_register); 1911 1912 retval = -ENODEV; 1913 goto err_out; 1914 } 1915 1916 /* At this point I'll assume that the chip is an SMC91x. */ 1917 pr_info_once("%s\n", version); 1918 1919 /* fill in some of the fields */ 1920 dev->base_addr = (unsigned long)ioaddr; 1921 lp->base = ioaddr; 1922 lp->version = revision_register & 0xff; 1923 spin_lock_init(&lp->lock); 1924 1925 /* Get the MAC address */ 1926 SMC_SELECT_BANK(lp, 1); 1927 SMC_GET_MAC_ADDR(lp, addr); 1928 eth_hw_addr_set(dev, addr); 1929 1930 /* now, reset the chip, and put it into a known state */ 1931 smc_reset(dev); 1932 1933 /* 1934 * If dev->irq is 0, then the device has to be banged on to see 1935 * what the IRQ is. 1936 * 1937 * This banging doesn't always detect the IRQ, for unknown reasons. 1938 * a workaround is to reset the chip and try again. 1939 * 1940 * Interestingly, the DOS packet driver *SETS* the IRQ on the card to 1941 * be what is requested on the command line. I don't do that, mostly 1942 * because the card that I have uses a non-standard method of accessing 1943 * the IRQs, and because this _should_ work in most configurations. 1944 * 1945 * Specifying an IRQ is done with the assumption that the user knows 1946 * what (s)he is doing. No checking is done!!!! 1947 */ 1948 if (dev->irq < 1) { 1949 int trials; 1950 1951 trials = 3; 1952 while (trials--) { 1953 dev->irq = smc_findirq(lp); 1954 if (dev->irq) 1955 break; 1956 /* kick the card and try again */ 1957 smc_reset(dev); 1958 } 1959 } 1960 if (dev->irq == 0) { 1961 netdev_warn(dev, "Couldn't autodetect your IRQ. Use irq=xx.\n"); 1962 retval = -ENODEV; 1963 goto err_out; 1964 } 1965 dev->irq = irq_canonicalize(dev->irq); 1966 1967 dev->watchdog_timeo = msecs_to_jiffies(watchdog); 1968 dev->netdev_ops = &smc_netdev_ops; 1969 dev->ethtool_ops = &smc_ethtool_ops; 1970 1971 tasklet_setup(&lp->tx_task, smc_hardware_send_pkt); 1972 INIT_WORK(&lp->phy_configure, smc_phy_configure); 1973 lp->dev = dev; 1974 lp->mii.phy_id_mask = 0x1f; 1975 lp->mii.reg_num_mask = 0x1f; 1976 lp->mii.force_media = 0; 1977 lp->mii.full_duplex = 0; 1978 lp->mii.dev = dev; 1979 lp->mii.mdio_read = smc_phy_read; 1980 lp->mii.mdio_write = smc_phy_write; 1981 1982 /* 1983 * Locate the phy, if any. 1984 */ 1985 if (lp->version >= (CHIP_91100 << 4)) 1986 smc_phy_detect(dev); 1987 1988 /* then shut everything down to save power */ 1989 smc_shutdown(dev); 1990 smc_phy_powerdown(dev); 1991 1992 /* Set default parameters */ 1993 lp->msg_enable = NETIF_MSG_LINK; 1994 lp->ctl_rfduplx = 0; 1995 lp->ctl_rspeed = 10; 1996 1997 if (lp->version >= (CHIP_91100 << 4)) { 1998 lp->ctl_rfduplx = 1; 1999 lp->ctl_rspeed = 100; 2000 } 2001 2002 /* Grab the IRQ */ 2003 retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev); 2004 if (retval) 2005 goto err_out; 2006 2007#ifdef CONFIG_ARCH_PXA 2008# ifdef SMC_USE_PXA_DMA 2009 lp->cfg.flags |= SMC91X_USE_DMA; 2010# endif 2011 if (lp->cfg.flags & SMC91X_USE_DMA) { 2012 dma_cap_mask_t mask; 2013 2014 dma_cap_zero(mask); 2015 dma_cap_set(DMA_SLAVE, mask); 2016 lp->dma_chan = dma_request_channel(mask, NULL, NULL); 2017 } 2018#endif 2019 2020 retval = register_netdev(dev); 2021 if (retval == 0) { 2022 /* now, print out the card info, in a short format.. */ 2023 netdev_info(dev, "%s (rev %d) at %p IRQ %d", 2024 version_string, revision_register & 0x0f, 2025 lp->base, dev->irq); 2026 2027 if (lp->dma_chan) 2028 pr_cont(" DMA %p", lp->dma_chan); 2029 2030 pr_cont("%s%s\n", 2031 lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "", 2032 THROTTLE_TX_PKTS ? " [throttle_tx]" : ""); 2033 2034 if (!is_valid_ether_addr(dev->dev_addr)) { 2035 netdev_warn(dev, "Invalid ethernet MAC address. Please set using ifconfig\n"); 2036 } else { 2037 /* Print the Ethernet address */ 2038 netdev_info(dev, "Ethernet addr: %pM\n", 2039 dev->dev_addr); 2040 } 2041 2042 if (lp->phy_type == 0) { 2043 PRINTK(dev, "No PHY found\n"); 2044 } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) { 2045 PRINTK(dev, "PHY LAN83C183 (LAN91C111 Internal)\n"); 2046 } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) { 2047 PRINTK(dev, "PHY LAN83C180\n"); 2048 } 2049 } 2050 2051err_out: 2052#ifdef CONFIG_ARCH_PXA 2053 if (retval && lp->dma_chan) 2054 dma_release_channel(lp->dma_chan); 2055#endif 2056 return retval; 2057} 2058 2059static int smc_enable_device(struct platform_device *pdev) 2060{ 2061 struct net_device *ndev = platform_get_drvdata(pdev); 2062 struct smc_local *lp = netdev_priv(ndev); 2063 unsigned long flags; 2064 unsigned char ecor, ecsr; 2065 void __iomem *addr; 2066 struct resource * res; 2067 2068 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2069 if (!res) 2070 return 0; 2071 2072 /* 2073 * Map the attribute space. This is overkill, but clean. 2074 */ 2075 addr = ioremap(res->start, ATTRIB_SIZE); 2076 if (!addr) 2077 return -ENOMEM; 2078 2079 /* 2080 * Reset the device. We must disable IRQs around this 2081 * since a reset causes the IRQ line become active. 2082 */ 2083 local_irq_save(flags); 2084 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; 2085 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); 2086 readb(addr + (ECOR << SMC_IO_SHIFT)); 2087 2088 /* 2089 * Wait 100us for the chip to reset. 2090 */ 2091 udelay(100); 2092 2093 /* 2094 * The device will ignore all writes to the enable bit while 2095 * reset is asserted, even if the reset bit is cleared in the 2096 * same write. Must clear reset first, then enable the device. 2097 */ 2098 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); 2099 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); 2100 2101 /* 2102 * Set the appropriate byte/word mode. 2103 */ 2104 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; 2105 if (!SMC_16BIT(lp)) 2106 ecsr |= ECSR_IOIS8; 2107 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); 2108 local_irq_restore(flags); 2109 2110 iounmap(addr); 2111 2112 /* 2113 * Wait for the chip to wake up. We could poll the control 2114 * register in the main register space, but that isn't mapped 2115 * yet. We know this is going to take 750us. 2116 */ 2117 msleep(1); 2118 2119 return 0; 2120} 2121 2122static int smc_request_attrib(struct platform_device *pdev, 2123 struct net_device *ndev) 2124{ 2125 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2126 struct smc_local *lp __maybe_unused = netdev_priv(ndev); 2127 2128 if (!res) 2129 return 0; 2130 2131 if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME)) 2132 return -EBUSY; 2133 2134 return 0; 2135} 2136 2137static void smc_release_attrib(struct platform_device *pdev, 2138 struct net_device *ndev) 2139{ 2140 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2141 struct smc_local *lp __maybe_unused = netdev_priv(ndev); 2142 2143 if (res) 2144 release_mem_region(res->start, ATTRIB_SIZE); 2145} 2146 2147static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev) 2148{ 2149 if (SMC_CAN_USE_DATACS) { 2150 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); 2151 struct smc_local *lp = netdev_priv(ndev); 2152 2153 if (!res) 2154 return; 2155 2156 if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) { 2157 netdev_info(ndev, "%s: failed to request datacs memory region.\n", 2158 CARDNAME); 2159 return; 2160 } 2161 2162 lp->datacs = ioremap(res->start, SMC_DATA_EXTENT); 2163 } 2164} 2165 2166static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev) 2167{ 2168 if (SMC_CAN_USE_DATACS) { 2169 struct smc_local *lp = netdev_priv(ndev); 2170 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); 2171 2172 if (lp->datacs) 2173 iounmap(lp->datacs); 2174 2175 lp->datacs = NULL; 2176 2177 if (res) 2178 release_mem_region(res->start, SMC_DATA_EXTENT); 2179 } 2180} 2181 2182static const struct acpi_device_id smc91x_acpi_match[] = { 2183 { "LNRO0003", 0 }, 2184 { } 2185}; 2186MODULE_DEVICE_TABLE(acpi, smc91x_acpi_match); 2187 2188#if IS_BUILTIN(CONFIG_OF) 2189static const struct of_device_id smc91x_match[] = { 2190 { .compatible = "smsc,lan91c94", }, 2191 { .compatible = "smsc,lan91c111", }, 2192 {}, 2193}; 2194MODULE_DEVICE_TABLE(of, smc91x_match); 2195 2196/** 2197 * try_toggle_control_gpio - configure a gpio if it exists 2198 * @dev: net device 2199 * @desc: where to store the GPIO descriptor, if it exists 2200 * @name: name of the GPIO in DT 2201 * @index: index of the GPIO in DT 2202 * @value: set the GPIO to this value 2203 * @nsdelay: delay before setting the GPIO 2204 */ 2205static int try_toggle_control_gpio(struct device *dev, 2206 struct gpio_desc **desc, 2207 const char *name, int index, 2208 int value, unsigned int nsdelay) 2209{ 2210 struct gpio_desc *gpio; 2211 enum gpiod_flags flags = value ? GPIOD_OUT_LOW : GPIOD_OUT_HIGH; 2212 2213 gpio = devm_gpiod_get_index_optional(dev, name, index, flags); 2214 if (IS_ERR(gpio)) 2215 return PTR_ERR(gpio); 2216 2217 if (gpio) { 2218 if (nsdelay) 2219 usleep_range(nsdelay, 2 * nsdelay); 2220 gpiod_set_value_cansleep(gpio, value); 2221 } 2222 *desc = gpio; 2223 2224 return 0; 2225} 2226#endif 2227 2228/* 2229 * smc_init(void) 2230 * Input parameters: 2231 * dev->base_addr == 0, try to find all possible locations 2232 * dev->base_addr > 0x1ff, this is the address to check 2233 * dev->base_addr == <anything else>, return failure code 2234 * 2235 * Output: 2236 * 0 --> there is a device 2237 * anything else, error 2238 */ 2239static int smc_drv_probe(struct platform_device *pdev) 2240{ 2241 struct smc91x_platdata *pd = dev_get_platdata(&pdev->dev); 2242 const struct of_device_id *match = NULL; 2243 struct smc_local *lp; 2244 struct net_device *ndev; 2245 struct resource *res; 2246 unsigned int __iomem *addr; 2247 unsigned long irq_flags = SMC_IRQ_FLAGS; 2248 unsigned long irq_resflags; 2249 int ret; 2250 2251 ndev = alloc_etherdev(sizeof(struct smc_local)); 2252 if (!ndev) { 2253 ret = -ENOMEM; 2254 goto out; 2255 } 2256 SET_NETDEV_DEV(ndev, &pdev->dev); 2257 2258 /* get configuration from platform data, only allow use of 2259 * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set. 2260 */ 2261 2262 lp = netdev_priv(ndev); 2263 lp->cfg.flags = 0; 2264 2265 if (pd) { 2266 memcpy(&lp->cfg, pd, sizeof(lp->cfg)); 2267 lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags); 2268 2269 if (!SMC_8BIT(lp) && !SMC_16BIT(lp)) { 2270 dev_err(&pdev->dev, 2271 "at least one of 8-bit or 16-bit access support is required.\n"); 2272 ret = -ENXIO; 2273 goto out_free_netdev; 2274 } 2275 } 2276 2277#if IS_BUILTIN(CONFIG_OF) 2278 match = of_match_device(of_match_ptr(smc91x_match), &pdev->dev); 2279 if (match) { 2280 u32 val; 2281 2282 /* Optional pwrdwn GPIO configured? */ 2283 ret = try_toggle_control_gpio(&pdev->dev, &lp->power_gpio, 2284 "power", 0, 0, 100); 2285 if (ret) 2286 goto out_free_netdev; 2287 2288 /* 2289 * Optional reset GPIO configured? Minimum 100 ns reset needed 2290 * according to LAN91C96 datasheet page 14. 2291 */ 2292 ret = try_toggle_control_gpio(&pdev->dev, &lp->reset_gpio, 2293 "reset", 0, 0, 100); 2294 if (ret) 2295 goto out_free_netdev; 2296 2297 /* 2298 * Need to wait for optional EEPROM to load, max 750 us according 2299 * to LAN91C96 datasheet page 55. 2300 */ 2301 if (lp->reset_gpio) 2302 usleep_range(750, 1000); 2303 2304 /* Combination of IO widths supported, default to 16-bit */ 2305 if (!device_property_read_u32(&pdev->dev, "reg-io-width", 2306 &val)) { 2307 if (val & 1) 2308 lp->cfg.flags |= SMC91X_USE_8BIT; 2309 if ((val == 0) || (val & 2)) 2310 lp->cfg.flags |= SMC91X_USE_16BIT; 2311 if (val & 4) 2312 lp->cfg.flags |= SMC91X_USE_32BIT; 2313 } else { 2314 lp->cfg.flags |= SMC91X_USE_16BIT; 2315 } 2316 if (!device_property_read_u32(&pdev->dev, "reg-shift", 2317 &val)) 2318 lp->io_shift = val; 2319 lp->cfg.pxa_u16_align4 = 2320 device_property_read_bool(&pdev->dev, "pxa-u16-align4"); 2321 } 2322#endif 2323 2324 if (!pd && !match) { 2325 lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0; 2326 lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0; 2327 lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0; 2328 lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0; 2329 } 2330 2331 if (!lp->cfg.leda && !lp->cfg.ledb) { 2332 lp->cfg.leda = RPC_LSA_DEFAULT; 2333 lp->cfg.ledb = RPC_LSB_DEFAULT; 2334 } 2335 2336 ndev->dma = (unsigned char)-1; 2337 2338 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); 2339 if (!res) 2340 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2341 if (!res) { 2342 ret = -ENODEV; 2343 goto out_free_netdev; 2344 } 2345 2346 2347 if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) { 2348 ret = -EBUSY; 2349 goto out_free_netdev; 2350 } 2351 2352 ndev->irq = platform_get_irq(pdev, 0); 2353 if (ndev->irq < 0) { 2354 ret = ndev->irq; 2355 goto out_release_io; 2356 } 2357 /* 2358 * If this platform does not specify any special irqflags, or if 2359 * the resource supplies a trigger, override the irqflags with 2360 * the trigger flags from the resource. 2361 */ 2362 irq_resflags = irqd_get_trigger_type(irq_get_irq_data(ndev->irq)); 2363 if (irq_flags == -1 || irq_resflags & IRQF_TRIGGER_MASK) 2364 irq_flags = irq_resflags & IRQF_TRIGGER_MASK; 2365 2366 ret = smc_request_attrib(pdev, ndev); 2367 if (ret) 2368 goto out_release_io; 2369#if defined(CONFIG_ASSABET_NEPONSET) 2370 if (machine_is_assabet() && machine_has_neponset()) 2371 neponset_ncr_set(NCR_ENET_OSC_EN); 2372#endif 2373 platform_set_drvdata(pdev, ndev); 2374 ret = smc_enable_device(pdev); 2375 if (ret) 2376 goto out_release_attrib; 2377 2378 addr = ioremap(res->start, SMC_IO_EXTENT); 2379 if (!addr) { 2380 ret = -ENOMEM; 2381 goto out_release_attrib; 2382 } 2383 2384#ifdef CONFIG_ARCH_PXA 2385 { 2386 struct smc_local *lp = netdev_priv(ndev); 2387 lp->device = &pdev->dev; 2388 lp->physaddr = res->start; 2389 2390 } 2391#endif 2392 2393 ret = smc_probe(ndev, addr, irq_flags); 2394 if (ret != 0) 2395 goto out_iounmap; 2396 2397 smc_request_datacs(pdev, ndev); 2398 2399 return 0; 2400 2401 out_iounmap: 2402 iounmap(addr); 2403 out_release_attrib: 2404 smc_release_attrib(pdev, ndev); 2405 out_release_io: 2406 release_mem_region(res->start, SMC_IO_EXTENT); 2407 out_free_netdev: 2408 free_netdev(ndev); 2409 out: 2410 pr_info("%s: not found (%d).\n", CARDNAME, ret); 2411 2412 return ret; 2413} 2414 2415static void smc_drv_remove(struct platform_device *pdev) 2416{ 2417 struct net_device *ndev = platform_get_drvdata(pdev); 2418 struct smc_local *lp = netdev_priv(ndev); 2419 struct resource *res; 2420 2421 unregister_netdev(ndev); 2422 2423 free_irq(ndev->irq, ndev); 2424 2425#ifdef CONFIG_ARCH_PXA 2426 if (lp->dma_chan) 2427 dma_release_channel(lp->dma_chan); 2428#endif 2429 iounmap(lp->base); 2430 2431 smc_release_datacs(pdev,ndev); 2432 smc_release_attrib(pdev,ndev); 2433 2434 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); 2435 if (!res) 2436 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2437 release_mem_region(res->start, SMC_IO_EXTENT); 2438 2439 free_netdev(ndev); 2440} 2441 2442static int smc_drv_suspend(struct device *dev) 2443{ 2444 struct net_device *ndev = dev_get_drvdata(dev); 2445 2446 if (ndev) { 2447 if (netif_running(ndev)) { 2448 netif_device_detach(ndev); 2449 smc_shutdown(ndev); 2450 smc_phy_powerdown(ndev); 2451 } 2452 } 2453 return 0; 2454} 2455 2456static int smc_drv_resume(struct device *dev) 2457{ 2458 struct platform_device *pdev = to_platform_device(dev); 2459 struct net_device *ndev = platform_get_drvdata(pdev); 2460 2461 if (ndev) { 2462 struct smc_local *lp = netdev_priv(ndev); 2463 smc_enable_device(pdev); 2464 if (netif_running(ndev)) { 2465 smc_reset(ndev); 2466 smc_enable(ndev); 2467 if (lp->phy_type != 0) 2468 smc_phy_configure(&lp->phy_configure); 2469 netif_device_attach(ndev); 2470 } 2471 } 2472 return 0; 2473} 2474 2475static const struct dev_pm_ops smc_drv_pm_ops = { 2476 .suspend = smc_drv_suspend, 2477 .resume = smc_drv_resume, 2478}; 2479 2480static struct platform_driver smc_driver = { 2481 .probe = smc_drv_probe, 2482 .remove_new = smc_drv_remove, 2483 .driver = { 2484 .name = CARDNAME, 2485 .pm = &smc_drv_pm_ops, 2486 .of_match_table = of_match_ptr(smc91x_match), 2487 .acpi_match_table = smc91x_acpi_match, 2488 }, 2489}; 2490 2491module_platform_driver(smc_driver); 2492