1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4#include <linux/module.h> 5#include <linux/netdevice.h> 6#include <linux/sfp.h> 7 8#include "ionic.h" 9#include "ionic_bus.h" 10#include "ionic_lif.h" 11#include "ionic_ethtool.h" 12#include "ionic_stats.h" 13 14static void ionic_get_stats_strings(struct ionic_lif *lif, u8 *buf) 15{ 16 u32 i; 17 18 for (i = 0; i < ionic_num_stats_grps; i++) 19 ionic_stats_groups[i].get_strings(lif, &buf); 20} 21 22static void ionic_get_stats(struct net_device *netdev, 23 struct ethtool_stats *stats, u64 *buf) 24{ 25 struct ionic_lif *lif = netdev_priv(netdev); 26 u32 i; 27 28 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 29 return; 30 31 memset(buf, 0, stats->n_stats * sizeof(*buf)); 32 for (i = 0; i < ionic_num_stats_grps; i++) 33 ionic_stats_groups[i].get_values(lif, &buf); 34} 35 36static int ionic_get_stats_count(struct ionic_lif *lif) 37{ 38 int i, num_stats = 0; 39 40 for (i = 0; i < ionic_num_stats_grps; i++) 41 num_stats += ionic_stats_groups[i].get_count(lif); 42 43 return num_stats; 44} 45 46static int ionic_get_sset_count(struct net_device *netdev, int sset) 47{ 48 struct ionic_lif *lif = netdev_priv(netdev); 49 int count = 0; 50 51 switch (sset) { 52 case ETH_SS_STATS: 53 count = ionic_get_stats_count(lif); 54 break; 55 } 56 return count; 57} 58 59static void ionic_get_strings(struct net_device *netdev, 60 u32 sset, u8 *buf) 61{ 62 struct ionic_lif *lif = netdev_priv(netdev); 63 64 switch (sset) { 65 case ETH_SS_STATS: 66 ionic_get_stats_strings(lif, buf); 67 break; 68 } 69} 70 71static void ionic_get_drvinfo(struct net_device *netdev, 72 struct ethtool_drvinfo *drvinfo) 73{ 74 struct ionic_lif *lif = netdev_priv(netdev); 75 struct ionic *ionic = lif->ionic; 76 77 strscpy(drvinfo->driver, IONIC_DRV_NAME, sizeof(drvinfo->driver)); 78 strscpy(drvinfo->fw_version, ionic->idev.dev_info.fw_version, 79 sizeof(drvinfo->fw_version)); 80 strscpy(drvinfo->bus_info, ionic_bus_info(ionic), 81 sizeof(drvinfo->bus_info)); 82} 83 84static int ionic_get_regs_len(struct net_device *netdev) 85{ 86 return (IONIC_DEV_INFO_REG_COUNT + IONIC_DEV_CMD_REG_COUNT) * sizeof(u32); 87} 88 89static void ionic_get_regs(struct net_device *netdev, struct ethtool_regs *regs, 90 void *p) 91{ 92 struct ionic_lif *lif = netdev_priv(netdev); 93 struct ionic_dev *idev; 94 unsigned int offset; 95 unsigned int size; 96 97 regs->version = IONIC_DEV_CMD_REG_VERSION; 98 99 idev = &lif->ionic->idev; 100 if (!idev->dev_info_regs) 101 return; 102 103 offset = 0; 104 size = IONIC_DEV_INFO_REG_COUNT * sizeof(u32); 105 memcpy_fromio(p + offset, lif->ionic->idev.dev_info_regs->words, size); 106 107 offset += size; 108 size = IONIC_DEV_CMD_REG_COUNT * sizeof(u32); 109 memcpy_fromio(p + offset, idev->dev_cmd_regs->words, size); 110} 111 112static void ionic_get_link_ext_stats(struct net_device *netdev, 113 struct ethtool_link_ext_stats *stats) 114{ 115 struct ionic_lif *lif = netdev_priv(netdev); 116 117 if (lif->ionic->pdev->is_physfn) 118 stats->link_down_events = lif->link_down_count; 119} 120 121static int ionic_get_link_ksettings(struct net_device *netdev, 122 struct ethtool_link_ksettings *ks) 123{ 124 struct ionic_lif *lif = netdev_priv(netdev); 125 struct ionic_dev *idev = &lif->ionic->idev; 126 int copper_seen = 0; 127 128 ethtool_link_ksettings_zero_link_mode(ks, supported); 129 130 if (!idev->port_info) { 131 netdev_err(netdev, "port_info not initialized\n"); 132 return -EOPNOTSUPP; 133 } 134 135 /* The port_info data is found in a DMA space that the NIC keeps 136 * up-to-date, so there's no need to request the data from the 137 * NIC, we already have it in our memory space. 138 */ 139 140 switch (le16_to_cpu(idev->port_info->status.xcvr.pid)) { 141 /* Copper */ 142 case IONIC_XCVR_PID_QSFP_100G_CR4: 143 ethtool_link_ksettings_add_link_mode(ks, supported, 144 100000baseCR4_Full); 145 copper_seen++; 146 break; 147 case IONIC_XCVR_PID_QSFP_40GBASE_CR4: 148 ethtool_link_ksettings_add_link_mode(ks, supported, 149 40000baseCR4_Full); 150 copper_seen++; 151 break; 152 case IONIC_XCVR_PID_SFP_25GBASE_CR_S: 153 case IONIC_XCVR_PID_SFP_25GBASE_CR_L: 154 case IONIC_XCVR_PID_SFP_25GBASE_CR_N: 155 ethtool_link_ksettings_add_link_mode(ks, supported, 156 25000baseCR_Full); 157 copper_seen++; 158 break; 159 case IONIC_XCVR_PID_SFP_10GBASE_AOC: 160 case IONIC_XCVR_PID_SFP_10GBASE_CU: 161 ethtool_link_ksettings_add_link_mode(ks, supported, 162 10000baseCR_Full); 163 copper_seen++; 164 break; 165 166 /* Fibre */ 167 case IONIC_XCVR_PID_QSFP_100G_SR4: 168 case IONIC_XCVR_PID_QSFP_100G_AOC: 169 ethtool_link_ksettings_add_link_mode(ks, supported, 170 100000baseSR4_Full); 171 break; 172 case IONIC_XCVR_PID_QSFP_100G_CWDM4: 173 case IONIC_XCVR_PID_QSFP_100G_PSM4: 174 case IONIC_XCVR_PID_QSFP_100G_LR4: 175 ethtool_link_ksettings_add_link_mode(ks, supported, 176 100000baseLR4_ER4_Full); 177 break; 178 case IONIC_XCVR_PID_QSFP_100G_ER4: 179 ethtool_link_ksettings_add_link_mode(ks, supported, 180 100000baseLR4_ER4_Full); 181 break; 182 case IONIC_XCVR_PID_QSFP_40GBASE_SR4: 183 case IONIC_XCVR_PID_QSFP_40GBASE_AOC: 184 ethtool_link_ksettings_add_link_mode(ks, supported, 185 40000baseSR4_Full); 186 break; 187 case IONIC_XCVR_PID_QSFP_40GBASE_LR4: 188 ethtool_link_ksettings_add_link_mode(ks, supported, 189 40000baseLR4_Full); 190 break; 191 case IONIC_XCVR_PID_SFP_25GBASE_SR: 192 case IONIC_XCVR_PID_SFP_25GBASE_AOC: 193 case IONIC_XCVR_PID_SFP_25GBASE_ACC: 194 ethtool_link_ksettings_add_link_mode(ks, supported, 195 25000baseSR_Full); 196 break; 197 case IONIC_XCVR_PID_SFP_10GBASE_SR: 198 ethtool_link_ksettings_add_link_mode(ks, supported, 199 10000baseSR_Full); 200 break; 201 case IONIC_XCVR_PID_SFP_10GBASE_LR: 202 ethtool_link_ksettings_add_link_mode(ks, supported, 203 10000baseLR_Full); 204 break; 205 case IONIC_XCVR_PID_SFP_10GBASE_LRM: 206 ethtool_link_ksettings_add_link_mode(ks, supported, 207 10000baseLRM_Full); 208 break; 209 case IONIC_XCVR_PID_SFP_10GBASE_ER: 210 ethtool_link_ksettings_add_link_mode(ks, supported, 211 10000baseER_Full); 212 break; 213 case IONIC_XCVR_PID_SFP_10GBASE_T: 214 ethtool_link_ksettings_add_link_mode(ks, supported, 215 10000baseT_Full); 216 break; 217 case IONIC_XCVR_PID_SFP_1000BASE_T: 218 ethtool_link_ksettings_add_link_mode(ks, supported, 219 1000baseT_Full); 220 break; 221 case IONIC_XCVR_PID_UNKNOWN: 222 /* This means there's no module plugged in */ 223 break; 224 default: 225 dev_info(lif->ionic->dev, "unknown xcvr type pid=%d / 0x%x\n", 226 idev->port_info->status.xcvr.pid, 227 idev->port_info->status.xcvr.pid); 228 break; 229 } 230 231 linkmode_copy(ks->link_modes.advertising, ks->link_modes.supported); 232 233 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER); 234 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS); 235 if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_FC) 236 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_BASER); 237 else if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_RS) 238 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS); 239 240 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE); 241 ethtool_link_ksettings_add_link_mode(ks, supported, Pause); 242 243 if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_COPPER || 244 copper_seen) 245 ks->base.port = PORT_DA; 246 else if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_FIBER) 247 ks->base.port = PORT_FIBRE; 248 else 249 ks->base.port = PORT_NONE; 250 251 if (ks->base.port != PORT_NONE) { 252 ks->base.speed = le32_to_cpu(lif->info->status.link_speed); 253 254 if (le16_to_cpu(lif->info->status.link_status)) 255 ks->base.duplex = DUPLEX_FULL; 256 else 257 ks->base.duplex = DUPLEX_UNKNOWN; 258 259 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg); 260 261 if (idev->port_info->config.an_enable) { 262 ethtool_link_ksettings_add_link_mode(ks, advertising, 263 Autoneg); 264 ks->base.autoneg = AUTONEG_ENABLE; 265 } 266 } 267 268 return 0; 269} 270 271static int ionic_set_link_ksettings(struct net_device *netdev, 272 const struct ethtool_link_ksettings *ks) 273{ 274 struct ionic_lif *lif = netdev_priv(netdev); 275 struct ionic_dev *idev = &lif->ionic->idev; 276 struct ionic *ionic = lif->ionic; 277 int err = 0; 278 279 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 280 return -EBUSY; 281 282 /* set autoneg */ 283 if (ks->base.autoneg != idev->port_info->config.an_enable) { 284 mutex_lock(&ionic->dev_cmd_lock); 285 ionic_dev_cmd_port_autoneg(idev, ks->base.autoneg); 286 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 287 mutex_unlock(&ionic->dev_cmd_lock); 288 if (err) 289 return err; 290 } 291 292 /* set speed */ 293 if (ks->base.speed != le32_to_cpu(idev->port_info->config.speed)) { 294 mutex_lock(&ionic->dev_cmd_lock); 295 ionic_dev_cmd_port_speed(idev, ks->base.speed); 296 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 297 mutex_unlock(&ionic->dev_cmd_lock); 298 if (err) 299 return err; 300 } 301 302 return 0; 303} 304 305static void ionic_get_pauseparam(struct net_device *netdev, 306 struct ethtool_pauseparam *pause) 307{ 308 struct ionic_lif *lif = netdev_priv(netdev); 309 u8 pause_type; 310 311 pause->autoneg = 0; 312 313 pause_type = lif->ionic->idev.port_info->config.pause_type; 314 if (pause_type) { 315 pause->rx_pause = (pause_type & IONIC_PAUSE_F_RX) ? 1 : 0; 316 pause->tx_pause = (pause_type & IONIC_PAUSE_F_TX) ? 1 : 0; 317 } 318} 319 320static int ionic_set_pauseparam(struct net_device *netdev, 321 struct ethtool_pauseparam *pause) 322{ 323 struct ionic_lif *lif = netdev_priv(netdev); 324 struct ionic *ionic = lif->ionic; 325 u32 requested_pause; 326 int err; 327 328 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 329 return -EBUSY; 330 331 if (pause->autoneg) 332 return -EOPNOTSUPP; 333 334 /* change both at the same time */ 335 requested_pause = IONIC_PORT_PAUSE_TYPE_LINK; 336 if (pause->rx_pause) 337 requested_pause |= IONIC_PAUSE_F_RX; 338 if (pause->tx_pause) 339 requested_pause |= IONIC_PAUSE_F_TX; 340 341 if (requested_pause == lif->ionic->idev.port_info->config.pause_type) 342 return 0; 343 344 mutex_lock(&ionic->dev_cmd_lock); 345 ionic_dev_cmd_port_pause(&lif->ionic->idev, requested_pause); 346 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 347 mutex_unlock(&ionic->dev_cmd_lock); 348 if (err) 349 return err; 350 351 return 0; 352} 353 354static int ionic_get_fecparam(struct net_device *netdev, 355 struct ethtool_fecparam *fec) 356{ 357 struct ionic_lif *lif = netdev_priv(netdev); 358 359 switch (lif->ionic->idev.port_info->config.fec_type) { 360 case IONIC_PORT_FEC_TYPE_NONE: 361 fec->active_fec = ETHTOOL_FEC_OFF; 362 break; 363 case IONIC_PORT_FEC_TYPE_RS: 364 fec->active_fec = ETHTOOL_FEC_RS; 365 break; 366 case IONIC_PORT_FEC_TYPE_FC: 367 fec->active_fec = ETHTOOL_FEC_BASER; 368 break; 369 } 370 371 fec->fec = ETHTOOL_FEC_OFF | ETHTOOL_FEC_RS | ETHTOOL_FEC_BASER; 372 373 return 0; 374} 375 376static int ionic_set_fecparam(struct net_device *netdev, 377 struct ethtool_fecparam *fec) 378{ 379 struct ionic_lif *lif = netdev_priv(netdev); 380 u8 fec_type; 381 int ret = 0; 382 383 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 384 return -EBUSY; 385 386 if (lif->ionic->idev.port_info->config.an_enable) { 387 netdev_err(netdev, "FEC request not allowed while autoneg is enabled\n"); 388 return -EINVAL; 389 } 390 391 switch (fec->fec) { 392 case ETHTOOL_FEC_NONE: 393 fec_type = IONIC_PORT_FEC_TYPE_NONE; 394 break; 395 case ETHTOOL_FEC_OFF: 396 fec_type = IONIC_PORT_FEC_TYPE_NONE; 397 break; 398 case ETHTOOL_FEC_RS: 399 fec_type = IONIC_PORT_FEC_TYPE_RS; 400 break; 401 case ETHTOOL_FEC_BASER: 402 fec_type = IONIC_PORT_FEC_TYPE_FC; 403 break; 404 case ETHTOOL_FEC_AUTO: 405 default: 406 netdev_err(netdev, "FEC request 0x%04x not supported\n", 407 fec->fec); 408 return -EINVAL; 409 } 410 411 if (fec_type != lif->ionic->idev.port_info->config.fec_type) { 412 mutex_lock(&lif->ionic->dev_cmd_lock); 413 ionic_dev_cmd_port_fec(&lif->ionic->idev, fec_type); 414 ret = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 415 mutex_unlock(&lif->ionic->dev_cmd_lock); 416 } 417 418 return ret; 419} 420 421static int ionic_get_coalesce(struct net_device *netdev, 422 struct ethtool_coalesce *coalesce, 423 struct kernel_ethtool_coalesce *kernel_coal, 424 struct netlink_ext_ack *extack) 425{ 426 struct ionic_lif *lif = netdev_priv(netdev); 427 428 coalesce->tx_coalesce_usecs = lif->tx_coalesce_usecs; 429 coalesce->rx_coalesce_usecs = lif->rx_coalesce_usecs; 430 431 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 432 coalesce->use_adaptive_tx_coalesce = test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 433 else 434 coalesce->use_adaptive_tx_coalesce = 0; 435 436 coalesce->use_adaptive_rx_coalesce = test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 437 438 return 0; 439} 440 441static int ionic_set_coalesce(struct net_device *netdev, 442 struct ethtool_coalesce *coalesce, 443 struct kernel_ethtool_coalesce *kernel_coal, 444 struct netlink_ext_ack *extack) 445{ 446 struct ionic_lif *lif = netdev_priv(netdev); 447 struct ionic_identity *ident; 448 u32 rx_coal, rx_dim; 449 u32 tx_coal, tx_dim; 450 unsigned int i; 451 452 ident = &lif->ionic->ident; 453 if (ident->dev.intr_coal_div == 0) { 454 netdev_warn(netdev, "bad HW value in dev.intr_coal_div = %d\n", 455 ident->dev.intr_coal_div); 456 return -EIO; 457 } 458 459 /* Tx normally shares Rx interrupt, so only change Rx if not split */ 460 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) && 461 (coalesce->tx_coalesce_usecs != lif->rx_coalesce_usecs || 462 coalesce->use_adaptive_tx_coalesce)) { 463 netdev_warn(netdev, "only rx parameters can be changed\n"); 464 return -EINVAL; 465 } 466 467 /* Convert the usec request to a HW usable value. If they asked 468 * for non-zero and it resolved to zero, bump it up 469 */ 470 rx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->rx_coalesce_usecs); 471 if (!rx_coal && coalesce->rx_coalesce_usecs) 472 rx_coal = 1; 473 tx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->tx_coalesce_usecs); 474 if (!tx_coal && coalesce->tx_coalesce_usecs) 475 tx_coal = 1; 476 477 if (rx_coal > IONIC_INTR_CTRL_COAL_MAX || 478 tx_coal > IONIC_INTR_CTRL_COAL_MAX) 479 return -ERANGE; 480 481 /* Save the new values */ 482 lif->rx_coalesce_usecs = coalesce->rx_coalesce_usecs; 483 lif->rx_coalesce_hw = rx_coal; 484 485 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 486 lif->tx_coalesce_usecs = coalesce->tx_coalesce_usecs; 487 else 488 lif->tx_coalesce_usecs = coalesce->rx_coalesce_usecs; 489 lif->tx_coalesce_hw = tx_coal; 490 491 if (coalesce->use_adaptive_rx_coalesce) { 492 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 493 rx_dim = rx_coal; 494 } else { 495 clear_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 496 rx_dim = 0; 497 } 498 499 if (coalesce->use_adaptive_tx_coalesce) { 500 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 501 tx_dim = tx_coal; 502 } else { 503 clear_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 504 tx_dim = 0; 505 } 506 507 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 508 for (i = 0; i < lif->nxqs; i++) { 509 if (lif->rxqcqs[i]->flags & IONIC_QCQ_F_INTR) { 510 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 511 lif->rxqcqs[i]->intr.index, 512 lif->rx_coalesce_hw); 513 lif->rxqcqs[i]->intr.dim_coal_hw = rx_dim; 514 } 515 516 if (lif->txqcqs[i]->flags & IONIC_QCQ_F_INTR) { 517 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 518 lif->txqcqs[i]->intr.index, 519 lif->tx_coalesce_hw); 520 lif->txqcqs[i]->intr.dim_coal_hw = tx_dim; 521 } 522 } 523 } 524 525 return 0; 526} 527 528static int ionic_validate_cmb_config(struct ionic_lif *lif, 529 struct ionic_queue_params *qparam) 530{ 531 int pages_have, pages_required = 0; 532 unsigned long sz; 533 534 if (!lif->ionic->idev.cmb_inuse && 535 (qparam->cmb_tx || qparam->cmb_rx)) { 536 netdev_info(lif->netdev, "CMB rings are not supported on this device\n"); 537 return -EOPNOTSUPP; 538 } 539 540 if (qparam->cmb_tx) { 541 if (!(lif->qtype_info[IONIC_QTYPE_TXQ].features & IONIC_QIDENT_F_CMB)) { 542 netdev_info(lif->netdev, 543 "CMB rings for tx-push are not supported on this device\n"); 544 return -EOPNOTSUPP; 545 } 546 547 sz = sizeof(struct ionic_txq_desc) * qparam->ntxq_descs * qparam->nxqs; 548 pages_required += ALIGN(sz, PAGE_SIZE) / PAGE_SIZE; 549 } 550 551 if (qparam->cmb_rx) { 552 if (!(lif->qtype_info[IONIC_QTYPE_RXQ].features & IONIC_QIDENT_F_CMB)) { 553 netdev_info(lif->netdev, 554 "CMB rings for rx-push are not supported on this device\n"); 555 return -EOPNOTSUPP; 556 } 557 558 sz = sizeof(struct ionic_rxq_desc) * qparam->nrxq_descs * qparam->nxqs; 559 pages_required += ALIGN(sz, PAGE_SIZE) / PAGE_SIZE; 560 } 561 562 pages_have = lif->ionic->bars[IONIC_PCI_BAR_CMB].len / PAGE_SIZE; 563 if (pages_required > pages_have) { 564 netdev_info(lif->netdev, 565 "Not enough CMB pages for number of queues and size of descriptor rings, need %d have %d", 566 pages_required, pages_have); 567 return -ENOMEM; 568 } 569 570 return pages_required; 571} 572 573static int ionic_cmb_rings_toggle(struct ionic_lif *lif, bool cmb_tx, bool cmb_rx) 574{ 575 struct ionic_queue_params qparam; 576 int pages_used; 577 578 if (netif_running(lif->netdev)) { 579 netdev_info(lif->netdev, "Please stop device to toggle CMB for tx/rx-push\n"); 580 return -EBUSY; 581 } 582 583 ionic_init_queue_params(lif, &qparam); 584 qparam.cmb_tx = cmb_tx; 585 qparam.cmb_rx = cmb_rx; 586 pages_used = ionic_validate_cmb_config(lif, &qparam); 587 if (pages_used < 0) 588 return pages_used; 589 590 if (cmb_tx) 591 set_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 592 else 593 clear_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 594 595 if (cmb_rx) 596 set_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 597 else 598 clear_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 599 600 if (cmb_tx || cmb_rx) 601 netdev_info(lif->netdev, "Enabling CMB %s %s rings - %d pages\n", 602 cmb_tx ? "TX" : "", cmb_rx ? "RX" : "", pages_used); 603 else 604 netdev_info(lif->netdev, "Disabling CMB rings\n"); 605 606 return 0; 607} 608 609static void ionic_get_ringparam(struct net_device *netdev, 610 struct ethtool_ringparam *ring, 611 struct kernel_ethtool_ringparam *kernel_ring, 612 struct netlink_ext_ack *extack) 613{ 614 struct ionic_lif *lif = netdev_priv(netdev); 615 616 ring->tx_max_pending = IONIC_MAX_TX_DESC; 617 ring->tx_pending = lif->ntxq_descs; 618 ring->rx_max_pending = IONIC_MAX_RX_DESC; 619 ring->rx_pending = lif->nrxq_descs; 620 kernel_ring->tx_push = test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); 621 kernel_ring->rx_push = test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); 622} 623 624static int ionic_set_ringparam(struct net_device *netdev, 625 struct ethtool_ringparam *ring, 626 struct kernel_ethtool_ringparam *kernel_ring, 627 struct netlink_ext_ack *extack) 628{ 629 struct ionic_lif *lif = netdev_priv(netdev); 630 struct ionic_queue_params qparam; 631 int err; 632 633 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 634 return -EBUSY; 635 636 ionic_init_queue_params(lif, &qparam); 637 638 if (ring->rx_mini_pending || ring->rx_jumbo_pending) { 639 netdev_info(netdev, "Changing jumbo or mini descriptors not supported\n"); 640 return -EINVAL; 641 } 642 643 if (!is_power_of_2(ring->tx_pending) || 644 !is_power_of_2(ring->rx_pending)) { 645 netdev_info(netdev, "Descriptor count must be a power of 2\n"); 646 return -EINVAL; 647 } 648 649 /* if nothing to do return success */ 650 if (ring->tx_pending == lif->ntxq_descs && 651 ring->rx_pending == lif->nrxq_descs && 652 kernel_ring->tx_push == test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) && 653 kernel_ring->rx_push == test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) 654 return 0; 655 656 qparam.ntxq_descs = ring->tx_pending; 657 qparam.nrxq_descs = ring->rx_pending; 658 qparam.cmb_tx = kernel_ring->tx_push; 659 qparam.cmb_rx = kernel_ring->rx_push; 660 661 err = ionic_validate_cmb_config(lif, &qparam); 662 if (err < 0) 663 return err; 664 665 if (kernel_ring->tx_push != test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) || 666 kernel_ring->rx_push != test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) { 667 err = ionic_cmb_rings_toggle(lif, kernel_ring->tx_push, 668 kernel_ring->rx_push); 669 if (err < 0) 670 return err; 671 } 672 673 if (ring->tx_pending != lif->ntxq_descs) 674 netdev_info(netdev, "Changing Tx ring size from %d to %d\n", 675 lif->ntxq_descs, ring->tx_pending); 676 677 if (ring->rx_pending != lif->nrxq_descs) 678 netdev_info(netdev, "Changing Rx ring size from %d to %d\n", 679 lif->nrxq_descs, ring->rx_pending); 680 681 /* if we're not running, just set the values and return */ 682 if (!netif_running(lif->netdev)) { 683 lif->ntxq_descs = ring->tx_pending; 684 lif->nrxq_descs = ring->rx_pending; 685 return 0; 686 } 687 688 mutex_lock(&lif->queue_lock); 689 err = ionic_reconfigure_queues(lif, &qparam); 690 mutex_unlock(&lif->queue_lock); 691 if (err) 692 netdev_info(netdev, "Ring reconfiguration failed, changes canceled: %d\n", err); 693 694 return err; 695} 696 697static void ionic_get_channels(struct net_device *netdev, 698 struct ethtool_channels *ch) 699{ 700 struct ionic_lif *lif = netdev_priv(netdev); 701 702 /* report maximum channels */ 703 ch->max_combined = lif->ionic->ntxqs_per_lif; 704 ch->max_rx = lif->ionic->ntxqs_per_lif / 2; 705 ch->max_tx = lif->ionic->ntxqs_per_lif / 2; 706 707 /* report current channels */ 708 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) { 709 ch->rx_count = lif->nxqs; 710 ch->tx_count = lif->nxqs; 711 } else { 712 ch->combined_count = lif->nxqs; 713 } 714} 715 716static int ionic_set_channels(struct net_device *netdev, 717 struct ethtool_channels *ch) 718{ 719 struct ionic_lif *lif = netdev_priv(netdev); 720 struct ionic_queue_params qparam; 721 int max_cnt; 722 int err; 723 724 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 725 return -EBUSY; 726 727 ionic_init_queue_params(lif, &qparam); 728 729 if ((ch->rx_count || ch->tx_count) && lif->xdp_prog) { 730 netdev_info(lif->netdev, "Split Tx/Rx interrupts not available when using XDP\n"); 731 return -EOPNOTSUPP; 732 } 733 734 if (ch->rx_count != ch->tx_count) { 735 netdev_info(netdev, "The rx and tx count must be equal\n"); 736 return -EINVAL; 737 } 738 739 if (ch->combined_count && ch->rx_count) { 740 netdev_info(netdev, "Use either combined or rx and tx, not both\n"); 741 return -EINVAL; 742 } 743 744 max_cnt = lif->ionic->ntxqs_per_lif; 745 if (ch->combined_count) { 746 if (ch->combined_count > max_cnt) 747 return -EINVAL; 748 749 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 750 netdev_info(lif->netdev, "Sharing queue interrupts\n"); 751 else if (ch->combined_count == lif->nxqs) 752 return 0; 753 754 if (lif->nxqs != ch->combined_count) 755 netdev_info(netdev, "Changing queue count from %d to %d\n", 756 lif->nxqs, ch->combined_count); 757 758 qparam.nxqs = ch->combined_count; 759 qparam.intr_split = false; 760 } else { 761 max_cnt /= 2; 762 if (ch->rx_count > max_cnt) 763 return -EINVAL; 764 765 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 766 netdev_info(lif->netdev, "Splitting queue interrupts\n"); 767 else if (ch->rx_count == lif->nxqs) 768 return 0; 769 770 if (lif->nxqs != ch->rx_count) 771 netdev_info(netdev, "Changing queue count from %d to %d\n", 772 lif->nxqs, ch->rx_count); 773 774 qparam.nxqs = ch->rx_count; 775 qparam.intr_split = true; 776 } 777 778 err = ionic_validate_cmb_config(lif, &qparam); 779 if (err < 0) 780 return err; 781 782 /* if we're not running, just set the values and return */ 783 if (!netif_running(lif->netdev)) { 784 lif->nxqs = qparam.nxqs; 785 786 if (qparam.intr_split) { 787 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 788 } else { 789 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 790 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 791 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 792 } 793 return 0; 794 } 795 796 mutex_lock(&lif->queue_lock); 797 err = ionic_reconfigure_queues(lif, &qparam); 798 mutex_unlock(&lif->queue_lock); 799 if (err) 800 netdev_info(netdev, "Queue reconfiguration failed, changes canceled: %d\n", err); 801 802 return err; 803} 804 805static int ionic_get_rxnfc(struct net_device *netdev, 806 struct ethtool_rxnfc *info, u32 *rules) 807{ 808 struct ionic_lif *lif = netdev_priv(netdev); 809 int err = 0; 810 811 switch (info->cmd) { 812 case ETHTOOL_GRXRINGS: 813 info->data = lif->nxqs; 814 break; 815 default: 816 netdev_dbg(netdev, "Command parameter %d is not supported\n", 817 info->cmd); 818 err = -EOPNOTSUPP; 819 } 820 821 return err; 822} 823 824static u32 ionic_get_rxfh_indir_size(struct net_device *netdev) 825{ 826 struct ionic_lif *lif = netdev_priv(netdev); 827 828 return le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 829} 830 831static u32 ionic_get_rxfh_key_size(struct net_device *netdev) 832{ 833 return IONIC_RSS_HASH_KEY_SIZE; 834} 835 836static int ionic_get_rxfh(struct net_device *netdev, 837 struct ethtool_rxfh_param *rxfh) 838{ 839 struct ionic_lif *lif = netdev_priv(netdev); 840 unsigned int i, tbl_sz; 841 842 if (rxfh->indir) { 843 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 844 for (i = 0; i < tbl_sz; i++) 845 rxfh->indir[i] = lif->rss_ind_tbl[i]; 846 } 847 848 if (rxfh->key) 849 memcpy(rxfh->key, lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 850 851 rxfh->hfunc = ETH_RSS_HASH_TOP; 852 853 return 0; 854} 855 856static int ionic_set_rxfh(struct net_device *netdev, 857 struct ethtool_rxfh_param *rxfh, 858 struct netlink_ext_ack *extack) 859{ 860 struct ionic_lif *lif = netdev_priv(netdev); 861 862 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && 863 rxfh->hfunc != ETH_RSS_HASH_TOP) 864 return -EOPNOTSUPP; 865 866 return ionic_lif_rss_config(lif, lif->rss_types, 867 rxfh->key, rxfh->indir); 868} 869 870static int ionic_set_tunable(struct net_device *dev, 871 const struct ethtool_tunable *tuna, 872 const void *data) 873{ 874 struct ionic_lif *lif = netdev_priv(dev); 875 876 switch (tuna->id) { 877 case ETHTOOL_RX_COPYBREAK: 878 lif->rx_copybreak = *(u32 *)data; 879 break; 880 default: 881 return -EOPNOTSUPP; 882 } 883 884 return 0; 885} 886 887static int ionic_get_tunable(struct net_device *netdev, 888 const struct ethtool_tunable *tuna, void *data) 889{ 890 struct ionic_lif *lif = netdev_priv(netdev); 891 892 switch (tuna->id) { 893 case ETHTOOL_RX_COPYBREAK: 894 *(u32 *)data = lif->rx_copybreak; 895 break; 896 default: 897 return -EOPNOTSUPP; 898 } 899 900 return 0; 901} 902 903static int ionic_get_module_info(struct net_device *netdev, 904 struct ethtool_modinfo *modinfo) 905 906{ 907 struct ionic_lif *lif = netdev_priv(netdev); 908 struct ionic_dev *idev = &lif->ionic->idev; 909 struct ionic_xcvr_status *xcvr; 910 struct sfp_eeprom_base *sfp; 911 912 xcvr = &idev->port_info->status.xcvr; 913 sfp = (struct sfp_eeprom_base *) xcvr->sprom; 914 915 /* report the module data type and length */ 916 switch (sfp->phys_id) { 917 case SFF8024_ID_SFP: 918 modinfo->type = ETH_MODULE_SFF_8079; 919 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 920 break; 921 case SFF8024_ID_QSFP_8436_8636: 922 case SFF8024_ID_QSFP28_8636: 923 modinfo->type = ETH_MODULE_SFF_8436; 924 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 925 break; 926 default: 927 netdev_info(netdev, "unknown xcvr type 0x%02x\n", 928 xcvr->sprom[0]); 929 modinfo->type = 0; 930 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 931 break; 932 } 933 934 return 0; 935} 936 937static int ionic_get_module_eeprom(struct net_device *netdev, 938 struct ethtool_eeprom *ee, 939 u8 *data) 940{ 941 struct ionic_lif *lif = netdev_priv(netdev); 942 struct ionic_dev *idev = &lif->ionic->idev; 943 struct ionic_xcvr_status *xcvr; 944 char tbuf[sizeof(xcvr->sprom)]; 945 int count = 10; 946 u32 len; 947 948 /* The NIC keeps the module prom up-to-date in the DMA space 949 * so we can simply copy the module bytes into the data buffer. 950 */ 951 xcvr = &idev->port_info->status.xcvr; 952 len = min_t(u32, sizeof(xcvr->sprom), ee->len); 953 954 do { 955 memcpy(data, xcvr->sprom, len); 956 memcpy(tbuf, xcvr->sprom, len); 957 958 /* Let's make sure we got a consistent copy */ 959 if (!memcmp(data, tbuf, len)) 960 break; 961 962 } while (--count); 963 964 if (!count) 965 return -ETIMEDOUT; 966 967 return 0; 968} 969 970static int ionic_get_ts_info(struct net_device *netdev, 971 struct ethtool_ts_info *info) 972{ 973 struct ionic_lif *lif = netdev_priv(netdev); 974 struct ionic *ionic = lif->ionic; 975 __le64 mask; 976 977 if (!lif->phc || !lif->phc->ptp) 978 return ethtool_op_get_ts_info(netdev, info); 979 980 info->phc_index = ptp_clock_index(lif->phc->ptp); 981 982 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 983 SOF_TIMESTAMPING_RX_SOFTWARE | 984 SOF_TIMESTAMPING_SOFTWARE | 985 SOF_TIMESTAMPING_TX_HARDWARE | 986 SOF_TIMESTAMPING_RX_HARDWARE | 987 SOF_TIMESTAMPING_RAW_HARDWARE; 988 989 /* tx modes */ 990 991 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 992 BIT(HWTSTAMP_TX_ON); 993 994 mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_SYNC)); 995 if (ionic->ident.lif.eth.hwstamp_tx_modes & mask) 996 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_SYNC); 997 998 mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_P2P)); 999 if (ionic->ident.lif.eth.hwstamp_tx_modes & mask) 1000 info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_P2P); 1001 1002 /* rx filters */ 1003 1004 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1005 BIT(HWTSTAMP_FILTER_ALL); 1006 1007 mask = cpu_to_le64(IONIC_PKT_CLS_NTP_ALL); 1008 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1009 info->rx_filters |= BIT(HWTSTAMP_FILTER_NTP_ALL); 1010 1011 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_SYNC); 1012 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1013 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC); 1014 1015 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_DREQ); 1016 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1017 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); 1018 1019 mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_ALL); 1020 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1021 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT); 1022 1023 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_SYNC); 1024 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1025 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC); 1026 1027 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_DREQ); 1028 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1029 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ); 1030 1031 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_ALL); 1032 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1033 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 1034 1035 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_SYNC); 1036 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1037 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC); 1038 1039 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_DREQ); 1040 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1041 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ); 1042 1043 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_ALL); 1044 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1045 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT); 1046 1047 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_SYNC); 1048 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1049 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_SYNC); 1050 1051 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_DREQ); 1052 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1053 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); 1054 1055 mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_ALL); 1056 if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask) 1057 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 1058 1059 return 0; 1060} 1061 1062static int ionic_nway_reset(struct net_device *netdev) 1063{ 1064 struct ionic_lif *lif = netdev_priv(netdev); 1065 struct ionic *ionic = lif->ionic; 1066 int err = 0; 1067 1068 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1069 return -EBUSY; 1070 1071 /* flap the link to force auto-negotiation */ 1072 1073 mutex_lock(&ionic->dev_cmd_lock); 1074 1075 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_DOWN); 1076 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 1077 1078 if (!err) { 1079 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_UP); 1080 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 1081 } 1082 1083 mutex_unlock(&ionic->dev_cmd_lock); 1084 1085 return err; 1086} 1087 1088static const struct ethtool_ops ionic_ethtool_ops = { 1089 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1090 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 1091 ETHTOOL_COALESCE_USE_ADAPTIVE_TX, 1092 .supported_ring_params = ETHTOOL_RING_USE_TX_PUSH | 1093 ETHTOOL_RING_USE_RX_PUSH, 1094 .get_drvinfo = ionic_get_drvinfo, 1095 .get_regs_len = ionic_get_regs_len, 1096 .get_regs = ionic_get_regs, 1097 .get_link = ethtool_op_get_link, 1098 .get_link_ext_stats = ionic_get_link_ext_stats, 1099 .get_link_ksettings = ionic_get_link_ksettings, 1100 .set_link_ksettings = ionic_set_link_ksettings, 1101 .get_coalesce = ionic_get_coalesce, 1102 .set_coalesce = ionic_set_coalesce, 1103 .get_ringparam = ionic_get_ringparam, 1104 .set_ringparam = ionic_set_ringparam, 1105 .get_channels = ionic_get_channels, 1106 .set_channels = ionic_set_channels, 1107 .get_strings = ionic_get_strings, 1108 .get_ethtool_stats = ionic_get_stats, 1109 .get_sset_count = ionic_get_sset_count, 1110 .get_rxnfc = ionic_get_rxnfc, 1111 .get_rxfh_indir_size = ionic_get_rxfh_indir_size, 1112 .get_rxfh_key_size = ionic_get_rxfh_key_size, 1113 .get_rxfh = ionic_get_rxfh, 1114 .set_rxfh = ionic_set_rxfh, 1115 .get_tunable = ionic_get_tunable, 1116 .set_tunable = ionic_set_tunable, 1117 .get_module_info = ionic_get_module_info, 1118 .get_module_eeprom = ionic_get_module_eeprom, 1119 .get_pauseparam = ionic_get_pauseparam, 1120 .set_pauseparam = ionic_set_pauseparam, 1121 .get_fecparam = ionic_get_fecparam, 1122 .set_fecparam = ionic_set_fecparam, 1123 .get_ts_info = ionic_get_ts_info, 1124 .nway_reset = ionic_nway_reset, 1125}; 1126 1127void ionic_ethtool_set_ops(struct net_device *netdev) 1128{ 1129 netdev->ethtool_ops = &ionic_ethtool_ops; 1130} 1131