1/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ 2 3/* Header file for Mellanox BlueField GigE register defines 4 * 5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES 6 */ 7 8#ifndef __MLXBF_GIGE_REGS_H__ 9#define __MLXBF_GIGE_REGS_H__ 10 11#include <linux/bitfield.h> 12 13#define MLXBF_GIGE_VERSION 0x0000 14#define MLXBF_GIGE_VERSION_BF2 0x0 15#define MLXBF_GIGE_VERSION_BF3 0x1 16#define MLXBF_GIGE_STATUS 0x0010 17#define MLXBF_GIGE_STATUS_READY BIT(0) 18#define MLXBF_GIGE_INT_STATUS 0x0028 19#define MLXBF_GIGE_INT_STATUS_RX_RECEIVE_PACKET BIT(0) 20#define MLXBF_GIGE_INT_STATUS_RX_MAC_ERROR BIT(1) 21#define MLXBF_GIGE_INT_STATUS_RX_TRN_ERROR BIT(2) 22#define MLXBF_GIGE_INT_STATUS_SW_ACCESS_ERROR BIT(3) 23#define MLXBF_GIGE_INT_STATUS_SW_CONFIG_ERROR BIT(4) 24#define MLXBF_GIGE_INT_STATUS_TX_PI_CI_EXCEED_WQ_SIZE BIT(5) 25#define MLXBF_GIGE_INT_STATUS_TX_SMALL_FRAME_SIZE BIT(6) 26#define MLXBF_GIGE_INT_STATUS_TX_CHECKSUM_INPUTS BIT(7) 27#define MLXBF_GIGE_INT_STATUS_HW_ACCESS_ERROR BIT(8) 28#define MLXBF_GIGE_INT_EN 0x0030 29#define MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET BIT(0) 30#define MLXBF_GIGE_INT_EN_RX_MAC_ERROR BIT(1) 31#define MLXBF_GIGE_INT_EN_RX_TRN_ERROR BIT(2) 32#define MLXBF_GIGE_INT_EN_SW_ACCESS_ERROR BIT(3) 33#define MLXBF_GIGE_INT_EN_SW_CONFIG_ERROR BIT(4) 34#define MLXBF_GIGE_INT_EN_TX_PI_CI_EXCEED_WQ_SIZE BIT(5) 35#define MLXBF_GIGE_INT_EN_TX_SMALL_FRAME_SIZE BIT(6) 36#define MLXBF_GIGE_INT_EN_TX_CHECKSUM_INPUTS BIT(7) 37#define MLXBF_GIGE_INT_EN_HW_ACCESS_ERROR BIT(8) 38#define MLXBF_GIGE_INT_MASK 0x0038 39#define MLXBF_GIGE_INT_MASK_RX_RECEIVE_PACKET BIT(0) 40#define MLXBF_GIGE_CONTROL 0x0040 41#define MLXBF_GIGE_CONTROL_PORT_EN BIT(0) 42#define MLXBF_GIGE_CONTROL_MAC_ID_RANGE_EN BIT(1) 43#define MLXBF_GIGE_CONTROL_EN_SPECIFIC_MAC BIT(4) 44#define MLXBF_GIGE_CONTROL_CLEAN_PORT_EN BIT(31) 45#define MLXBF_GIGE_RX_WQ_BASE 0x0200 46#define MLXBF_GIGE_RX_WQE_SIZE_LOG2 0x0208 47#define MLXBF_GIGE_RX_WQE_SIZE_LOG2_RESET_VAL 7 48#define MLXBF_GIGE_RX_CQ_BASE 0x0210 49#define MLXBF_GIGE_TX_WQ_BASE 0x0218 50#define MLXBF_GIGE_TX_WQ_SIZE_LOG2 0x0220 51#define MLXBF_GIGE_TX_WQ_SIZE_LOG2_RESET_VAL 7 52#define MLXBF_GIGE_TX_CI_UPDATE_ADDRESS 0x0228 53#define MLXBF_GIGE_RX_WQE_PI 0x0230 54#define MLXBF_GIGE_TX_PRODUCER_INDEX 0x0238 55#define MLXBF_GIGE_RX_MAC_FILTER 0x0240 56#define MLXBF_GIGE_RX_MAC_FILTER_STRIDE 0x0008 57#define MLXBF_GIGE_RX_DIN_DROP_COUNTER 0x0260 58#define MLXBF_GIGE_TX_CONSUMER_INDEX 0x0310 59#define MLXBF_GIGE_TX_CONTROL 0x0318 60#define MLXBF_GIGE_TX_CONTROL_GRACEFUL_STOP BIT(0) 61#define MLXBF_GIGE_TX_STATUS 0x0388 62#define MLXBF_GIGE_TX_STATUS_DATA_FIFO_FULL BIT(1) 63#define MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_START 0x0520 64#define MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_END 0x0528 65#define MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC 0x0540 66#define MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC_EN BIT(0) 67#define MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS 0x0548 68#define MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS_EN BIT(0) 69#define MLXBF_GIGE_RX_PASS_COUNTER_ALL 0x0550 70#define MLXBF_GIGE_RX_DISC_COUNTER_ALL 0x0560 71#define MLXBF_GIGE_RX 0x0578 72#define MLXBF_GIGE_RX_STRIP_CRC_EN BIT(1) 73#define MLXBF_GIGE_RX_DMA 0x0580 74#define MLXBF_GIGE_RX_DMA_EN BIT(0) 75#define MLXBF_GIGE_RX_CQE_PACKET_CI 0x05b0 76#define MLXBF_GIGE_MAC_CFG 0x05e8 77 78/* NOTE: MLXBF_GIGE_MAC_CFG is the last defined register offset, 79 * so use that plus size of single register to derive total size 80 */ 81#define MLXBF_GIGE_MMIO_REG_SZ (MLXBF_GIGE_MAC_CFG + 8) 82 83#define MLXBF_GIGE_PLU_TX_REG0 0x80 84#define MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK GENMASK(11, 0) 85#define MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK GENMASK(15, 14) 86 87#define MLXBF_GIGE_PLU_RX_REG0 0x10 88#define MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK GENMASK(25, 24) 89 90#define MLXBF_GIGE_1G_SGMII_MODE 0x0 91#define MLXBF_GIGE_10M_SGMII_MODE 0x1 92#define MLXBF_GIGE_100M_SGMII_MODE 0x2 93 94/* ipg_size default value for 1G is fixed by HW to 11 + End = 12. 95 * So for 100M it is 12 * 10 - 1 = 119 96 * For 10M, it is 12 * 100 - 1 = 1199 97 */ 98#define MLXBF_GIGE_1G_IPG_SIZE 11 99#define MLXBF_GIGE_100M_IPG_SIZE 119 100#define MLXBF_GIGE_10M_IPG_SIZE 1199 101 102/* Offsets into OOB LLU block for pause frame counters */ 103#define MLXBF_GIGE_BF2_TX_PAUSE_CNT_HI 0x33d8 104#define MLXBF_GIGE_BF2_TX_PAUSE_CNT_LO 0x33dc 105#define MLXBF_GIGE_BF2_RX_PAUSE_CNT_HI 0x3210 106#define MLXBF_GIGE_BF2_RX_PAUSE_CNT_LO 0x3214 107 108#define MLXBF_GIGE_BF3_TX_PAUSE_CNT_HI 0x3a88 109#define MLXBF_GIGE_BF3_TX_PAUSE_CNT_LO 0x3a8c 110#define MLXBF_GIGE_BF3_RX_PAUSE_CNT_HI 0x38c0 111#define MLXBF_GIGE_BF3_RX_PAUSE_CNT_LO 0x38c4 112 113#define MLXBF_GIGE_TX_PAUSE_CNT_HI ((priv->hw_version == MLXBF_GIGE_VERSION_BF2) ? \ 114 MLXBF_GIGE_BF2_TX_PAUSE_CNT_HI : \ 115 MLXBF_GIGE_BF3_TX_PAUSE_CNT_HI) 116#define MLXBF_GIGE_TX_PAUSE_CNT_LO ((priv->hw_version == MLXBF_GIGE_VERSION_BF2) ? \ 117 MLXBF_GIGE_BF2_TX_PAUSE_CNT_LO : \ 118 MLXBF_GIGE_BF3_TX_PAUSE_CNT_LO) 119#define MLXBF_GIGE_RX_PAUSE_CNT_HI ((priv->hw_version == MLXBF_GIGE_VERSION_BF2) ? \ 120 MLXBF_GIGE_BF2_RX_PAUSE_CNT_HI : \ 121 MLXBF_GIGE_BF3_RX_PAUSE_CNT_HI) 122#define MLXBF_GIGE_RX_PAUSE_CNT_LO ((priv->hw_version == MLXBF_GIGE_VERSION_BF2) ? \ 123 MLXBF_GIGE_BF2_RX_PAUSE_CNT_LO : \ 124 MLXBF_GIGE_BF3_RX_PAUSE_CNT_LO) 125 126#define MLXBF_GIGE_BF2_LLU_GENERAL_CONFIG 0x2110 127#define MLXBF_GIGE_BF3_LLU_GENERAL_CONFIG 0x2030 128 129#define MLXBF_GIGE_BF2_LLU_COUNTERS_EN BIT(0) 130#define MLXBF_GIGE_BF3_LLU_COUNTERS_EN BIT(4) 131 132#endif /* !defined(__MLXBF_GIGE_REGS_H__) */ 133