1/* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#include <linux/highmem.h> 34#include <linux/module.h> 35#include <linux/init.h> 36#include <linux/errno.h> 37#include <linux/pci.h> 38#include <linux/dma-mapping.h> 39#include <linux/slab.h> 40#include <linux/interrupt.h> 41#include <linux/delay.h> 42#include <linux/mlx5/driver.h> 43#include <linux/mlx5/cq.h> 44#include <linux/mlx5/qp.h> 45#include <linux/debugfs.h> 46#include <linux/kmod.h> 47#include <linux/mlx5/mlx5_ifc.h> 48#include <linux/mlx5/vport.h> 49#include <linux/version.h> 50#include <net/devlink.h> 51#include "mlx5_core.h" 52#include "lib/eq.h" 53#include "fs_core.h" 54#include "lib/mpfs.h" 55#include "eswitch.h" 56#include "devlink.h" 57#include "fw_reset.h" 58#include "lib/mlx5.h" 59#include "lib/tout.h" 60#include "fpga/core.h" 61#include "en_accel/ipsec.h" 62#include "lib/clock.h" 63#include "lib/vxlan.h" 64#include "lib/geneve.h" 65#include "lib/devcom.h" 66#include "lib/pci_vsc.h" 67#include "diag/fw_tracer.h" 68#include "ecpf.h" 69#include "lib/hv_vhca.h" 70#include "diag/rsc_dump.h" 71#include "sf/vhca_event.h" 72#include "sf/dev/dev.h" 73#include "sf/sf.h" 74#include "mlx5_irq.h" 75#include "hwmon.h" 76#include "lag/lag.h" 77 78MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 79MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 80MODULE_LICENSE("Dual BSD/GPL"); 81 82unsigned int mlx5_core_debug_mask; 83module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 84MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 85 86static unsigned int prof_sel = MLX5_DEFAULT_PROF; 87module_param_named(prof_sel, prof_sel, uint, 0444); 88MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 89 90static u32 sw_owner_id[4]; 91#define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) 92static DEFINE_IDA(sw_vhca_ida); 93 94enum { 95 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 96 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 97}; 98 99#define LOG_MAX_SUPPORTED_QPS 0xff 100 101static struct mlx5_profile profile[] = { 102 [0] = { 103 .mask = 0, 104 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 105 }, 106 [1] = { 107 .mask = MLX5_PROF_MASK_QP_SIZE, 108 .log_max_qp = 12, 109 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 110 111 }, 112 [2] = { 113 .mask = MLX5_PROF_MASK_QP_SIZE | 114 MLX5_PROF_MASK_MR_CACHE, 115 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 116 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 117 .mr_cache[0] = { 118 .size = 500, 119 .limit = 250 120 }, 121 .mr_cache[1] = { 122 .size = 500, 123 .limit = 250 124 }, 125 .mr_cache[2] = { 126 .size = 500, 127 .limit = 250 128 }, 129 .mr_cache[3] = { 130 .size = 500, 131 .limit = 250 132 }, 133 .mr_cache[4] = { 134 .size = 500, 135 .limit = 250 136 }, 137 .mr_cache[5] = { 138 .size = 500, 139 .limit = 250 140 }, 141 .mr_cache[6] = { 142 .size = 500, 143 .limit = 250 144 }, 145 .mr_cache[7] = { 146 .size = 500, 147 .limit = 250 148 }, 149 .mr_cache[8] = { 150 .size = 500, 151 .limit = 250 152 }, 153 .mr_cache[9] = { 154 .size = 500, 155 .limit = 250 156 }, 157 .mr_cache[10] = { 158 .size = 500, 159 .limit = 250 160 }, 161 .mr_cache[11] = { 162 .size = 500, 163 .limit = 250 164 }, 165 .mr_cache[12] = { 166 .size = 64, 167 .limit = 32 168 }, 169 .mr_cache[13] = { 170 .size = 32, 171 .limit = 16 172 }, 173 .mr_cache[14] = { 174 .size = 16, 175 .limit = 8 176 }, 177 .mr_cache[15] = { 178 .size = 8, 179 .limit = 4 180 }, 181 }, 182 [3] = { 183 .mask = MLX5_PROF_MASK_QP_SIZE, 184 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 185 .num_cmd_caches = 0, 186 }, 187}; 188 189static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 190 u32 warn_time_mili, const char *init_state) 191{ 192 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 193 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 194 u32 fw_initializing; 195 196 do { 197 fw_initializing = ioread32be(&dev->iseg->initializing); 198 if (!(fw_initializing >> 31)) 199 break; 200 if (time_after(jiffies, end)) { 201 mlx5_core_err(dev, "Firmware over %u MS in %s state, aborting\n", 202 max_wait_mili, init_state); 203 return -ETIMEDOUT; 204 } 205 if (test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { 206 mlx5_core_warn(dev, "device is being removed, stop waiting for FW %s\n", 207 init_state); 208 return -ENODEV; 209 } 210 if (warn_time_mili && time_after(jiffies, warn)) { 211 mlx5_core_warn(dev, "Waiting for FW %s, timeout abort in %ds (0x%x)\n", 212 init_state, jiffies_to_msecs(end - warn) / 1000, 213 fw_initializing); 214 warn = jiffies + msecs_to_jiffies(warn_time_mili); 215 } 216 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 217 } while (true); 218 219 return 0; 220} 221 222static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 223{ 224 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 225 driver_version); 226 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 227 char *string; 228 229 if (!MLX5_CAP_GEN(dev, driver_version)) 230 return; 231 232 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 233 234 snprintf(string, driver_ver_sz, "Linux,%s,%u.%u.%u", 235 KBUILD_MODNAME, LINUX_VERSION_MAJOR, 236 LINUX_VERSION_PATCHLEVEL, LINUX_VERSION_SUBLEVEL); 237 238 /*Send the command*/ 239 MLX5_SET(set_driver_version_in, in, opcode, 240 MLX5_CMD_OP_SET_DRIVER_VERSION); 241 242 mlx5_cmd_exec_in(dev, set_driver_version, in); 243} 244 245static int set_dma_caps(struct pci_dev *pdev) 246{ 247 int err; 248 249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 250 if (err) { 251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 252 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 253 if (err) { 254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 255 return err; 256 } 257 } 258 259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 260 return err; 261} 262 263static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 264{ 265 struct pci_dev *pdev = dev->pdev; 266 int err = 0; 267 268 mutex_lock(&dev->pci_status_mutex); 269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 270 err = pci_enable_device(pdev); 271 if (!err) 272 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 273 } 274 mutex_unlock(&dev->pci_status_mutex); 275 276 return err; 277} 278 279static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 280{ 281 struct pci_dev *pdev = dev->pdev; 282 283 mutex_lock(&dev->pci_status_mutex); 284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 285 pci_disable_device(pdev); 286 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 287 } 288 mutex_unlock(&dev->pci_status_mutex); 289} 290 291static int request_bar(struct pci_dev *pdev) 292{ 293 int err = 0; 294 295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 297 return -ENODEV; 298 } 299 300 err = pci_request_regions(pdev, KBUILD_MODNAME); 301 if (err) 302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 303 304 return err; 305} 306 307static void release_bar(struct pci_dev *pdev) 308{ 309 pci_release_regions(pdev); 310} 311 312struct mlx5_reg_host_endianness { 313 u8 he; 314 u8 rsvd[15]; 315}; 316 317static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 318{ 319 switch (size) { 320 case 128: 321 return 0; 322 case 256: 323 return 1; 324 case 512: 325 return 2; 326 case 1024: 327 return 3; 328 case 2048: 329 return 4; 330 case 4096: 331 return 5; 332 default: 333 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 334 return 0; 335 } 336} 337 338void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev) 339{ 340 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 341 dev->mlx5e_res.uplink_netdev = netdev; 342 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 343 netdev); 344 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 345} 346 347void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev) 348{ 349 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 350 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 351 dev->mlx5e_res.uplink_netdev); 352 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 353} 354EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay); 355 356void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data) 357{ 358 mlx5_blocking_notifier_call_chain(dev, event, data); 359} 360EXPORT_SYMBOL(mlx5_core_mp_event_replay); 361 362int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 363 enum mlx5_cap_mode cap_mode) 364{ 365 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 366 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 367 void *out, *hca_caps; 368 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 369 int err; 370 371 memset(in, 0, sizeof(in)); 372 out = kzalloc(out_sz, GFP_KERNEL); 373 if (!out) 374 return -ENOMEM; 375 376 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 377 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 378 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 379 if (err) { 380 mlx5_core_warn(dev, 381 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 382 cap_type, cap_mode, err); 383 goto query_ex; 384 } 385 386 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 387 388 switch (cap_mode) { 389 case HCA_CAP_OPMOD_GET_MAX: 390 memcpy(dev->caps.hca[cap_type]->max, hca_caps, 391 MLX5_UN_SZ_BYTES(hca_cap_union)); 392 break; 393 case HCA_CAP_OPMOD_GET_CUR: 394 memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 395 MLX5_UN_SZ_BYTES(hca_cap_union)); 396 break; 397 default: 398 mlx5_core_warn(dev, 399 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 400 cap_type, cap_mode); 401 err = -EINVAL; 402 break; 403 } 404query_ex: 405 kfree(out); 406 return err; 407} 408 409int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 410{ 411 int ret; 412 413 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 414 if (ret) 415 return ret; 416 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 417} 418 419static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 420{ 421 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 422 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 423 return mlx5_cmd_exec_in(dev, set_hca_cap, in); 424} 425 426static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 427{ 428 void *set_hca_cap; 429 int req_endianness; 430 int err; 431 432 if (!MLX5_CAP_GEN(dev, atomic)) 433 return 0; 434 435 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 436 if (err) 437 return err; 438 439 req_endianness = 440 MLX5_CAP_ATOMIC(dev, 441 supported_atomic_req_8B_endianness_mode_1); 442 443 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 444 return 0; 445 446 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 447 448 /* Set requestor to host endianness */ 449 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 450 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 451 452 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 453} 454 455static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 456{ 457 void *set_hca_cap; 458 bool do_set = false; 459 int err; 460 461 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 462 !MLX5_CAP_GEN(dev, pg)) 463 return 0; 464 465 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 466 if (err) 467 return err; 468 469 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 470 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 471 MLX5_ST_SZ_BYTES(odp_cap)); 472 473#define ODP_CAP_SET_MAX(dev, field) \ 474 do { \ 475 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 476 if (_res) { \ 477 do_set = true; \ 478 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 479 } \ 480 } while (0) 481 482 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 483 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 484 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 485 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 486 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 487 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 488 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 489 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 490 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 491 ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 492 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 493 ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 494 ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 495 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 496 497 if (!do_set) 498 return 0; 499 500 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 501} 502 503static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 504{ 505 struct devlink *devlink = priv_to_devlink(dev); 506 union devlink_param_value val; 507 int err; 508 509 err = devl_param_driverinit_value_get(devlink, 510 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 511 &val); 512 if (!err) 513 return val.vu32; 514 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 515 return err; 516} 517 518bool mlx5_is_roce_on(struct mlx5_core_dev *dev) 519{ 520 struct devlink *devlink = priv_to_devlink(dev); 521 union devlink_param_value val; 522 int err; 523 524 err = devl_param_driverinit_value_get(devlink, 525 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, 526 &val); 527 528 if (!err) 529 return val.vbool; 530 531 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 532 return MLX5_CAP_GEN(dev, roce); 533} 534EXPORT_SYMBOL(mlx5_is_roce_on); 535 536static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) 537{ 538 void *set_hca_cap; 539 int err; 540 541 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2)) 542 return 0; 543 544 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); 545 if (err) 546 return err; 547 548 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) || 549 !(dev->priv.sw_vhca_id > 0)) 550 return 0; 551 552 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 553 capability); 554 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, 555 MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); 556 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 557 558 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2); 559} 560 561static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 562{ 563 struct mlx5_profile *prof = &dev->profile; 564 void *set_hca_cap; 565 int max_uc_list; 566 int err; 567 568 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 569 if (err) 570 return err; 571 572 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 573 capability); 574 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 575 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 576 577 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 578 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 579 128); 580 /* we limit the size of the pkey table to 128 entries for now */ 581 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 582 to_fw_pkey_sz(dev, 128)); 583 584 /* Check log_max_qp from HCA caps to set in current profile */ 585 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 586 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 587 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 588 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 589 prof->log_max_qp, 590 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 591 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 592 } 593 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 594 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 595 prof->log_max_qp); 596 597 /* disable cmdif checksum */ 598 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 599 600 /* Enable 4K UAR only when HCA supports it and page size is bigger 601 * than 4K. 602 */ 603 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 604 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 605 606 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 607 608 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 609 MLX5_SET(cmd_hca_cap, 610 set_hca_cap, 611 cache_line_128byte, 612 cache_line_size() >= 128 ? 1 : 0); 613 614 if (MLX5_CAP_GEN_MAX(dev, dct)) 615 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 616 617 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 618 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 619 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_with_driver_unload)) 620 MLX5_SET(cmd_hca_cap, set_hca_cap, 621 pci_sync_for_fw_update_with_driver_unload, 1); 622 623 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 624 MLX5_SET(cmd_hca_cap, 625 set_hca_cap, 626 num_vhca_ports, 627 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 628 629 if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 630 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 631 632 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 633 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 634 635 mlx5_vhca_state_cap_handle(dev, set_hca_cap); 636 637 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 638 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 639 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 640 641 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce)) 642 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, 643 mlx5_is_roce_on(dev)); 644 645 max_uc_list = max_uc_list_get_devlink_param(dev); 646 if (max_uc_list > 0) 647 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list, 648 ilog2(max_uc_list)); 649 650 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 651} 652 653/* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 654 * boot process. 655 * In case RoCE cap is writable in FW and user/devlink requested to change the 656 * cap, we are yet to query the final state of the above cap. 657 * Hence, the need for this function. 658 * 659 * Returns 660 * True: 661 * 1) RoCE cap is read only in FW and already disabled 662 * OR: 663 * 2) RoCE cap is writable in FW and user/devlink requested it off. 664 * 665 * In any other case, return False. 666 */ 667static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 668{ 669 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) || 670 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 671} 672 673static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 674{ 675 void *set_hca_cap; 676 int err; 677 678 if (is_roce_fw_disabled(dev)) 679 return 0; 680 681 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 682 if (err) 683 return err; 684 685 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 686 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 687 return 0; 688 689 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 690 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 691 MLX5_ST_SZ_BYTES(roce_cap)); 692 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 693 694 if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default)) 695 MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1); 696 697 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 698 return err; 699} 700 701static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev, 702 void *set_ctx) 703{ 704 void *set_hca_cap; 705 int err; 706 707 if (!MLX5_CAP_GEN(dev, port_selection_cap)) 708 return 0; 709 710 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION); 711 if (err) 712 return err; 713 714 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) || 715 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass)) 716 return 0; 717 718 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 719 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, 720 MLX5_ST_SZ_BYTES(port_selection_cap)); 721 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1); 722 723 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION); 724 725 return err; 726} 727 728static int set_hca_cap(struct mlx5_core_dev *dev) 729{ 730 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 731 void *set_ctx; 732 int err; 733 734 set_ctx = kzalloc(set_sz, GFP_KERNEL); 735 if (!set_ctx) 736 return -ENOMEM; 737 738 err = handle_hca_cap(dev, set_ctx); 739 if (err) { 740 mlx5_core_err(dev, "handle_hca_cap failed\n"); 741 goto out; 742 } 743 744 memset(set_ctx, 0, set_sz); 745 err = handle_hca_cap_atomic(dev, set_ctx); 746 if (err) { 747 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 748 goto out; 749 } 750 751 memset(set_ctx, 0, set_sz); 752 err = handle_hca_cap_odp(dev, set_ctx); 753 if (err) { 754 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 755 goto out; 756 } 757 758 memset(set_ctx, 0, set_sz); 759 err = handle_hca_cap_roce(dev, set_ctx); 760 if (err) { 761 mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 762 goto out; 763 } 764 765 memset(set_ctx, 0, set_sz); 766 err = handle_hca_cap_2(dev, set_ctx); 767 if (err) { 768 mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); 769 goto out; 770 } 771 772 memset(set_ctx, 0, set_sz); 773 err = handle_hca_cap_port_selection(dev, set_ctx); 774 if (err) { 775 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n"); 776 goto out; 777 } 778 779out: 780 kfree(set_ctx); 781 return err; 782} 783 784static int set_hca_ctrl(struct mlx5_core_dev *dev) 785{ 786 struct mlx5_reg_host_endianness he_in; 787 struct mlx5_reg_host_endianness he_out; 788 int err; 789 790 if (!mlx5_core_is_pf(dev)) 791 return 0; 792 793 memset(&he_in, 0, sizeof(he_in)); 794 he_in.he = MLX5_SET_HOST_ENDIANNESS; 795 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 796 &he_out, sizeof(he_out), 797 MLX5_REG_HOST_ENDIANNESS, 0, 1); 798 return err; 799} 800 801static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 802{ 803 int ret = 0; 804 805 /* Disable local_lb by default */ 806 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 807 ret = mlx5_nic_vport_update_local_lb(dev, false); 808 809 return ret; 810} 811 812int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 813{ 814 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 815 816 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 817 MLX5_SET(enable_hca_in, in, function_id, func_id); 818 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 819 dev->caps.embedded_cpu); 820 return mlx5_cmd_exec_in(dev, enable_hca, in); 821} 822 823int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 824{ 825 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 826 827 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 828 MLX5_SET(disable_hca_in, in, function_id, func_id); 829 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 830 dev->caps.embedded_cpu); 831 return mlx5_cmd_exec_in(dev, disable_hca, in); 832} 833 834static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 835{ 836 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 837 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 838 u32 sup_issi; 839 int err; 840 841 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 842 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 843 if (err) { 844 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); 845 u8 status = MLX5_GET(query_issi_out, query_out, status); 846 847 if (!status || syndrome == MLX5_DRIVER_SYND) { 848 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 849 err, status, syndrome); 850 return err; 851 } 852 853 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 854 dev->issi = 0; 855 return 0; 856 } 857 858 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 859 860 if (sup_issi & (1 << 1)) { 861 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 862 863 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 864 MLX5_SET(set_issi_in, set_in, current_issi, 1); 865 err = mlx5_cmd_exec_in(dev, set_issi, set_in); 866 if (err) { 867 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 868 err); 869 return err; 870 } 871 872 dev->issi = 1; 873 874 return 0; 875 } else if (sup_issi & (1 << 0) || !sup_issi) { 876 return 0; 877 } 878 879 return -EOPNOTSUPP; 880} 881 882static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 883 const struct pci_device_id *id) 884{ 885 int err = 0; 886 887 mutex_init(&dev->pci_status_mutex); 888 pci_set_drvdata(dev->pdev, dev); 889 890 dev->bar_addr = pci_resource_start(pdev, 0); 891 892 err = mlx5_pci_enable_device(dev); 893 if (err) { 894 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 895 return err; 896 } 897 898 err = request_bar(pdev); 899 if (err) { 900 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 901 goto err_disable; 902 } 903 904 pci_set_master(pdev); 905 906 err = set_dma_caps(pdev); 907 if (err) { 908 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 909 goto err_clr_master; 910 } 911 912 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 913 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 914 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 915 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 916 917 dev->iseg_base = dev->bar_addr; 918 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 919 if (!dev->iseg) { 920 err = -ENOMEM; 921 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 922 goto err_clr_master; 923 } 924 925 mlx5_pci_vsc_init(dev); 926 return 0; 927 928err_clr_master: 929 release_bar(dev->pdev); 930err_disable: 931 mlx5_pci_disable_device(dev); 932 return err; 933} 934 935static void mlx5_pci_close(struct mlx5_core_dev *dev) 936{ 937 /* health work might still be active, and it needs pci bar in 938 * order to know the NIC state. Therefore, drain the health WQ 939 * before removing the pci bars 940 */ 941 mlx5_drain_health_wq(dev); 942 iounmap(dev->iseg); 943 release_bar(dev->pdev); 944 mlx5_pci_disable_device(dev); 945} 946 947static void mlx5_register_hca_devcom_comp(struct mlx5_core_dev *dev) 948{ 949 /* This component is use to sync adding core_dev to lag_dev and to sync 950 * changes of mlx5_adev_devices between LAG layer and other layers. 951 */ 952 if (!mlx5_lag_is_supported(dev)) 953 return; 954 955 dev->priv.hca_devcom_comp = 956 mlx5_devcom_register_component(dev->priv.devc, MLX5_DEVCOM_HCA_PORTS, 957 mlx5_query_nic_system_image_guid(dev), 958 NULL, dev); 959 if (IS_ERR(dev->priv.hca_devcom_comp)) 960 mlx5_core_err(dev, "Failed to register devcom HCA component\n"); 961} 962 963static void mlx5_unregister_hca_devcom_comp(struct mlx5_core_dev *dev) 964{ 965 mlx5_devcom_unregister_component(dev->priv.hca_devcom_comp); 966} 967 968static int mlx5_init_once(struct mlx5_core_dev *dev) 969{ 970 int err; 971 972 dev->priv.devc = mlx5_devcom_register_device(dev); 973 if (IS_ERR(dev->priv.devc)) 974 mlx5_core_warn(dev, "failed to register devcom device %ld\n", 975 PTR_ERR(dev->priv.devc)); 976 mlx5_register_hca_devcom_comp(dev); 977 978 err = mlx5_query_board_id(dev); 979 if (err) { 980 mlx5_core_err(dev, "query board id failed\n"); 981 goto err_devcom; 982 } 983 984 err = mlx5_irq_table_init(dev); 985 if (err) { 986 mlx5_core_err(dev, "failed to initialize irq table\n"); 987 goto err_devcom; 988 } 989 990 err = mlx5_eq_table_init(dev); 991 if (err) { 992 mlx5_core_err(dev, "failed to initialize eq\n"); 993 goto err_irq_cleanup; 994 } 995 996 err = mlx5_events_init(dev); 997 if (err) { 998 mlx5_core_err(dev, "failed to initialize events\n"); 999 goto err_eq_cleanup; 1000 } 1001 1002 err = mlx5_fw_reset_init(dev); 1003 if (err) { 1004 mlx5_core_err(dev, "failed to initialize fw reset events\n"); 1005 goto err_events_cleanup; 1006 } 1007 1008 mlx5_cq_debugfs_init(dev); 1009 1010 mlx5_init_reserved_gids(dev); 1011 1012 mlx5_init_clock(dev); 1013 1014 dev->vxlan = mlx5_vxlan_create(dev); 1015 dev->geneve = mlx5_geneve_create(dev); 1016 1017 err = mlx5_init_rl_table(dev); 1018 if (err) { 1019 mlx5_core_err(dev, "Failed to init rate limiting\n"); 1020 goto err_tables_cleanup; 1021 } 1022 1023 err = mlx5_mpfs_init(dev); 1024 if (err) { 1025 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 1026 goto err_rl_cleanup; 1027 } 1028 1029 err = mlx5_sriov_init(dev); 1030 if (err) { 1031 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 1032 goto err_mpfs_cleanup; 1033 } 1034 1035 err = mlx5_eswitch_init(dev); 1036 if (err) { 1037 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 1038 goto err_sriov_cleanup; 1039 } 1040 1041 err = mlx5_fpga_init(dev); 1042 if (err) { 1043 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 1044 goto err_eswitch_cleanup; 1045 } 1046 1047 err = mlx5_vhca_event_init(dev); 1048 if (err) { 1049 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 1050 goto err_fpga_cleanup; 1051 } 1052 1053 err = mlx5_sf_hw_table_init(dev); 1054 if (err) { 1055 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 1056 goto err_sf_hw_table_cleanup; 1057 } 1058 1059 err = mlx5_sf_table_init(dev); 1060 if (err) { 1061 mlx5_core_err(dev, "Failed to init SF table %d\n", err); 1062 goto err_sf_table_cleanup; 1063 } 1064 1065 err = mlx5_fs_core_alloc(dev); 1066 if (err) { 1067 mlx5_core_err(dev, "Failed to alloc flow steering\n"); 1068 goto err_fs; 1069 } 1070 1071 dev->dm = mlx5_dm_create(dev); 1072 if (IS_ERR(dev->dm)) 1073 mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm)); 1074 1075 dev->tracer = mlx5_fw_tracer_create(dev); 1076 dev->hv_vhca = mlx5_hv_vhca_create(dev); 1077 dev->rsc_dump = mlx5_rsc_dump_create(dev); 1078 1079 return 0; 1080 1081err_fs: 1082 mlx5_sf_table_cleanup(dev); 1083err_sf_table_cleanup: 1084 mlx5_sf_hw_table_cleanup(dev); 1085err_sf_hw_table_cleanup: 1086 mlx5_vhca_event_cleanup(dev); 1087err_fpga_cleanup: 1088 mlx5_fpga_cleanup(dev); 1089err_eswitch_cleanup: 1090 mlx5_eswitch_cleanup(dev->priv.eswitch); 1091err_sriov_cleanup: 1092 mlx5_sriov_cleanup(dev); 1093err_mpfs_cleanup: 1094 mlx5_mpfs_cleanup(dev); 1095err_rl_cleanup: 1096 mlx5_cleanup_rl_table(dev); 1097err_tables_cleanup: 1098 mlx5_geneve_destroy(dev->geneve); 1099 mlx5_vxlan_destroy(dev->vxlan); 1100 mlx5_cleanup_clock(dev); 1101 mlx5_cleanup_reserved_gids(dev); 1102 mlx5_cq_debugfs_cleanup(dev); 1103 mlx5_fw_reset_cleanup(dev); 1104err_events_cleanup: 1105 mlx5_events_cleanup(dev); 1106err_eq_cleanup: 1107 mlx5_eq_table_cleanup(dev); 1108err_irq_cleanup: 1109 mlx5_irq_table_cleanup(dev); 1110err_devcom: 1111 mlx5_unregister_hca_devcom_comp(dev); 1112 mlx5_devcom_unregister_device(dev->priv.devc); 1113 1114 return err; 1115} 1116 1117static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 1118{ 1119 mlx5_rsc_dump_destroy(dev); 1120 mlx5_hv_vhca_destroy(dev->hv_vhca); 1121 mlx5_fw_tracer_destroy(dev->tracer); 1122 mlx5_dm_cleanup(dev); 1123 mlx5_fs_core_free(dev); 1124 mlx5_sf_table_cleanup(dev); 1125 mlx5_sf_hw_table_cleanup(dev); 1126 mlx5_vhca_event_cleanup(dev); 1127 mlx5_fpga_cleanup(dev); 1128 mlx5_eswitch_cleanup(dev->priv.eswitch); 1129 mlx5_sriov_cleanup(dev); 1130 mlx5_mpfs_cleanup(dev); 1131 mlx5_cleanup_rl_table(dev); 1132 mlx5_geneve_destroy(dev->geneve); 1133 mlx5_vxlan_destroy(dev->vxlan); 1134 mlx5_cleanup_clock(dev); 1135 mlx5_cleanup_reserved_gids(dev); 1136 mlx5_cq_debugfs_cleanup(dev); 1137 mlx5_fw_reset_cleanup(dev); 1138 mlx5_events_cleanup(dev); 1139 mlx5_eq_table_cleanup(dev); 1140 mlx5_irq_table_cleanup(dev); 1141 mlx5_unregister_hca_devcom_comp(dev); 1142 mlx5_devcom_unregister_device(dev->priv.devc); 1143} 1144 1145static int mlx5_function_enable(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1146{ 1147 int err; 1148 1149 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 1150 fw_rev_min(dev), fw_rev_sub(dev)); 1151 1152 /* Only PFs hold the relevant PCIe information for this query */ 1153 if (mlx5_core_is_pf(dev)) 1154 pcie_print_link_status(dev->pdev); 1155 1156 /* wait for firmware to accept initialization segments configurations 1157 */ 1158 err = wait_fw_init(dev, timeout, 1159 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL), 1160 "pre-initializing"); 1161 if (err) 1162 return err; 1163 1164 err = mlx5_cmd_enable(dev); 1165 if (err) { 1166 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 1167 return err; 1168 } 1169 1170 mlx5_tout_query_iseg(dev); 1171 1172 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0, "initializing"); 1173 if (err) 1174 goto err_cmd_cleanup; 1175 1176 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 1177 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1178 1179 mlx5_start_health_poll(dev); 1180 1181 err = mlx5_core_enable_hca(dev, 0); 1182 if (err) { 1183 mlx5_core_err(dev, "enable hca failed\n"); 1184 goto stop_health_poll; 1185 } 1186 1187 err = mlx5_core_set_issi(dev); 1188 if (err) { 1189 mlx5_core_err(dev, "failed to set issi\n"); 1190 goto err_disable_hca; 1191 } 1192 1193 err = mlx5_satisfy_startup_pages(dev, 1); 1194 if (err) { 1195 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1196 goto err_disable_hca; 1197 } 1198 1199 err = mlx5_tout_query_dtor(dev); 1200 if (err) { 1201 mlx5_core_err(dev, "failed to read dtor\n"); 1202 goto reclaim_boot_pages; 1203 } 1204 1205 return 0; 1206 1207reclaim_boot_pages: 1208 mlx5_reclaim_startup_pages(dev); 1209err_disable_hca: 1210 mlx5_core_disable_hca(dev, 0); 1211stop_health_poll: 1212 mlx5_stop_health_poll(dev, boot); 1213err_cmd_cleanup: 1214 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1215 mlx5_cmd_disable(dev); 1216 1217 return err; 1218} 1219 1220static void mlx5_function_disable(struct mlx5_core_dev *dev, bool boot) 1221{ 1222 mlx5_reclaim_startup_pages(dev); 1223 mlx5_core_disable_hca(dev, 0); 1224 mlx5_stop_health_poll(dev, boot); 1225 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1226 mlx5_cmd_disable(dev); 1227} 1228 1229static int mlx5_function_open(struct mlx5_core_dev *dev) 1230{ 1231 int err; 1232 1233 err = set_hca_ctrl(dev); 1234 if (err) { 1235 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1236 return err; 1237 } 1238 1239 err = set_hca_cap(dev); 1240 if (err) { 1241 mlx5_core_err(dev, "set_hca_cap failed\n"); 1242 return err; 1243 } 1244 1245 err = mlx5_satisfy_startup_pages(dev, 0); 1246 if (err) { 1247 mlx5_core_err(dev, "failed to allocate init pages\n"); 1248 return err; 1249 } 1250 1251 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1252 if (err) { 1253 mlx5_core_err(dev, "init hca failed\n"); 1254 return err; 1255 } 1256 1257 mlx5_set_driver_version(dev); 1258 1259 err = mlx5_query_hca_caps(dev); 1260 if (err) { 1261 mlx5_core_err(dev, "query hca failed\n"); 1262 return err; 1263 } 1264 mlx5_start_health_fw_log_up(dev); 1265 return 0; 1266} 1267 1268static int mlx5_function_close(struct mlx5_core_dev *dev) 1269{ 1270 int err; 1271 1272 err = mlx5_cmd_teardown_hca(dev); 1273 if (err) { 1274 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1275 return err; 1276 } 1277 1278 return 0; 1279} 1280 1281static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1282{ 1283 int err; 1284 1285 err = mlx5_function_enable(dev, boot, timeout); 1286 if (err) 1287 return err; 1288 1289 err = mlx5_function_open(dev); 1290 if (err) 1291 mlx5_function_disable(dev, boot); 1292 return err; 1293} 1294 1295static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1296{ 1297 int err = mlx5_function_close(dev); 1298 1299 if (!err) 1300 mlx5_function_disable(dev, boot); 1301 else 1302 mlx5_stop_health_poll(dev, boot); 1303 1304 return err; 1305} 1306 1307static int mlx5_load(struct mlx5_core_dev *dev) 1308{ 1309 int err; 1310 1311 dev->priv.uar = mlx5_get_uars_page(dev); 1312 if (IS_ERR(dev->priv.uar)) { 1313 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1314 err = PTR_ERR(dev->priv.uar); 1315 return err; 1316 } 1317 1318 mlx5_events_start(dev); 1319 mlx5_pagealloc_start(dev); 1320 1321 err = mlx5_irq_table_create(dev); 1322 if (err) { 1323 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1324 goto err_irq_table; 1325 } 1326 1327 err = mlx5_eq_table_create(dev); 1328 if (err) { 1329 mlx5_core_err(dev, "Failed to create EQs\n"); 1330 goto err_eq_table; 1331 } 1332 1333 err = mlx5_fw_tracer_init(dev->tracer); 1334 if (err) { 1335 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1336 mlx5_fw_tracer_destroy(dev->tracer); 1337 dev->tracer = NULL; 1338 } 1339 1340 mlx5_fw_reset_events_start(dev); 1341 mlx5_hv_vhca_init(dev->hv_vhca); 1342 1343 err = mlx5_rsc_dump_init(dev); 1344 if (err) { 1345 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1346 mlx5_rsc_dump_destroy(dev); 1347 dev->rsc_dump = NULL; 1348 } 1349 1350 err = mlx5_fpga_device_start(dev); 1351 if (err) { 1352 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1353 goto err_fpga_start; 1354 } 1355 1356 err = mlx5_fs_core_init(dev); 1357 if (err) { 1358 mlx5_core_err(dev, "Failed to init flow steering\n"); 1359 goto err_fs; 1360 } 1361 1362 err = mlx5_core_set_hca_defaults(dev); 1363 if (err) { 1364 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1365 goto err_set_hca; 1366 } 1367 1368 mlx5_vhca_event_start(dev); 1369 1370 err = mlx5_sf_hw_table_create(dev); 1371 if (err) { 1372 mlx5_core_err(dev, "sf table create failed %d\n", err); 1373 goto err_vhca; 1374 } 1375 1376 err = mlx5_ec_init(dev); 1377 if (err) { 1378 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1379 goto err_ec; 1380 } 1381 1382 mlx5_lag_add_mdev(dev); 1383 err = mlx5_sriov_attach(dev); 1384 if (err) { 1385 mlx5_core_err(dev, "sriov init failed %d\n", err); 1386 goto err_sriov; 1387 } 1388 1389 mlx5_sf_dev_table_create(dev); 1390 1391 err = mlx5_devlink_traps_register(priv_to_devlink(dev)); 1392 if (err) 1393 goto err_traps_reg; 1394 1395 return 0; 1396 1397err_traps_reg: 1398 mlx5_sf_dev_table_destroy(dev); 1399 mlx5_sriov_detach(dev); 1400err_sriov: 1401 mlx5_lag_remove_mdev(dev); 1402 mlx5_ec_cleanup(dev); 1403err_ec: 1404 mlx5_sf_hw_table_destroy(dev); 1405err_vhca: 1406 mlx5_vhca_event_stop(dev); 1407err_set_hca: 1408 mlx5_fs_core_cleanup(dev); 1409err_fs: 1410 mlx5_fpga_device_stop(dev); 1411err_fpga_start: 1412 mlx5_rsc_dump_cleanup(dev); 1413 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1414 mlx5_fw_reset_events_stop(dev); 1415 mlx5_fw_tracer_cleanup(dev->tracer); 1416 mlx5_eq_table_destroy(dev); 1417err_eq_table: 1418 mlx5_irq_table_destroy(dev); 1419err_irq_table: 1420 mlx5_pagealloc_stop(dev); 1421 mlx5_events_stop(dev); 1422 mlx5_put_uars_page(dev, dev->priv.uar); 1423 return err; 1424} 1425 1426static void mlx5_unload(struct mlx5_core_dev *dev) 1427{ 1428 mlx5_eswitch_disable(dev->priv.eswitch); 1429 mlx5_devlink_traps_unregister(priv_to_devlink(dev)); 1430 mlx5_sf_dev_table_destroy(dev); 1431 mlx5_sriov_detach(dev); 1432 mlx5_lag_remove_mdev(dev); 1433 mlx5_ec_cleanup(dev); 1434 mlx5_sf_hw_table_destroy(dev); 1435 mlx5_vhca_event_stop(dev); 1436 mlx5_fs_core_cleanup(dev); 1437 mlx5_fpga_device_stop(dev); 1438 mlx5_rsc_dump_cleanup(dev); 1439 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1440 mlx5_fw_reset_events_stop(dev); 1441 mlx5_fw_tracer_cleanup(dev->tracer); 1442 mlx5_eq_table_destroy(dev); 1443 mlx5_irq_table_destroy(dev); 1444 mlx5_pagealloc_stop(dev); 1445 mlx5_events_stop(dev); 1446 mlx5_put_uars_page(dev, dev->priv.uar); 1447} 1448 1449int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev) 1450{ 1451 bool light_probe = mlx5_dev_is_lightweight(dev); 1452 int err = 0; 1453 1454 mutex_lock(&dev->intf_state_mutex); 1455 dev->state = MLX5_DEVICE_STATE_UP; 1456 1457 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1458 if (err) 1459 goto err_function; 1460 1461 err = mlx5_init_once(dev); 1462 if (err) { 1463 mlx5_core_err(dev, "sw objs init failed\n"); 1464 goto function_teardown; 1465 } 1466 1467 /* In case of light_probe, mlx5_devlink is already registered. 1468 * Hence, don't register devlink again. 1469 */ 1470 if (!light_probe) { 1471 err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1472 if (err) 1473 goto err_devlink_params_reg; 1474 } 1475 1476 err = mlx5_load(dev); 1477 if (err) 1478 goto err_load; 1479 1480 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1481 1482 err = mlx5_register_device(dev); 1483 if (err) 1484 goto err_register; 1485 1486 err = mlx5_crdump_enable(dev); 1487 if (err) 1488 mlx5_core_err(dev, "mlx5_crdump_enable failed with error code %d\n", err); 1489 1490 err = mlx5_hwmon_dev_register(dev); 1491 if (err) 1492 mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n", err); 1493 1494 mutex_unlock(&dev->intf_state_mutex); 1495 return 0; 1496 1497err_register: 1498 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1499 mlx5_unload(dev); 1500err_load: 1501 if (!light_probe) 1502 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1503err_devlink_params_reg: 1504 mlx5_cleanup_once(dev); 1505function_teardown: 1506 mlx5_function_teardown(dev, true); 1507err_function: 1508 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1509 mutex_unlock(&dev->intf_state_mutex); 1510 return err; 1511} 1512 1513int mlx5_init_one(struct mlx5_core_dev *dev) 1514{ 1515 struct devlink *devlink = priv_to_devlink(dev); 1516 int err; 1517 1518 devl_lock(devlink); 1519 devl_register(devlink); 1520 err = mlx5_init_one_devl_locked(dev); 1521 if (err) 1522 devl_unregister(devlink); 1523 devl_unlock(devlink); 1524 return err; 1525} 1526 1527void mlx5_uninit_one(struct mlx5_core_dev *dev) 1528{ 1529 struct devlink *devlink = priv_to_devlink(dev); 1530 1531 devl_lock(devlink); 1532 mutex_lock(&dev->intf_state_mutex); 1533 1534 mlx5_hwmon_dev_unregister(dev); 1535 mlx5_crdump_disable(dev); 1536 mlx5_unregister_device(dev); 1537 1538 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1539 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1540 __func__); 1541 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1542 mlx5_cleanup_once(dev); 1543 goto out; 1544 } 1545 1546 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1547 mlx5_unload(dev); 1548 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1549 mlx5_cleanup_once(dev); 1550 mlx5_function_teardown(dev, true); 1551out: 1552 mutex_unlock(&dev->intf_state_mutex); 1553 devl_unregister(devlink); 1554 devl_unlock(devlink); 1555} 1556 1557int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery) 1558{ 1559 int err = 0; 1560 u64 timeout; 1561 1562 devl_assert_locked(priv_to_devlink(dev)); 1563 mutex_lock(&dev->intf_state_mutex); 1564 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1565 mlx5_core_warn(dev, "interface is up, NOP\n"); 1566 goto out; 1567 } 1568 /* remove any previous indication of internal error */ 1569 dev->state = MLX5_DEVICE_STATE_UP; 1570 1571 if (recovery) 1572 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT); 1573 else 1574 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT); 1575 err = mlx5_function_setup(dev, false, timeout); 1576 if (err) 1577 goto err_function; 1578 1579 err = mlx5_load(dev); 1580 if (err) 1581 goto err_load; 1582 1583 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1584 1585 err = mlx5_attach_device(dev); 1586 if (err) 1587 goto err_attach; 1588 1589 mutex_unlock(&dev->intf_state_mutex); 1590 return 0; 1591 1592err_attach: 1593 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1594 mlx5_unload(dev); 1595err_load: 1596 mlx5_function_teardown(dev, false); 1597err_function: 1598 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1599out: 1600 mutex_unlock(&dev->intf_state_mutex); 1601 return err; 1602} 1603 1604int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery) 1605{ 1606 struct devlink *devlink = priv_to_devlink(dev); 1607 int ret; 1608 1609 devl_lock(devlink); 1610 ret = mlx5_load_one_devl_locked(dev, recovery); 1611 devl_unlock(devlink); 1612 return ret; 1613} 1614 1615void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend) 1616{ 1617 devl_assert_locked(priv_to_devlink(dev)); 1618 mutex_lock(&dev->intf_state_mutex); 1619 1620 mlx5_detach_device(dev, suspend); 1621 1622 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1623 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1624 __func__); 1625 goto out; 1626 } 1627 1628 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1629 mlx5_unload(dev); 1630 mlx5_function_teardown(dev, false); 1631out: 1632 mutex_unlock(&dev->intf_state_mutex); 1633} 1634 1635void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend) 1636{ 1637 struct devlink *devlink = priv_to_devlink(dev); 1638 1639 devl_lock(devlink); 1640 mlx5_unload_one_devl_locked(dev, suspend); 1641 devl_unlock(devlink); 1642} 1643 1644/* In case of light probe, we don't need a full query of hca_caps, but only the bellow caps. 1645 * A full query of hca_caps will be done when the device will reload. 1646 */ 1647static int mlx5_query_hca_caps_light(struct mlx5_core_dev *dev) 1648{ 1649 int err; 1650 1651 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 1652 if (err) 1653 return err; 1654 1655 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { 1656 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS, 1657 HCA_CAP_OPMOD_GET_CUR); 1658 if (err) 1659 return err; 1660 } 1661 1662 if (MLX5_CAP_GEN(dev, nic_flow_table) || 1663 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 1664 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE, 1665 HCA_CAP_OPMOD_GET_CUR); 1666 if (err) 1667 return err; 1668 } 1669 1670 if (MLX5_CAP_GEN_64(dev, general_obj_types) & 1671 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 1672 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION, 1673 HCA_CAP_OPMOD_GET_CUR); 1674 if (err) 1675 return err; 1676 } 1677 1678 return 0; 1679} 1680 1681int mlx5_init_one_light(struct mlx5_core_dev *dev) 1682{ 1683 struct devlink *devlink = priv_to_devlink(dev); 1684 int err; 1685 1686 devl_lock(devlink); 1687 devl_register(devlink); 1688 dev->state = MLX5_DEVICE_STATE_UP; 1689 err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1690 if (err) { 1691 mlx5_core_warn(dev, "mlx5_function_enable err=%d\n", err); 1692 goto out; 1693 } 1694 1695 err = mlx5_query_hca_caps_light(dev); 1696 if (err) { 1697 mlx5_core_warn(dev, "mlx5_query_hca_caps_light err=%d\n", err); 1698 goto query_hca_caps_err; 1699 } 1700 1701 err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1702 if (err) { 1703 mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err); 1704 goto query_hca_caps_err; 1705 } 1706 1707 devl_unlock(devlink); 1708 return 0; 1709 1710query_hca_caps_err: 1711 mlx5_function_disable(dev, true); 1712out: 1713 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1714 devl_unregister(devlink); 1715 devl_unlock(devlink); 1716 return err; 1717} 1718 1719void mlx5_uninit_one_light(struct mlx5_core_dev *dev) 1720{ 1721 struct devlink *devlink = priv_to_devlink(dev); 1722 1723 devl_lock(devlink); 1724 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1725 devl_unregister(devlink); 1726 devl_unlock(devlink); 1727 if (dev->state != MLX5_DEVICE_STATE_UP) 1728 return; 1729 mlx5_function_disable(dev, true); 1730} 1731 1732/* xxx_light() function are used in order to configure the device without full 1733 * init (light init). e.g.: There isn't a point in reload a device to light state. 1734 * Hence, mlx5_load_one_light() isn't needed. 1735 */ 1736 1737void mlx5_unload_one_light(struct mlx5_core_dev *dev) 1738{ 1739 if (dev->state != MLX5_DEVICE_STATE_UP) 1740 return; 1741 mlx5_function_disable(dev, false); 1742 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1743} 1744 1745static const int types[] = { 1746 MLX5_CAP_GENERAL, 1747 MLX5_CAP_GENERAL_2, 1748 MLX5_CAP_ETHERNET_OFFLOADS, 1749 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1750 MLX5_CAP_ODP, 1751 MLX5_CAP_ATOMIC, 1752 MLX5_CAP_ROCE, 1753 MLX5_CAP_IPOIB_OFFLOADS, 1754 MLX5_CAP_FLOW_TABLE, 1755 MLX5_CAP_ESWITCH_FLOW_TABLE, 1756 MLX5_CAP_ESWITCH, 1757 MLX5_CAP_QOS, 1758 MLX5_CAP_DEBUG, 1759 MLX5_CAP_DEV_MEM, 1760 MLX5_CAP_DEV_EVENT, 1761 MLX5_CAP_TLS, 1762 MLX5_CAP_VDPA_EMULATION, 1763 MLX5_CAP_IPSEC, 1764 MLX5_CAP_PORT_SELECTION, 1765 MLX5_CAP_MACSEC, 1766 MLX5_CAP_ADV_VIRTUALIZATION, 1767 MLX5_CAP_CRYPTO, 1768}; 1769 1770static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 1771{ 1772 int type; 1773 int i; 1774 1775 for (i = 0; i < ARRAY_SIZE(types); i++) { 1776 type = types[i]; 1777 kfree(dev->caps.hca[type]); 1778 } 1779} 1780 1781static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 1782{ 1783 struct mlx5_hca_cap *cap; 1784 int type; 1785 int i; 1786 1787 for (i = 0; i < ARRAY_SIZE(types); i++) { 1788 cap = kzalloc(sizeof(*cap), GFP_KERNEL); 1789 if (!cap) 1790 goto err; 1791 type = types[i]; 1792 dev->caps.hca[type] = cap; 1793 } 1794 1795 return 0; 1796 1797err: 1798 mlx5_hca_caps_free(dev); 1799 return -ENOMEM; 1800} 1801 1802static int vhca_id_show(struct seq_file *file, void *priv) 1803{ 1804 struct mlx5_core_dev *dev = file->private; 1805 1806 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id)); 1807 return 0; 1808} 1809 1810DEFINE_SHOW_ATTRIBUTE(vhca_id); 1811 1812int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1813{ 1814 struct mlx5_priv *priv = &dev->priv; 1815 int err; 1816 1817 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1818 lockdep_register_key(&dev->lock_key); 1819 mutex_init(&dev->intf_state_mutex); 1820 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key); 1821 mutex_init(&dev->mlx5e_res.uplink_netdev_lock); 1822 1823 mutex_init(&priv->bfregs.reg_head.lock); 1824 mutex_init(&priv->bfregs.wc_head.lock); 1825 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1826 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1827 1828 mutex_init(&priv->alloc_mutex); 1829 mutex_init(&priv->pgdir_mutex); 1830 INIT_LIST_HEAD(&priv->pgdir_list); 1831 1832 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 1833 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), 1834 mlx5_debugfs_root); 1835 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops); 1836 INIT_LIST_HEAD(&priv->traps); 1837 1838 err = mlx5_cmd_init(dev); 1839 if (err) { 1840 mlx5_core_err(dev, "Failed initializing cmdif SW structs, aborting\n"); 1841 goto err_cmd_init; 1842 } 1843 1844 err = mlx5_tout_init(dev); 1845 if (err) { 1846 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 1847 goto err_timeout_init; 1848 } 1849 1850 err = mlx5_health_init(dev); 1851 if (err) 1852 goto err_health_init; 1853 1854 err = mlx5_pagealloc_init(dev); 1855 if (err) 1856 goto err_pagealloc_init; 1857 1858 err = mlx5_adev_init(dev); 1859 if (err) 1860 goto err_adev_init; 1861 1862 err = mlx5_hca_caps_alloc(dev); 1863 if (err) 1864 goto err_hca_caps; 1865 1866 /* The conjunction of sw_vhca_id with sw_owner_id will be a global 1867 * unique id per function which uses mlx5_core. 1868 * Those values are supplied to FW as part of the init HCA command to 1869 * be used by both driver and FW when it's applicable. 1870 */ 1871 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1, 1872 MAX_SW_VHCA_ID, 1873 GFP_KERNEL); 1874 if (dev->priv.sw_vhca_id < 0) 1875 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n", 1876 dev->priv.sw_vhca_id); 1877 1878 return 0; 1879 1880err_hca_caps: 1881 mlx5_adev_cleanup(dev); 1882err_adev_init: 1883 mlx5_pagealloc_cleanup(dev); 1884err_pagealloc_init: 1885 mlx5_health_cleanup(dev); 1886err_health_init: 1887 mlx5_tout_cleanup(dev); 1888err_timeout_init: 1889 mlx5_cmd_cleanup(dev); 1890err_cmd_init: 1891 debugfs_remove(dev->priv.dbg.dbg_root); 1892 mutex_destroy(&priv->pgdir_mutex); 1893 mutex_destroy(&priv->alloc_mutex); 1894 mutex_destroy(&priv->bfregs.wc_head.lock); 1895 mutex_destroy(&priv->bfregs.reg_head.lock); 1896 mutex_destroy(&dev->intf_state_mutex); 1897 lockdep_unregister_key(&dev->lock_key); 1898 return err; 1899} 1900 1901void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1902{ 1903 struct mlx5_priv *priv = &dev->priv; 1904 1905 if (priv->sw_vhca_id > 0) 1906 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id); 1907 1908 mlx5_hca_caps_free(dev); 1909 mlx5_adev_cleanup(dev); 1910 mlx5_pagealloc_cleanup(dev); 1911 mlx5_health_cleanup(dev); 1912 mlx5_tout_cleanup(dev); 1913 mlx5_cmd_cleanup(dev); 1914 debugfs_remove_recursive(dev->priv.dbg.dbg_root); 1915 mutex_destroy(&priv->pgdir_mutex); 1916 mutex_destroy(&priv->alloc_mutex); 1917 mutex_destroy(&priv->bfregs.wc_head.lock); 1918 mutex_destroy(&priv->bfregs.reg_head.lock); 1919 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock); 1920 mutex_destroy(&dev->intf_state_mutex); 1921 lockdep_unregister_key(&dev->lock_key); 1922} 1923 1924static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 1925{ 1926 struct mlx5_core_dev *dev; 1927 struct devlink *devlink; 1928 int err; 1929 1930 devlink = mlx5_devlink_alloc(&pdev->dev); 1931 if (!devlink) { 1932 dev_err(&pdev->dev, "devlink alloc failed\n"); 1933 return -ENOMEM; 1934 } 1935 1936 dev = devlink_priv(devlink); 1937 dev->device = &pdev->dev; 1938 dev->pdev = pdev; 1939 1940 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1941 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1942 1943 dev->priv.adev_idx = mlx5_adev_idx_alloc(); 1944 if (dev->priv.adev_idx < 0) { 1945 err = dev->priv.adev_idx; 1946 goto adev_init_err; 1947 } 1948 1949 err = mlx5_mdev_init(dev, prof_sel); 1950 if (err) 1951 goto mdev_init_err; 1952 1953 err = mlx5_pci_init(dev, pdev, id); 1954 if (err) { 1955 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1956 err); 1957 goto pci_init_err; 1958 } 1959 1960 err = mlx5_init_one(dev); 1961 if (err) { 1962 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 1963 err); 1964 goto err_init_one; 1965 } 1966 1967 pci_save_state(pdev); 1968 return 0; 1969 1970err_init_one: 1971 mlx5_pci_close(dev); 1972pci_init_err: 1973 mlx5_mdev_uninit(dev); 1974mdev_init_err: 1975 mlx5_adev_idx_free(dev->priv.adev_idx); 1976adev_init_err: 1977 mlx5_devlink_free(devlink); 1978 1979 return err; 1980} 1981 1982static void remove_one(struct pci_dev *pdev) 1983{ 1984 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1985 struct devlink *devlink = priv_to_devlink(dev); 1986 1987 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 1988 mlx5_drain_fw_reset(dev); 1989 mlx5_drain_health_wq(dev); 1990 mlx5_sriov_disable(pdev, false); 1991 mlx5_uninit_one(dev); 1992 mlx5_pci_close(dev); 1993 mlx5_mdev_uninit(dev); 1994 mlx5_adev_idx_free(dev->priv.adev_idx); 1995 mlx5_devlink_free(devlink); 1996} 1997 1998#define mlx5_pci_trace(dev, fmt, ...) ({ \ 1999 struct mlx5_core_dev *__dev = (dev); \ 2000 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 2001 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 2002 __dev->pci_status, ##__VA_ARGS__); \ 2003}) 2004 2005static const char *result2str(enum pci_ers_result result) 2006{ 2007 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 2008 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 2009 result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 2010 "unknown"; 2011} 2012 2013static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 2014 pci_channel_state_t state) 2015{ 2016 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2017 enum pci_ers_result res; 2018 2019 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 2020 2021 mlx5_enter_error_state(dev, false); 2022 mlx5_error_sw_reset(dev); 2023 mlx5_unload_one(dev, false); 2024 mlx5_drain_health_wq(dev); 2025 mlx5_pci_disable_device(dev); 2026 2027 res = state == pci_channel_io_perm_failure ? 2028 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 2029 2030 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n", 2031 __func__, dev->state, dev->pci_status, res, result2str(res)); 2032 return res; 2033} 2034 2035/* wait for the device to show vital signs by waiting 2036 * for the health counter to start counting. 2037 */ 2038static int wait_vital(struct pci_dev *pdev) 2039{ 2040 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2041 struct mlx5_core_health *health = &dev->priv.health; 2042 const int niter = 100; 2043 u32 last_count = 0; 2044 u32 count; 2045 int i; 2046 2047 for (i = 0; i < niter; i++) { 2048 count = ioread32be(health->health_counter); 2049 if (count && count != 0xffffffff) { 2050 if (last_count && last_count != count) { 2051 mlx5_core_info(dev, 2052 "wait vital counter value 0x%x after %d iterations\n", 2053 count, i); 2054 return 0; 2055 } 2056 last_count = count; 2057 } 2058 msleep(50); 2059 } 2060 2061 return -ETIMEDOUT; 2062} 2063 2064static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 2065{ 2066 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 2067 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2068 int err; 2069 2070 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n", 2071 __func__, dev->state, dev->pci_status); 2072 2073 err = mlx5_pci_enable_device(dev); 2074 if (err) { 2075 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 2076 __func__, err); 2077 goto out; 2078 } 2079 2080 pci_set_master(pdev); 2081 pci_restore_state(pdev); 2082 pci_save_state(pdev); 2083 2084 err = wait_vital(pdev); 2085 if (err) { 2086 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 2087 __func__, err); 2088 goto out; 2089 } 2090 2091 res = PCI_ERS_RESULT_RECOVERED; 2092out: 2093 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n", 2094 __func__, dev->state, dev->pci_status, err, res, result2str(res)); 2095 return res; 2096} 2097 2098static void mlx5_pci_resume(struct pci_dev *pdev) 2099{ 2100 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2101 int err; 2102 2103 mlx5_pci_trace(dev, "Enter, loading driver..\n"); 2104 2105 err = mlx5_load_one(dev, false); 2106 2107 if (!err) 2108 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter, 2109 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY); 2110 2111 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 2112 !err ? "recovered" : "Failed"); 2113} 2114 2115static const struct pci_error_handlers mlx5_err_handler = { 2116 .error_detected = mlx5_pci_err_detected, 2117 .slot_reset = mlx5_pci_slot_reset, 2118 .resume = mlx5_pci_resume 2119}; 2120 2121static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 2122{ 2123 bool fast_teardown = false, force_teardown = false; 2124 int ret = 1; 2125 2126 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 2127 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 2128 2129 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 2130 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 2131 2132 if (!fast_teardown && !force_teardown) 2133 return -EOPNOTSUPP; 2134 2135 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 2136 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 2137 return -EAGAIN; 2138 } 2139 2140 /* Panic tear down fw command will stop the PCI bus communication 2141 * with the HCA, so the health poll is no longer needed. 2142 */ 2143 mlx5_drain_health_wq(dev); 2144 mlx5_stop_health_poll(dev, false); 2145 2146 ret = mlx5_cmd_fast_teardown_hca(dev); 2147 if (!ret) 2148 goto succeed; 2149 2150 ret = mlx5_cmd_force_teardown_hca(dev); 2151 if (!ret) 2152 goto succeed; 2153 2154 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 2155 mlx5_start_health_poll(dev); 2156 return ret; 2157 2158succeed: 2159 mlx5_enter_error_state(dev, true); 2160 2161 /* Some platforms requiring freeing the IRQ's in the shutdown 2162 * flow. If they aren't freed they can't be allocated after 2163 * kexec. There is no need to cleanup the mlx5_core software 2164 * contexts. 2165 */ 2166 mlx5_core_eq_free_irqs(dev); 2167 2168 return 0; 2169} 2170 2171static void shutdown(struct pci_dev *pdev) 2172{ 2173 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2174 int err; 2175 2176 mlx5_core_info(dev, "Shutdown was called\n"); 2177 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 2178 err = mlx5_try_fast_unload(dev); 2179 if (err) 2180 mlx5_unload_one(dev, false); 2181 mlx5_pci_disable_device(dev); 2182} 2183 2184static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 2185{ 2186 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2187 2188 mlx5_unload_one(dev, true); 2189 2190 return 0; 2191} 2192 2193static int mlx5_resume(struct pci_dev *pdev) 2194{ 2195 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2196 2197 return mlx5_load_one(dev, false); 2198} 2199 2200static const struct pci_device_id mlx5_core_pci_table[] = { 2201 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 2202 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 2203 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 2204 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 2205 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 2206 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 2207 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 2208 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 2209 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 2210 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 2211 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 2212 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 2213 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 2214 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 2215 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 2216 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 2217 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 2218 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 2219 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 2220 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2221 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 2222 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 2223 { 0, } 2224}; 2225 2226MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 2227 2228void mlx5_disable_device(struct mlx5_core_dev *dev) 2229{ 2230 mlx5_error_sw_reset(dev); 2231 mlx5_unload_one_devl_locked(dev, false); 2232} 2233 2234int mlx5_recover_device(struct mlx5_core_dev *dev) 2235{ 2236 if (!mlx5_core_is_sf(dev)) { 2237 mlx5_pci_disable_device(dev); 2238 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 2239 return -EIO; 2240 } 2241 2242 return mlx5_load_one_devl_locked(dev, true); 2243} 2244 2245static struct pci_driver mlx5_core_driver = { 2246 .name = KBUILD_MODNAME, 2247 .id_table = mlx5_core_pci_table, 2248 .probe = probe_one, 2249 .remove = remove_one, 2250 .suspend = mlx5_suspend, 2251 .resume = mlx5_resume, 2252 .shutdown = shutdown, 2253 .err_handler = &mlx5_err_handler, 2254 .sriov_configure = mlx5_core_sriov_configure, 2255 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 2256 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 2257}; 2258 2259/** 2260 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if 2261 * mlx5_core is its driver. 2262 * @pdev: The associated PCI device. 2263 * 2264 * Upon return the interface state lock stay held to let caller uses it safely. 2265 * Caller must ensure to use the returned mlx5 device for a narrow window 2266 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. 2267 * 2268 * Return: Pointer to the associated mlx5_core_dev or NULL. 2269 */ 2270struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) 2271{ 2272 struct mlx5_core_dev *mdev; 2273 2274 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); 2275 if (IS_ERR(mdev)) 2276 return NULL; 2277 2278 mutex_lock(&mdev->intf_state_mutex); 2279 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { 2280 mutex_unlock(&mdev->intf_state_mutex); 2281 return NULL; 2282 } 2283 2284 return mdev; 2285} 2286EXPORT_SYMBOL(mlx5_vf_get_core_dev); 2287 2288/** 2289 * mlx5_vf_put_core_dev - Put the mlx5 core device back. 2290 * @mdev: The mlx5 core device. 2291 * 2292 * Upon return the interface state lock is unlocked and caller should not 2293 * access the mdev any more. 2294 */ 2295void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) 2296{ 2297 mutex_unlock(&mdev->intf_state_mutex); 2298} 2299EXPORT_SYMBOL(mlx5_vf_put_core_dev); 2300 2301static void mlx5_core_verify_params(void) 2302{ 2303 if (prof_sel >= ARRAY_SIZE(profile)) { 2304 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 2305 prof_sel, 2306 ARRAY_SIZE(profile) - 1, 2307 MLX5_DEFAULT_PROF); 2308 prof_sel = MLX5_DEFAULT_PROF; 2309 } 2310} 2311 2312static int __init mlx5_init(void) 2313{ 2314 int err; 2315 2316 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 2317 "mlx5_core name not in sync with kernel module name"); 2318 2319 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 2320 2321 mlx5_core_verify_params(); 2322 mlx5_register_debugfs(); 2323 2324 err = mlx5e_init(); 2325 if (err) 2326 goto err_debug; 2327 2328 err = mlx5_sf_driver_register(); 2329 if (err) 2330 goto err_sf; 2331 2332 err = pci_register_driver(&mlx5_core_driver); 2333 if (err) 2334 goto err_pci; 2335 2336 return 0; 2337 2338err_pci: 2339 mlx5_sf_driver_unregister(); 2340err_sf: 2341 mlx5e_cleanup(); 2342err_debug: 2343 mlx5_unregister_debugfs(); 2344 return err; 2345} 2346 2347static void __exit mlx5_cleanup(void) 2348{ 2349 pci_unregister_driver(&mlx5_core_driver); 2350 mlx5_sf_driver_unregister(); 2351 mlx5e_cleanup(); 2352 mlx5_unregister_debugfs(); 2353} 2354 2355module_init(mlx5_init); 2356module_exit(mlx5_cleanup); 2357