1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2/* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved. */ 3 4#include <devlink.h> 5 6#include "fw_reset.h" 7#include "diag/fw_tracer.h" 8#include "lib/tout.h" 9 10enum { 11 MLX5_FW_RESET_FLAGS_RESET_REQUESTED, 12 MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, 13 MLX5_FW_RESET_FLAGS_PENDING_COMP, 14 MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, 15 MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED 16}; 17 18struct mlx5_fw_reset { 19 struct mlx5_core_dev *dev; 20 struct mlx5_nb nb; 21 struct workqueue_struct *wq; 22 struct work_struct fw_live_patch_work; 23 struct work_struct reset_request_work; 24 struct work_struct reset_unload_work; 25 struct work_struct reset_reload_work; 26 struct work_struct reset_now_work; 27 struct work_struct reset_abort_work; 28 unsigned long reset_flags; 29 struct timer_list timer; 30 struct completion done; 31 int ret; 32}; 33 34enum { 35 MLX5_FW_RST_STATE_IDLE = 0, 36 MLX5_FW_RST_STATE_TOGGLE_REQ = 4, 37}; 38 39enum { 40 MLX5_RST_STATE_BIT_NUM = 12, 41 MLX5_RST_ACK_BIT_NUM = 22, 42}; 43 44static u8 mlx5_get_fw_rst_state(struct mlx5_core_dev *dev) 45{ 46 return (ioread32be(&dev->iseg->initializing) >> MLX5_RST_STATE_BIT_NUM) & 0xF; 47} 48 49static void mlx5_set_fw_rst_ack(struct mlx5_core_dev *dev) 50{ 51 iowrite32be(BIT(MLX5_RST_ACK_BIT_NUM), &dev->iseg->initializing); 52} 53 54static int mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink *devlink, u32 id, 55 struct devlink_param_gset_ctx *ctx, 56 struct netlink_ext_ack *extack) 57{ 58 struct mlx5_core_dev *dev = devlink_priv(devlink); 59 struct mlx5_fw_reset *fw_reset; 60 61 fw_reset = dev->priv.fw_reset; 62 63 if (ctx->val.vbool) 64 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags); 65 else 66 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags); 67 return 0; 68} 69 70static int mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink *devlink, u32 id, 71 struct devlink_param_gset_ctx *ctx) 72{ 73 struct mlx5_core_dev *dev = devlink_priv(devlink); 74 struct mlx5_fw_reset *fw_reset; 75 76 fw_reset = dev->priv.fw_reset; 77 78 ctx->val.vbool = !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, 79 &fw_reset->reset_flags); 80 return 0; 81} 82 83static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level, 84 u8 reset_type_sel, u8 sync_resp, bool sync_start) 85{ 86 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 87 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 88 89 MLX5_SET(mfrl_reg, in, reset_level, reset_level); 90 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel); 91 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp); 92 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start); 93 94 return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1); 95} 96 97static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level, 98 u8 *reset_type, u8 *reset_state) 99{ 100 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 101 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 102 int err; 103 104 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0); 105 if (err) 106 return err; 107 108 if (reset_level) 109 *reset_level = MLX5_GET(mfrl_reg, out, reset_level); 110 if (reset_type) 111 *reset_type = MLX5_GET(mfrl_reg, out, reset_type); 112 if (reset_state) 113 *reset_state = MLX5_GET(mfrl_reg, out, reset_state); 114 115 return 0; 116} 117 118int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type) 119{ 120 return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL); 121} 122 123static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev, 124 struct netlink_ext_ack *extack) 125{ 126 u8 reset_state; 127 128 if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state)) 129 goto out; 130 131 if (!reset_state) 132 return 0; 133 134 switch (reset_state) { 135 case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION: 136 case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS: 137 NL_SET_ERR_MSG_MOD(extack, "Sync reset still in progress"); 138 return -EBUSY; 139 case MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT: 140 NL_SET_ERR_MSG_MOD(extack, "Sync reset negotiation timeout"); 141 return -ETIMEDOUT; 142 case MLX5_MFRL_REG_RESET_STATE_NACK: 143 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset"); 144 return -EPERM; 145 case MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT: 146 NL_SET_ERR_MSG_MOD(extack, "Sync reset unload timeout"); 147 return -ETIMEDOUT; 148 } 149 150out: 151 NL_SET_ERR_MSG_MOD(extack, "Sync reset failed"); 152 return -EIO; 153} 154 155int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel, 156 struct netlink_ext_ack *extack) 157{ 158 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 159 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 160 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {}; 161 int err, rst_res; 162 163 set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags); 164 165 MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3); 166 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel); 167 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1); 168 err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out), 169 MLX5_REG_MFRL, 0, 1, false); 170 if (!err) 171 return 0; 172 173 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags); 174 if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state)) { 175 rst_res = mlx5_fw_reset_get_reset_state_err(dev, extack); 176 return rst_res ? rst_res : err; 177 } 178 179 NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed"); 180 return mlx5_cmd_check(dev, err, in, out); 181} 182 183int mlx5_fw_reset_verify_fw_complete(struct mlx5_core_dev *dev, 184 struct netlink_ext_ack *extack) 185{ 186 u8 rst_state; 187 int err; 188 189 err = mlx5_fw_reset_get_reset_state_err(dev, extack); 190 if (err) 191 return err; 192 193 rst_state = mlx5_get_fw_rst_state(dev); 194 if (!rst_state) 195 return 0; 196 197 mlx5_core_err(dev, "Sync reset did not complete, state=%d\n", rst_state); 198 NL_SET_ERR_MSG_MOD(extack, "Sync reset did not complete successfully"); 199 return rst_state; 200} 201 202int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev) 203{ 204 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false); 205} 206 207static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool unloaded) 208{ 209 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 210 211 /* if this is the driver that initiated the fw reset, devlink completed the reload */ 212 if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) { 213 complete(&fw_reset->done); 214 } else { 215 if (!unloaded) 216 mlx5_unload_one(dev, false); 217 if (mlx5_health_wait_pci_up(dev)) 218 mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n"); 219 else 220 mlx5_load_one(dev, true); 221 devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0, 222 BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 223 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE)); 224 } 225} 226 227static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev) 228{ 229 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 230 231 del_timer_sync(&fw_reset->timer); 232} 233 234static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health) 235{ 236 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 237 238 if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) { 239 mlx5_core_warn(dev, "Reset request was already cleared\n"); 240 return -EALREADY; 241 } 242 243 mlx5_stop_sync_reset_poll(dev); 244 if (poll_health) 245 mlx5_start_health_poll(dev); 246 return 0; 247} 248 249static void mlx5_sync_reset_reload_work(struct work_struct *work) 250{ 251 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 252 reset_reload_work); 253 struct mlx5_core_dev *dev = fw_reset->dev; 254 255 mlx5_sync_reset_clear_reset_requested(dev, false); 256 mlx5_enter_error_state(dev, true); 257 mlx5_fw_reset_complete_reload(dev, false); 258} 259 260#define MLX5_RESET_POLL_INTERVAL (HZ / 10) 261static void poll_sync_reset(struct timer_list *t) 262{ 263 struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer); 264 struct mlx5_core_dev *dev = fw_reset->dev; 265 u32 fatal_error; 266 267 if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) 268 return; 269 270 fatal_error = mlx5_health_check_fatal_sensors(dev); 271 272 if (fatal_error) { 273 mlx5_core_warn(dev, "Got Device Reset\n"); 274 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags)) 275 queue_work(fw_reset->wq, &fw_reset->reset_reload_work); 276 else 277 mlx5_core_err(dev, "Device is being removed, Drop new reset work\n"); 278 return; 279 } 280 281 mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL)); 282} 283 284static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev) 285{ 286 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 287 288 timer_setup(&fw_reset->timer, poll_sync_reset, 0); 289 fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL); 290 add_timer(&fw_reset->timer); 291} 292 293static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev) 294{ 295 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false); 296} 297 298static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev) 299{ 300 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false); 301} 302 303static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev) 304{ 305 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 306 307 if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) { 308 mlx5_core_warn(dev, "Reset request was already set\n"); 309 return -EALREADY; 310 } 311 mlx5_stop_health_poll(dev, true); 312 mlx5_start_sync_reset_poll(dev); 313 return 0; 314} 315 316static void mlx5_fw_live_patch_event(struct work_struct *work) 317{ 318 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 319 fw_live_patch_work); 320 struct mlx5_core_dev *dev = fw_reset->dev; 321 322 mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev), 323 fw_rev_min(dev), fw_rev_sub(dev)); 324 325 if (mlx5_fw_tracer_reload(dev->tracer)) 326 mlx5_core_err(dev, "Failed to reload FW tracer\n"); 327} 328 329#if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE) 330static int mlx5_check_hotplug_interrupt(struct mlx5_core_dev *dev) 331{ 332 struct pci_dev *bridge = dev->pdev->bus->self; 333 u16 reg16; 334 int err; 335 336 if (!bridge) 337 return -EOPNOTSUPP; 338 339 err = pcie_capability_read_word(bridge, PCI_EXP_SLTCTL, ®16); 340 if (err) 341 return err; 342 343 if ((reg16 & PCI_EXP_SLTCTL_HPIE) && (reg16 & PCI_EXP_SLTCTL_DLLSCE)) { 344 mlx5_core_warn(dev, "FW reset is not supported as HotPlug is enabled\n"); 345 return -EOPNOTSUPP; 346 } 347 348 return 0; 349} 350#endif 351 352static const struct pci_device_id mgt_ifc_device_ids[] = { 353 { PCI_VDEVICE(MELLANOX, 0xc2d2) }, /* BlueField1 MGT interface device ID */ 354 { PCI_VDEVICE(MELLANOX, 0xc2d3) }, /* BlueField2 MGT interface device ID */ 355 { PCI_VDEVICE(MELLANOX, 0xc2d4) }, /* BlueField3-Lx MGT interface device ID */ 356 { PCI_VDEVICE(MELLANOX, 0xc2d5) }, /* BlueField3 MGT interface device ID */ 357 { PCI_VDEVICE(MELLANOX, 0xc2d6) }, /* BlueField4 MGT interface device ID */ 358}; 359 360static bool mlx5_is_mgt_ifc_pci_device(struct mlx5_core_dev *dev, u16 dev_id) 361{ 362 int i; 363 364 for (i = 0; i < ARRAY_SIZE(mgt_ifc_device_ids); ++i) 365 if (mgt_ifc_device_ids[i].device == dev_id) 366 return true; 367 368 return false; 369} 370 371static int mlx5_check_dev_ids(struct mlx5_core_dev *dev, u16 dev_id) 372{ 373 struct pci_bus *bridge_bus = dev->pdev->bus; 374 struct pci_dev *sdev; 375 u16 sdev_id; 376 int err; 377 378 /* Check that all functions under the pci bridge are PFs of 379 * this device otherwise fail this function. 380 */ 381 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) { 382 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id); 383 if (err) 384 return pcibios_err_to_errno(err); 385 386 if (sdev_id == dev_id) 387 continue; 388 389 if (mlx5_is_mgt_ifc_pci_device(dev, sdev_id)) 390 continue; 391 392 mlx5_core_warn(dev, "unrecognized dev_id (0x%x)\n", sdev_id); 393 return -EPERM; 394 } 395 return 0; 396} 397 398static bool mlx5_is_reset_now_capable(struct mlx5_core_dev *dev) 399{ 400 u16 dev_id; 401 int err; 402 403 if (!MLX5_CAP_GEN(dev, fast_teardown)) { 404 mlx5_core_warn(dev, "fast teardown is not supported by firmware\n"); 405 return false; 406 } 407 408#if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE) 409 err = mlx5_check_hotplug_interrupt(dev); 410 if (err) 411 return false; 412#endif 413 414 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id); 415 if (err) 416 return false; 417 return (!mlx5_check_dev_ids(dev, dev_id)); 418} 419 420static void mlx5_sync_reset_request_event(struct work_struct *work) 421{ 422 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 423 reset_request_work); 424 struct mlx5_core_dev *dev = fw_reset->dev; 425 int err; 426 427 if (test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags) || 428 !mlx5_is_reset_now_capable(dev)) { 429 err = mlx5_fw_reset_set_reset_sync_nack(dev); 430 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s", 431 err ? "Failed" : "Sent"); 432 return; 433 } 434 if (mlx5_sync_reset_set_reset_requested(dev)) 435 return; 436 437 err = mlx5_fw_reset_set_reset_sync_ack(dev); 438 if (err) 439 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err); 440 else 441 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n"); 442} 443 444static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev) 445{ 446 struct pci_bus *bridge_bus = dev->pdev->bus; 447 struct pci_dev *bridge = bridge_bus->self; 448 unsigned long timeout; 449 struct pci_dev *sdev; 450 u16 reg16, dev_id; 451 int cap, err; 452 453 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id); 454 if (err) 455 return pcibios_err_to_errno(err); 456 err = mlx5_check_dev_ids(dev, dev_id); 457 if (err) 458 return err; 459 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP); 460 if (!cap) 461 return -EOPNOTSUPP; 462 463 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) { 464 pci_save_state(sdev); 465 pci_cfg_access_lock(sdev); 466 } 467 /* PCI link toggle */ 468 err = pcie_capability_set_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD); 469 if (err) 470 return pcibios_err_to_errno(err); 471 msleep(500); 472 err = pcie_capability_clear_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD); 473 if (err) 474 return pcibios_err_to_errno(err); 475 476 /* Check link */ 477 if (!bridge->link_active_reporting) { 478 mlx5_core_warn(dev, "No PCI link reporting capability\n"); 479 msleep(1000); 480 goto restore; 481 } 482 483 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE)); 484 do { 485 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, ®16); 486 if (err) 487 return pcibios_err_to_errno(err); 488 if (reg16 & PCI_EXP_LNKSTA_DLLLA) 489 break; 490 msleep(20); 491 } while (!time_after(jiffies, timeout)); 492 493 if (reg16 & PCI_EXP_LNKSTA_DLLLA) { 494 mlx5_core_info(dev, "PCI Link up\n"); 495 } else { 496 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n", 497 reg16, mlx5_tout_ms(dev, PCI_TOGGLE)); 498 err = -ETIMEDOUT; 499 goto restore; 500 } 501 502 do { 503 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, ®16); 504 if (err) 505 return pcibios_err_to_errno(err); 506 if (reg16 == dev_id) 507 break; 508 msleep(20); 509 } while (!time_after(jiffies, timeout)); 510 511 if (reg16 == dev_id) { 512 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n"); 513 } else { 514 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n", 515 reg16, mlx5_tout_ms(dev, PCI_TOGGLE)); 516 err = -ETIMEDOUT; 517 } 518 519restore: 520 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) { 521 pci_cfg_access_unlock(sdev); 522 pci_restore_state(sdev); 523 } 524 525 return err; 526} 527 528static void mlx5_sync_reset_now_event(struct work_struct *work) 529{ 530 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 531 reset_now_work); 532 struct mlx5_core_dev *dev = fw_reset->dev; 533 int err; 534 535 if (mlx5_sync_reset_clear_reset_requested(dev, false)) 536 return; 537 538 mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n"); 539 540 err = mlx5_cmd_fast_teardown_hca(dev); 541 if (err) { 542 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err); 543 goto done; 544 } 545 546 err = mlx5_pci_link_toggle(dev); 547 if (err) { 548 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, no reset done, err %d\n", err); 549 set_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags); 550 } 551 552 mlx5_enter_error_state(dev, true); 553done: 554 fw_reset->ret = err; 555 mlx5_fw_reset_complete_reload(dev, false); 556} 557 558static void mlx5_sync_reset_unload_event(struct work_struct *work) 559{ 560 struct mlx5_fw_reset *fw_reset; 561 struct mlx5_core_dev *dev; 562 unsigned long timeout; 563 bool reset_action; 564 u8 rst_state; 565 int err; 566 567 fw_reset = container_of(work, struct mlx5_fw_reset, reset_unload_work); 568 dev = fw_reset->dev; 569 570 if (mlx5_sync_reset_clear_reset_requested(dev, false)) 571 return; 572 573 mlx5_core_warn(dev, "Sync Reset Unload. Function is forced down.\n"); 574 575 err = mlx5_cmd_fast_teardown_hca(dev); 576 if (err) 577 mlx5_core_warn(dev, "Fast teardown failed, unloading, err %d\n", err); 578 else 579 mlx5_enter_error_state(dev, true); 580 581 if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) 582 mlx5_unload_one_devl_locked(dev, false); 583 else 584 mlx5_unload_one(dev, false); 585 586 mlx5_set_fw_rst_ack(dev); 587 mlx5_core_warn(dev, "Sync Reset Unload done, device reset expected\n"); 588 589 reset_action = false; 590 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, RESET_UNLOAD)); 591 do { 592 rst_state = mlx5_get_fw_rst_state(dev); 593 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ || 594 rst_state == MLX5_FW_RST_STATE_IDLE) { 595 reset_action = true; 596 break; 597 } 598 msleep(20); 599 } while (!time_after(jiffies, timeout)); 600 601 if (!reset_action) { 602 mlx5_core_err(dev, "Got timeout waiting for sync reset action, state = %u\n", 603 rst_state); 604 fw_reset->ret = -ETIMEDOUT; 605 goto done; 606 } 607 608 mlx5_core_warn(dev, "Sync Reset, got reset action. rst_state = %u\n", rst_state); 609 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ) { 610 err = mlx5_pci_link_toggle(dev); 611 if (err) { 612 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, err %d\n", err); 613 fw_reset->ret = err; 614 } 615 } 616 617done: 618 mlx5_fw_reset_complete_reload(dev, true); 619} 620 621static void mlx5_sync_reset_abort_event(struct work_struct *work) 622{ 623 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset, 624 reset_abort_work); 625 struct mlx5_core_dev *dev = fw_reset->dev; 626 627 if (mlx5_sync_reset_clear_reset_requested(dev, true)) 628 return; 629 mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n"); 630} 631 632static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe) 633{ 634 struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe; 635 u8 sync_event_rst_type; 636 637 sync_fw_update_eqe = &eqe->data.sync_fw_update; 638 sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK; 639 switch (sync_event_rst_type) { 640 case MLX5_SYNC_RST_STATE_RESET_REQUEST: 641 queue_work(fw_reset->wq, &fw_reset->reset_request_work); 642 break; 643 case MLX5_SYNC_RST_STATE_RESET_UNLOAD: 644 queue_work(fw_reset->wq, &fw_reset->reset_unload_work); 645 break; 646 case MLX5_SYNC_RST_STATE_RESET_NOW: 647 queue_work(fw_reset->wq, &fw_reset->reset_now_work); 648 break; 649 case MLX5_SYNC_RST_STATE_RESET_ABORT: 650 queue_work(fw_reset->wq, &fw_reset->reset_abort_work); 651 break; 652 } 653} 654 655static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data) 656{ 657 struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb); 658 struct mlx5_eqe *eqe = data; 659 660 if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags)) 661 return NOTIFY_DONE; 662 663 switch (eqe->sub_type) { 664 case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT: 665 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work); 666 break; 667 case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT: 668 mlx5_sync_reset_events_handle(fw_reset, eqe); 669 break; 670 default: 671 return NOTIFY_DONE; 672 } 673 674 return NOTIFY_OK; 675} 676 677int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev) 678{ 679 unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE); 680 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 681 unsigned long timeout; 682 int err; 683 684 if (MLX5_CAP_GEN(dev, pci_sync_for_fw_update_with_driver_unload)) 685 pci_sync_update_timeout += mlx5_tout_ms(dev, RESET_UNLOAD); 686 timeout = msecs_to_jiffies(pci_sync_update_timeout); 687 if (!wait_for_completion_timeout(&fw_reset->done, timeout)) { 688 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n", 689 pci_sync_update_timeout / 1000); 690 err = -ETIMEDOUT; 691 goto out; 692 } 693 err = fw_reset->ret; 694 if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) { 695 mlx5_unload_one_devl_locked(dev, false); 696 mlx5_load_one_devl_locked(dev, true); 697 } 698out: 699 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags); 700 return err; 701} 702 703void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev) 704{ 705 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 706 707 if (!fw_reset) 708 return; 709 710 MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT); 711 mlx5_eq_notifier_register(dev, &fw_reset->nb); 712} 713 714void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev) 715{ 716 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 717 718 if (!fw_reset) 719 return; 720 721 mlx5_eq_notifier_unregister(dev, &fw_reset->nb); 722} 723 724void mlx5_drain_fw_reset(struct mlx5_core_dev *dev) 725{ 726 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 727 728 if (!fw_reset) 729 return; 730 731 set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags); 732 cancel_work_sync(&fw_reset->fw_live_patch_work); 733 cancel_work_sync(&fw_reset->reset_request_work); 734 cancel_work_sync(&fw_reset->reset_unload_work); 735 cancel_work_sync(&fw_reset->reset_reload_work); 736 cancel_work_sync(&fw_reset->reset_now_work); 737 cancel_work_sync(&fw_reset->reset_abort_work); 738} 739 740static const struct devlink_param mlx5_fw_reset_devlink_params[] = { 741 DEVLINK_PARAM_GENERIC(ENABLE_REMOTE_DEV_RESET, BIT(DEVLINK_PARAM_CMODE_RUNTIME), 742 mlx5_fw_reset_enable_remote_dev_reset_get, 743 mlx5_fw_reset_enable_remote_dev_reset_set, NULL), 744}; 745 746int mlx5_fw_reset_init(struct mlx5_core_dev *dev) 747{ 748 struct mlx5_fw_reset *fw_reset; 749 int err; 750 751 if (!MLX5_CAP_MCAM_REG(dev, mfrl)) 752 return 0; 753 754 fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL); 755 if (!fw_reset) 756 return -ENOMEM; 757 fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events"); 758 if (!fw_reset->wq) { 759 kfree(fw_reset); 760 return -ENOMEM; 761 } 762 763 fw_reset->dev = dev; 764 dev->priv.fw_reset = fw_reset; 765 766 err = devl_params_register(priv_to_devlink(dev), 767 mlx5_fw_reset_devlink_params, 768 ARRAY_SIZE(mlx5_fw_reset_devlink_params)); 769 if (err) { 770 destroy_workqueue(fw_reset->wq); 771 kfree(fw_reset); 772 return err; 773 } 774 775 INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event); 776 INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event); 777 INIT_WORK(&fw_reset->reset_unload_work, mlx5_sync_reset_unload_event); 778 INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work); 779 INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event); 780 INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event); 781 782 init_completion(&fw_reset->done); 783 return 0; 784} 785 786void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev) 787{ 788 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; 789 790 if (!fw_reset) 791 return; 792 793 devl_params_unregister(priv_to_devlink(dev), 794 mlx5_fw_reset_devlink_params, 795 ARRAY_SIZE(mlx5_fw_reset_devlink_params)); 796 destroy_workqueue(fw_reset->wq); 797 kfree(dev->priv.fw_reset); 798} 799