1/* SPDX-License-Identifier: GPL-2.0 */
2/* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2023 Marvell.
5 *
6 */
7#ifndef OTX2_QOS_H
8#define OTX2_QOS_H
9
10#include <linux/types.h>
11#include <linux/netdevice.h>
12#include <linux/rhashtable.h>
13
14#define OTX2_QOS_MAX_LVL		4
15#define OTX2_QOS_MAX_PRIO		7
16#define OTX2_QOS_MAX_LEAF_NODES                16
17
18enum qos_smq_operations {
19	QOS_CFG_SQ,
20	QOS_SMQ_FLUSH,
21};
22
23u64 otx2_get_txschq_rate_regval(struct otx2_nic *nic, u64 maxrate, u32 burst);
24
25int otx2_setup_tc_htb(struct net_device *ndev, struct tc_htb_qopt_offload *htb);
26int otx2_qos_get_qid(struct otx2_nic *pfvf);
27void otx2_qos_free_qid(struct otx2_nic *pfvf, int qidx);
28int otx2_qos_enable_sq(struct otx2_nic *pfvf, int qidx);
29void otx2_qos_disable_sq(struct otx2_nic *pfvf, int qidx);
30
31struct otx2_qos_cfg {
32	u16 schq[NIX_TXSCH_LVL_CNT];
33	u16 schq_contig[NIX_TXSCH_LVL_CNT];
34	int static_node_pos[NIX_TXSCH_LVL_CNT];
35	int dwrr_node_pos[NIX_TXSCH_LVL_CNT];
36	u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
37	u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
38	bool schq_index_used[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
39};
40
41struct otx2_qos {
42	DECLARE_HASHTABLE(qos_hlist, order_base_2(OTX2_QOS_MAX_LEAF_NODES));
43	struct mutex qos_lock; /* child list lock */
44	u16 qid_to_sqmap[OTX2_QOS_MAX_LEAF_NODES];
45	struct list_head qos_tree;
46	DECLARE_BITMAP(qos_sq_bmap, OTX2_QOS_MAX_LEAF_NODES);
47	u16 maj_id;
48	u16 defcls;
49	u8  link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
50};
51
52struct otx2_qos_node {
53	struct list_head list; /* list management */
54	struct list_head child_list;
55	struct list_head child_schq_list;
56	struct hlist_node hlist;
57	DECLARE_BITMAP(prio_bmap, OTX2_QOS_MAX_PRIO + 1);
58	struct otx2_qos_node *parent;	/* parent qos node */
59	u64 rate; /* htb params */
60	u64 ceil;
61	u32 classid;
62	u32 prio;
63	u32 quantum;
64	/* hw txschq */
65	u16 schq;
66	u16 qid;
67	u16 prio_anchor;
68	u16 max_static_prio;
69	u16 child_dwrr_cnt;
70	u16 child_static_cnt;
71	u16 child_dwrr_prio;
72	u16 txschq_idx;			/* txschq allocation index */
73	u8 level;
74	bool is_static;
75};
76
77
78#endif
79