1/* SPDX-License-Identifier: GPL-2.0 */
2/* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2021 Marvell.
5 *
6 */
7
8#ifndef CN10K_H
9#define CN10K_H
10
11#include "otx2_common.h"
12
13static inline int mtu_to_dwrr_weight(struct otx2_nic *pfvf, int mtu)
14{
15	u32 weight;
16
17	/* On OTx2, since AF returns DWRR_MTU as '1', this logic
18	 * will work on those silicons as well.
19	 */
20	weight = mtu / pfvf->hw.dwrr_mtu;
21	if (mtu % pfvf->hw.dwrr_mtu)
22		weight += 1;
23
24	return weight;
25}
26
27int cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
28void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx);
29int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
30int cn10k_lmtst_init(struct otx2_nic *pfvf);
31int cn10k_free_all_ipolicers(struct otx2_nic *pfvf);
32int cn10k_alloc_matchall_ipolicer(struct otx2_nic *pfvf);
33int cn10k_free_matchall_ipolicer(struct otx2_nic *pfvf);
34int cn10k_set_matchall_ipolicer_rate(struct otx2_nic *pfvf,
35				     u32 burst, u64 rate);
36int cn10k_map_unmap_rq_policer(struct otx2_nic *pfvf, int rq_idx,
37			       u16 policer, bool map);
38int cn10k_alloc_leaf_profile(struct otx2_nic *pfvf, u16 *leaf);
39int cn10k_set_ipolicer_rate(struct otx2_nic *pfvf, u16 profile,
40			    u32 burst, u64 rate, bool pps);
41int cn10k_free_leaf_profile(struct otx2_nic *pfvf, u16 leaf);
42#endif /* CN10K_H */
43