1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver 4 * 5 * Copyright 2008 JMicron Technology Corporation 6 * https://www.jmicron.com/ 7 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org> 8 * 9 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org> 10 */ 11 12#ifndef __JME_H_INCLUDED__ 13#define __JME_H_INCLUDED__ 14#include <linux/interrupt.h> 15 16#define DRV_NAME "jme" 17#define DRV_VERSION "1.0.8" 18 19#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250 20#define PCI_DEVICE_ID_JMICRON_JMC260 0x0260 21 22/* 23 * Message related definitions 24 */ 25#define JME_DEF_MSG_ENABLE \ 26 (NETIF_MSG_PROBE | \ 27 NETIF_MSG_LINK | \ 28 NETIF_MSG_RX_ERR | \ 29 NETIF_MSG_TX_ERR | \ 30 NETIF_MSG_HW) 31 32#ifdef TX_DEBUG 33#define tx_dbg(priv, fmt, args...) \ 34 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args) 35#else 36#define tx_dbg(priv, fmt, args...) \ 37do { \ 38 if (0) \ 39 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \ 40} while (0) 41#endif 42 43/* 44 * Extra PCI Configuration space interface 45 */ 46#define PCI_DCSR_MRRS 0x59 47#define PCI_DCSR_MRRS_MASK 0x70 48 49enum pci_dcsr_mrrs_vals { 50 MRRS_128B = 0x00, 51 MRRS_256B = 0x10, 52 MRRS_512B = 0x20, 53 MRRS_1024B = 0x30, 54 MRRS_2048B = 0x40, 55 MRRS_4096B = 0x50, 56}; 57 58#define PCI_SPI 0xB0 59 60enum pci_spi_bits { 61 SPI_EN = 0x10, 62 SPI_MISO = 0x08, 63 SPI_MOSI = 0x04, 64 SPI_SCLK = 0x02, 65 SPI_CS = 0x01, 66}; 67 68struct jme_spi_op { 69 void __user *uwbuf; 70 void __user *urbuf; 71 __u8 wn; /* Number of write actions */ 72 __u8 rn; /* Number of read actions */ 73 __u8 bitn; /* Number of bits per action */ 74 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/ 75 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */ 76 77 /* Internal use only */ 78 u8 *kwbuf; 79 u8 *krbuf; 80 u8 sr; 81 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */ 82}; 83 84enum jme_spi_op_bits { 85 SPI_MODE_CPHA = 0x01, 86 SPI_MODE_CPOL = 0x02, 87 SPI_MODE_DUP = 0x80, 88}; 89 90#define HALF_US 500 /* 500 ns */ 91 92#define PCI_PRIV_PE1 0xE4 93 94enum pci_priv_pe1_bit_masks { 95 PE1_ASPMSUPRT = 0x00000003, /* 96 * RW: 97 * Aspm_support[1:0] 98 * (R/W Port of 5C[11:10]) 99 */ 100 PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */ 101 PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */ 102 PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */ 103 PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */ 104 PE1_GPREG0 = 0x0000FF00, /* 105 * SRW: 106 * Cfg_gp_reg0 107 * [7:6] phy_giga BG control 108 * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#) 109 * [4:0] Reserved 110 */ 111 PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */ 112 PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */ 113 PE1_REVID = 0xFF000000, /* RO: Rev ID */ 114}; 115 116enum pci_priv_pe1_values { 117 PE1_GPREG0_ENBG = 0x00000000, /* en BG */ 118 PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */ 119 PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */ 120 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */ 121}; 122 123/* 124 * Dynamic(adaptive)/Static PCC values 125 */ 126enum dynamic_pcc_values { 127 PCC_OFF = 0, 128 PCC_P1 = 1, 129 PCC_P2 = 2, 130 PCC_P3 = 3, 131 132 PCC_OFF_TO = 0, 133 PCC_P1_TO = 1, 134 PCC_P2_TO = 64, 135 PCC_P3_TO = 128, 136 137 PCC_OFF_CNT = 0, 138 PCC_P1_CNT = 1, 139 PCC_P2_CNT = 16, 140 PCC_P3_CNT = 32, 141}; 142struct dynpcc_info { 143 unsigned long last_bytes; 144 unsigned long last_pkts; 145 unsigned long intr_cnt; 146 unsigned char cur; 147 unsigned char attempt; 148 unsigned char cnt; 149}; 150#define PCC_INTERVAL_US 100000 151#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US)) 152#define PCC_P3_THRESHOLD (2 * 1024 * 1024) 153#define PCC_P2_THRESHOLD 800 154#define PCC_INTR_THRESHOLD 800 155#define PCC_TX_TO 1000 156#define PCC_TX_CNT 8 157 158/* 159 * TX/RX Descriptors 160 * 161 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024 162 */ 163#define RING_DESC_ALIGN 16 /* Descriptor alignment */ 164#define TX_DESC_SIZE 16 165#define TX_RING_NR 8 166#define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN) 167 168struct txdesc { 169 union { 170 __u8 all[16]; 171 __le32 dw[4]; 172 struct { 173 /* DW0 */ 174 __le16 vlan; 175 __u8 rsv1; 176 __u8 flags; 177 178 /* DW1 */ 179 __le16 datalen; 180 __le16 mss; 181 182 /* DW2 */ 183 __le16 pktsize; 184 __le16 rsv2; 185 186 /* DW3 */ 187 __le32 bufaddr; 188 } desc1; 189 struct { 190 /* DW0 */ 191 __le16 rsv1; 192 __u8 rsv2; 193 __u8 flags; 194 195 /* DW1 */ 196 __le16 datalen; 197 __le16 rsv3; 198 199 /* DW2 */ 200 __le32 bufaddrh; 201 202 /* DW3 */ 203 __le32 bufaddrl; 204 } desc2; 205 struct { 206 /* DW0 */ 207 __u8 ehdrsz; 208 __u8 rsv1; 209 __u8 rsv2; 210 __u8 flags; 211 212 /* DW1 */ 213 __le16 trycnt; 214 __le16 segcnt; 215 216 /* DW2 */ 217 __le16 pktsz; 218 __le16 rsv3; 219 220 /* DW3 */ 221 __le32 bufaddrl; 222 } descwb; 223 }; 224}; 225 226enum jme_txdesc_flags_bits { 227 TXFLAG_OWN = 0x80, 228 TXFLAG_INT = 0x40, 229 TXFLAG_64BIT = 0x20, 230 TXFLAG_TCPCS = 0x10, 231 TXFLAG_UDPCS = 0x08, 232 TXFLAG_IPCS = 0x04, 233 TXFLAG_LSEN = 0x02, 234 TXFLAG_TAGON = 0x01, 235}; 236 237#define TXDESC_MSS_SHIFT 2 238enum jme_txwbdesc_flags_bits { 239 TXWBFLAG_OWN = 0x80, 240 TXWBFLAG_INT = 0x40, 241 TXWBFLAG_TMOUT = 0x20, 242 TXWBFLAG_TRYOUT = 0x10, 243 TXWBFLAG_COL = 0x08, 244 245 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT | 246 TXWBFLAG_TRYOUT | 247 TXWBFLAG_COL, 248}; 249 250#define RX_DESC_SIZE 16 251#define RX_RING_NR 4 252#define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN) 253#define RX_BUF_DMA_ALIGN 8 254#define RX_PREPAD_SIZE 10 255#define ETH_CRC_LEN 2 256#define RX_VLANHDR_LEN 2 257#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \ 258 ETH_HLEN + \ 259 ETH_CRC_LEN + \ 260 RX_VLANHDR_LEN + \ 261 RX_BUF_DMA_ALIGN) 262 263struct rxdesc { 264 union { 265 __u8 all[16]; 266 __le32 dw[4]; 267 struct { 268 /* DW0 */ 269 __le16 rsv2; 270 __u8 rsv1; 271 __u8 flags; 272 273 /* DW1 */ 274 __le16 datalen; 275 __le16 wbcpl; 276 277 /* DW2 */ 278 __le32 bufaddrh; 279 280 /* DW3 */ 281 __le32 bufaddrl; 282 } desc1; 283 struct { 284 /* DW0 */ 285 __le16 vlan; 286 __le16 flags; 287 288 /* DW1 */ 289 __le16 framesize; 290 __u8 errstat; 291 __u8 desccnt; 292 293 /* DW2 */ 294 __le32 rsshash; 295 296 /* DW3 */ 297 __u8 hashfun; 298 __u8 hashtype; 299 __le16 resrv; 300 } descwb; 301 }; 302}; 303 304enum jme_rxdesc_flags_bits { 305 RXFLAG_OWN = 0x80, 306 RXFLAG_INT = 0x40, 307 RXFLAG_64BIT = 0x20, 308}; 309 310enum jme_rxwbdesc_flags_bits { 311 RXWBFLAG_OWN = 0x8000, 312 RXWBFLAG_INT = 0x4000, 313 RXWBFLAG_MF = 0x2000, 314 RXWBFLAG_64BIT = 0x2000, 315 RXWBFLAG_TCPON = 0x1000, 316 RXWBFLAG_UDPON = 0x0800, 317 RXWBFLAG_IPCS = 0x0400, 318 RXWBFLAG_TCPCS = 0x0200, 319 RXWBFLAG_UDPCS = 0x0100, 320 RXWBFLAG_TAGON = 0x0080, 321 RXWBFLAG_IPV4 = 0x0040, 322 RXWBFLAG_IPV6 = 0x0020, 323 RXWBFLAG_PAUSE = 0x0010, 324 RXWBFLAG_MAGIC = 0x0008, 325 RXWBFLAG_WAKEUP = 0x0004, 326 RXWBFLAG_DEST = 0x0003, 327 RXWBFLAG_DEST_UNI = 0x0001, 328 RXWBFLAG_DEST_MUL = 0x0002, 329 RXWBFLAG_DEST_BRO = 0x0003, 330}; 331 332enum jme_rxwbdesc_desccnt_mask { 333 RXWBDCNT_WBCPL = 0x80, 334 RXWBDCNT_DCNT = 0x7F, 335}; 336 337enum jme_rxwbdesc_errstat_bits { 338 RXWBERR_LIMIT = 0x80, 339 RXWBERR_MIIER = 0x40, 340 RXWBERR_NIBON = 0x20, 341 RXWBERR_COLON = 0x10, 342 RXWBERR_ABORT = 0x08, 343 RXWBERR_SHORT = 0x04, 344 RXWBERR_OVERUN = 0x02, 345 RXWBERR_CRCERR = 0x01, 346 RXWBERR_ALLERR = 0xFF, 347}; 348 349/* 350 * Buffer information corresponding to ring descriptors. 351 */ 352struct jme_buffer_info { 353 struct sk_buff *skb; 354 dma_addr_t mapping; 355 int len; 356 int nr_desc; 357 unsigned long start_xmit; 358}; 359 360/* 361 * The structure holding buffer information and ring descriptors all together. 362 */ 363struct jme_ring { 364 void *alloc; /* pointer to allocated memory */ 365 void *desc; /* pointer to ring memory */ 366 dma_addr_t dmaalloc; /* phys address of ring alloc */ 367 dma_addr_t dma; /* phys address for ring dma */ 368 369 /* Buffer information corresponding to each descriptor */ 370 struct jme_buffer_info *bufinf; 371 372 int next_to_use; 373 atomic_t next_to_clean; 374 atomic_t nr_free; 375}; 376 377#define NET_STAT(priv) (priv->dev->stats) 378#define NETDEV_GET_STATS(netdev, fun_ptr) 379#define DECLARE_NET_DEVICE_STATS 380 381#define DECLARE_NAPI_STRUCT struct napi_struct napi; 382#define JME_NAPI_HOLDER(holder) struct napi_struct *holder 383#define JME_NAPI_WEIGHT(w) int w 384#define JME_NAPI_WEIGHT_VAL(w) w 385#define JME_NAPI_WEIGHT_SET(w, r) 386#define JME_RX_COMPLETE(dev, napis) napi_complete(napis) 387#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi); 388#define JME_NAPI_DISABLE(priv) \ 389 if (!napi_disable_pending(&priv->napi)) \ 390 napi_disable(&priv->napi); 391#define JME_RX_SCHEDULE_PREP(priv) \ 392 napi_schedule_prep(&priv->napi) 393#define JME_RX_SCHEDULE(priv) \ 394 __napi_schedule(&priv->napi); 395 396/* 397 * Jmac Adapter Private data 398 */ 399struct jme_adapter { 400 struct pci_dev *pdev; 401 struct net_device *dev; 402 void __iomem *regs; 403 struct mii_if_info mii_if; 404 struct jme_ring rxring[RX_RING_NR]; 405 struct jme_ring txring[TX_RING_NR]; 406 spinlock_t phy_lock; 407 spinlock_t macaddr_lock; 408 spinlock_t rxmcs_lock; 409 struct tasklet_struct rxempty_task; 410 struct tasklet_struct rxclean_task; 411 struct tasklet_struct txclean_task; 412 struct work_struct linkch_task; 413 struct tasklet_struct pcc_task; 414 unsigned long flags; 415 u32 reg_txcs; 416 u32 reg_txpfc; 417 u32 reg_rxcs; 418 u32 reg_rxmcs; 419 u32 reg_ghc; 420 u32 reg_pmcs; 421 u32 reg_gpreg1; 422 u32 phylink; 423 u32 tx_ring_size; 424 u32 tx_ring_mask; 425 u32 tx_wake_threshold; 426 u32 rx_ring_size; 427 u32 rx_ring_mask; 428 u8 mrrs; 429 unsigned int fpgaver; 430 u8 chiprev; 431 u8 chip_main_rev; 432 u8 chip_sub_rev; 433 u8 pcirev; 434 u32 msg_enable; 435 struct ethtool_link_ksettings old_cmd; 436 unsigned int old_mtu; 437 struct dynpcc_info dpi; 438 atomic_t intr_sem; 439 atomic_t link_changing; 440 atomic_t tx_cleaning; 441 atomic_t rx_cleaning; 442 atomic_t rx_empty; 443 int (*jme_rx)(struct sk_buff *skb); 444 DECLARE_NAPI_STRUCT 445 DECLARE_NET_DEVICE_STATS 446}; 447 448enum jme_flags_bits { 449 JME_FLAG_MSI = 1, 450 JME_FLAG_SSET = 2, 451 JME_FLAG_POLL = 5, 452 JME_FLAG_SHUTDOWN = 6, 453}; 454 455#define TX_TIMEOUT (5 * HZ) 456#define JME_REG_LEN 0x500 457#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216 458 459static inline struct jme_adapter* 460jme_napi_priv(struct napi_struct *napi) 461{ 462 struct jme_adapter *jme; 463 jme = container_of(napi, struct jme_adapter, napi); 464 return jme; 465} 466 467/* 468 * MMaped I/O Resters 469 */ 470enum jme_iomap_offsets { 471 JME_MAC = 0x0000, 472 JME_PHY = 0x0400, 473 JME_MISC = 0x0800, 474 JME_RSS = 0x0C00, 475}; 476 477enum jme_iomap_lens { 478 JME_MAC_LEN = 0x80, 479 JME_PHY_LEN = 0x58, 480 JME_MISC_LEN = 0x98, 481 JME_RSS_LEN = 0xFF, 482}; 483 484enum jme_iomap_regs { 485 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */ 486 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */ 487 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */ 488 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */ 489 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */ 490 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */ 491 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */ 492 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */ 493 494 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */ 495 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */ 496 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */ 497 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */ 498 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */ 499 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */ 500 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */ 501 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */ 502 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */ 503 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */ 504 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */ 505 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */ 506 507 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */ 508 JME_GHC = JME_MAC | 0x54, /* Global Host Control */ 509 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */ 510 511 512 JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */ 513 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */ 514 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */ 515 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */ 516 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */ 517 518 519 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */ 520 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */ 521 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */ 522 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */ 523 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */ 524 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */ 525 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */ 526 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */ 527 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */ 528 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */ 529 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */ 530 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */ 531 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */ 532 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */ 533 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */ 534 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */ 535}; 536 537/* 538 * TX Control/Status Bits 539 */ 540enum jme_txcs_bits { 541 TXCS_QUEUE7S = 0x00008000, 542 TXCS_QUEUE6S = 0x00004000, 543 TXCS_QUEUE5S = 0x00002000, 544 TXCS_QUEUE4S = 0x00001000, 545 TXCS_QUEUE3S = 0x00000800, 546 TXCS_QUEUE2S = 0x00000400, 547 TXCS_QUEUE1S = 0x00000200, 548 TXCS_QUEUE0S = 0x00000100, 549 TXCS_FIFOTH = 0x000000C0, 550 TXCS_DMASIZE = 0x00000030, 551 TXCS_BURST = 0x00000004, 552 TXCS_ENABLE = 0x00000001, 553}; 554 555enum jme_txcs_value { 556 TXCS_FIFOTH_16QW = 0x000000C0, 557 TXCS_FIFOTH_12QW = 0x00000080, 558 TXCS_FIFOTH_8QW = 0x00000040, 559 TXCS_FIFOTH_4QW = 0x00000000, 560 561 TXCS_DMASIZE_64B = 0x00000000, 562 TXCS_DMASIZE_128B = 0x00000010, 563 TXCS_DMASIZE_256B = 0x00000020, 564 TXCS_DMASIZE_512B = 0x00000030, 565 566 TXCS_SELECT_QUEUE0 = 0x00000000, 567 TXCS_SELECT_QUEUE1 = 0x00010000, 568 TXCS_SELECT_QUEUE2 = 0x00020000, 569 TXCS_SELECT_QUEUE3 = 0x00030000, 570 TXCS_SELECT_QUEUE4 = 0x00040000, 571 TXCS_SELECT_QUEUE5 = 0x00050000, 572 TXCS_SELECT_QUEUE6 = 0x00060000, 573 TXCS_SELECT_QUEUE7 = 0x00070000, 574 575 TXCS_DEFAULT = TXCS_FIFOTH_4QW | 576 TXCS_BURST, 577}; 578 579#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */ 580 581/* 582 * TX MAC Control/Status Bits 583 */ 584enum jme_txmcs_bit_masks { 585 TXMCS_IFG2 = 0xC0000000, 586 TXMCS_IFG1 = 0x30000000, 587 TXMCS_TTHOLD = 0x00000300, 588 TXMCS_FBURST = 0x00000080, 589 TXMCS_CARRIEREXT = 0x00000040, 590 TXMCS_DEFER = 0x00000020, 591 TXMCS_BACKOFF = 0x00000010, 592 TXMCS_CARRIERSENSE = 0x00000008, 593 TXMCS_COLLISION = 0x00000004, 594 TXMCS_CRC = 0x00000002, 595 TXMCS_PADDING = 0x00000001, 596}; 597 598enum jme_txmcs_values { 599 TXMCS_IFG2_6_4 = 0x00000000, 600 TXMCS_IFG2_8_5 = 0x40000000, 601 TXMCS_IFG2_10_6 = 0x80000000, 602 TXMCS_IFG2_12_7 = 0xC0000000, 603 604 TXMCS_IFG1_8_4 = 0x00000000, 605 TXMCS_IFG1_12_6 = 0x10000000, 606 TXMCS_IFG1_16_8 = 0x20000000, 607 TXMCS_IFG1_20_10 = 0x30000000, 608 609 TXMCS_TTHOLD_1_8 = 0x00000000, 610 TXMCS_TTHOLD_1_4 = 0x00000100, 611 TXMCS_TTHOLD_1_2 = 0x00000200, 612 TXMCS_TTHOLD_FULL = 0x00000300, 613 614 TXMCS_DEFAULT = TXMCS_IFG2_8_5 | 615 TXMCS_IFG1_16_8 | 616 TXMCS_TTHOLD_FULL | 617 TXMCS_DEFER | 618 TXMCS_CRC | 619 TXMCS_PADDING, 620}; 621 622enum jme_txpfc_bits_masks { 623 TXPFC_VLAN_TAG = 0xFFFF0000, 624 TXPFC_VLAN_EN = 0x00008000, 625 TXPFC_PF_EN = 0x00000001, 626}; 627 628enum jme_txtrhd_bits_masks { 629 TXTRHD_TXPEN = 0x80000000, 630 TXTRHD_TXP = 0x7FFFFF00, 631 TXTRHD_TXREN = 0x00000080, 632 TXTRHD_TXRL = 0x0000007F, 633}; 634 635enum jme_txtrhd_shifts { 636 TXTRHD_TXP_SHIFT = 8, 637 TXTRHD_TXRL_SHIFT = 0, 638}; 639 640enum jme_txtrhd_values { 641 TXTRHD_FULLDUPLEX = 0x00000000, 642 TXTRHD_HALFDUPLEX = TXTRHD_TXPEN | 643 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) | 644 TXTRHD_TXREN | 645 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL), 646}; 647 648/* 649 * RX Control/Status Bits 650 */ 651enum jme_rxcs_bit_masks { 652 /* FIFO full threshold for transmitting Tx Pause Packet */ 653 RXCS_FIFOTHTP = 0x30000000, 654 /* FIFO threshold for processing next packet */ 655 RXCS_FIFOTHNP = 0x0C000000, 656 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */ 657 RXCS_QUEUESEL = 0x00030000, /* Queue selection */ 658 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */ 659 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */ 660 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */ 661 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */ 662 RXCS_SHORT = 0x00000010, /* Enable receive short packet */ 663 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */ 664 RXCS_QST = 0x00000004, /* Receive queue start */ 665 RXCS_SUSPEND = 0x00000002, 666 RXCS_ENABLE = 0x00000001, 667}; 668 669enum jme_rxcs_values { 670 RXCS_FIFOTHTP_16T = 0x00000000, 671 RXCS_FIFOTHTP_32T = 0x10000000, 672 RXCS_FIFOTHTP_64T = 0x20000000, 673 RXCS_FIFOTHTP_128T = 0x30000000, 674 675 RXCS_FIFOTHNP_16QW = 0x00000000, 676 RXCS_FIFOTHNP_32QW = 0x04000000, 677 RXCS_FIFOTHNP_64QW = 0x08000000, 678 RXCS_FIFOTHNP_128QW = 0x0C000000, 679 680 RXCS_DMAREQSZ_16B = 0x00000000, 681 RXCS_DMAREQSZ_32B = 0x01000000, 682 RXCS_DMAREQSZ_64B = 0x02000000, 683 RXCS_DMAREQSZ_128B = 0x03000000, 684 685 RXCS_QUEUESEL_Q0 = 0x00000000, 686 RXCS_QUEUESEL_Q1 = 0x00010000, 687 RXCS_QUEUESEL_Q2 = 0x00020000, 688 RXCS_QUEUESEL_Q3 = 0x00030000, 689 690 RXCS_RETRYGAP_256ns = 0x00000000, 691 RXCS_RETRYGAP_512ns = 0x00001000, 692 RXCS_RETRYGAP_1024ns = 0x00002000, 693 RXCS_RETRYGAP_2048ns = 0x00003000, 694 RXCS_RETRYGAP_4096ns = 0x00004000, 695 RXCS_RETRYGAP_8192ns = 0x00005000, 696 RXCS_RETRYGAP_16384ns = 0x00006000, 697 RXCS_RETRYGAP_32768ns = 0x00007000, 698 699 RXCS_RETRYCNT_0 = 0x00000000, 700 RXCS_RETRYCNT_4 = 0x00000100, 701 RXCS_RETRYCNT_8 = 0x00000200, 702 RXCS_RETRYCNT_12 = 0x00000300, 703 RXCS_RETRYCNT_16 = 0x00000400, 704 RXCS_RETRYCNT_20 = 0x00000500, 705 RXCS_RETRYCNT_24 = 0x00000600, 706 RXCS_RETRYCNT_28 = 0x00000700, 707 RXCS_RETRYCNT_32 = 0x00000800, 708 RXCS_RETRYCNT_36 = 0x00000900, 709 RXCS_RETRYCNT_40 = 0x00000A00, 710 RXCS_RETRYCNT_44 = 0x00000B00, 711 RXCS_RETRYCNT_48 = 0x00000C00, 712 RXCS_RETRYCNT_52 = 0x00000D00, 713 RXCS_RETRYCNT_56 = 0x00000E00, 714 RXCS_RETRYCNT_60 = 0x00000F00, 715 716 RXCS_DEFAULT = RXCS_FIFOTHTP_128T | 717 RXCS_FIFOTHNP_16QW | 718 RXCS_DMAREQSZ_128B | 719 RXCS_RETRYGAP_256ns | 720 RXCS_RETRYCNT_32, 721}; 722 723#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */ 724 725/* 726 * RX MAC Control/Status Bits 727 */ 728enum jme_rxmcs_bits { 729 RXMCS_ALLFRAME = 0x00000800, 730 RXMCS_BRDFRAME = 0x00000400, 731 RXMCS_MULFRAME = 0x00000200, 732 RXMCS_UNIFRAME = 0x00000100, 733 RXMCS_ALLMULFRAME = 0x00000080, 734 RXMCS_MULFILTERED = 0x00000040, 735 RXMCS_RXCOLLDEC = 0x00000020, 736 RXMCS_FLOWCTRL = 0x00000008, 737 RXMCS_VTAGRM = 0x00000004, 738 RXMCS_PREPAD = 0x00000002, 739 RXMCS_CHECKSUM = 0x00000001, 740 741 RXMCS_DEFAULT = RXMCS_VTAGRM | 742 RXMCS_PREPAD | 743 RXMCS_FLOWCTRL | 744 RXMCS_CHECKSUM, 745}; 746 747/* Extern PHY common register 2 */ 748 749#define PHY_GAD_TEST_MODE_1 0x00002000 750#define PHY_GAD_TEST_MODE_MSK 0x0000E000 751#define JM_PHY_SPEC_REG_READ 0x00004000 752#define JM_PHY_SPEC_REG_WRITE 0x00008000 753#define PHY_CALIBRATION_DELAY 20 754#define JM_PHY_SPEC_ADDR_REG 0x1E 755#define JM_PHY_SPEC_DATA_REG 0x1F 756 757#define JM_PHY_EXT_COMM_0_REG 0x30 758#define JM_PHY_EXT_COMM_1_REG 0x31 759#define JM_PHY_EXT_COMM_2_REG 0x32 760#define JM_PHY_EXT_COMM_2_CALI_ENABLE 0x01 761#define JM_PHY_EXT_COMM_2_CALI_MODE_0 0x02 762#define JM_PHY_EXT_COMM_2_CALI_LATCH 0x10 763#define PCI_PRIV_SHARE_NICCTRL 0xF5 764#define JME_FLAG_PHYEA_ENABLE 0x2 765 766/* 767 * Wakeup Frame setup interface registers 768 */ 769#define WAKEUP_FRAME_NR 8 770#define WAKEUP_FRAME_MASK_DWNR 4 771 772enum jme_wfoi_bit_masks { 773 WFOI_MASK_SEL = 0x00000070, 774 WFOI_CRC_SEL = 0x00000008, 775 WFOI_FRAME_SEL = 0x00000007, 776}; 777 778enum jme_wfoi_shifts { 779 WFOI_MASK_SHIFT = 4, 780}; 781 782/* 783 * SMI Related definitions 784 */ 785enum jme_smi_bit_mask { 786 SMI_DATA_MASK = 0xFFFF0000, 787 SMI_REG_ADDR_MASK = 0x0000F800, 788 SMI_PHY_ADDR_MASK = 0x000007C0, 789 SMI_OP_WRITE = 0x00000020, 790 /* Set to 1, after req done it'll be cleared to 0 */ 791 SMI_OP_REQ = 0x00000010, 792 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */ 793 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */ 794 SMI_OP_MDC = 0x00000002, /* Software CLK Control */ 795 SMI_OP_MDEN = 0x00000001, /* Software access Enable */ 796}; 797 798enum jme_smi_bit_shift { 799 SMI_DATA_SHIFT = 16, 800 SMI_REG_ADDR_SHIFT = 11, 801 SMI_PHY_ADDR_SHIFT = 6, 802}; 803 804static inline u32 smi_reg_addr(int x) 805{ 806 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK; 807} 808 809static inline u32 smi_phy_addr(int x) 810{ 811 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK; 812} 813 814#define JME_PHY_TIMEOUT 100 /* 100 msec */ 815#define JME_PHY_REG_NR 32 816 817/* 818 * Global Host Control 819 */ 820enum jme_ghc_bit_mask { 821 GHC_SWRST = 0x40000000, 822 GHC_TO_CLK_SRC = 0x00C00000, 823 GHC_TXMAC_CLK_SRC = 0x00300000, 824 GHC_DPX = 0x00000040, 825 GHC_SPEED = 0x00000030, 826 GHC_LINK_POLL = 0x00000001, 827}; 828 829enum jme_ghc_speed_val { 830 GHC_SPEED_10M = 0x00000010, 831 GHC_SPEED_100M = 0x00000020, 832 GHC_SPEED_1000M = 0x00000030, 833}; 834 835enum jme_ghc_to_clk { 836 GHC_TO_CLK_OFF = 0x00000000, 837 GHC_TO_CLK_GPHY = 0x00400000, 838 GHC_TO_CLK_PCIE = 0x00800000, 839 GHC_TO_CLK_INVALID = 0x00C00000, 840}; 841 842enum jme_ghc_txmac_clk { 843 GHC_TXMAC_CLK_OFF = 0x00000000, 844 GHC_TXMAC_CLK_GPHY = 0x00100000, 845 GHC_TXMAC_CLK_PCIE = 0x00200000, 846 GHC_TXMAC_CLK_INVALID = 0x00300000, 847}; 848 849/* 850 * Power management control and status register 851 */ 852enum jme_pmcs_bit_masks { 853 PMCS_STMASK = 0xFFFF0000, 854 PMCS_WF7DET = 0x80000000, 855 PMCS_WF6DET = 0x40000000, 856 PMCS_WF5DET = 0x20000000, 857 PMCS_WF4DET = 0x10000000, 858 PMCS_WF3DET = 0x08000000, 859 PMCS_WF2DET = 0x04000000, 860 PMCS_WF1DET = 0x02000000, 861 PMCS_WF0DET = 0x01000000, 862 PMCS_LFDET = 0x00040000, 863 PMCS_LRDET = 0x00020000, 864 PMCS_MFDET = 0x00010000, 865 PMCS_ENMASK = 0x0000FFFF, 866 PMCS_WF7EN = 0x00008000, 867 PMCS_WF6EN = 0x00004000, 868 PMCS_WF5EN = 0x00002000, 869 PMCS_WF4EN = 0x00001000, 870 PMCS_WF3EN = 0x00000800, 871 PMCS_WF2EN = 0x00000400, 872 PMCS_WF1EN = 0x00000200, 873 PMCS_WF0EN = 0x00000100, 874 PMCS_LFEN = 0x00000004, 875 PMCS_LREN = 0x00000002, 876 PMCS_MFEN = 0x00000001, 877}; 878 879/* 880 * New PHY Power Control Register 881 */ 882enum jme_phy_pwr_bit_masks { 883 PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */ 884 PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */ 885 PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */ 886 PHY_PWR_CLKSEL = 0x08000000, /* 887 * XTL_OUT Clock select 888 * (an internal free-running clock) 889 * 0: xtl_out = phy_giga.A_XTL25_O 890 * 1: xtl_out = phy_giga.PD_OSC 891 */ 892}; 893 894/* 895 * Giga PHY Status Registers 896 */ 897enum jme_phy_link_bit_mask { 898 PHY_LINK_SPEED_MASK = 0x0000C000, 899 PHY_LINK_DUPLEX = 0x00002000, 900 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800, 901 PHY_LINK_UP = 0x00000400, 902 PHY_LINK_AUTONEG_COMPLETE = 0x00000200, 903 PHY_LINK_MDI_STAT = 0x00000040, 904}; 905 906enum jme_phy_link_speed_val { 907 PHY_LINK_SPEED_10M = 0x00000000, 908 PHY_LINK_SPEED_100M = 0x00004000, 909 PHY_LINK_SPEED_1000M = 0x00008000, 910}; 911 912#define JME_SPDRSV_TIMEOUT 500 /* 500 us */ 913 914/* 915 * SMB Control and Status 916 */ 917enum jme_smbcsr_bit_mask { 918 SMBCSR_CNACK = 0x00020000, 919 SMBCSR_RELOAD = 0x00010000, 920 SMBCSR_EEPROMD = 0x00000020, 921 SMBCSR_INITDONE = 0x00000010, 922 SMBCSR_BUSY = 0x0000000F, 923}; 924 925enum jme_smbintf_bit_mask { 926 SMBINTF_HWDATR = 0xFF000000, 927 SMBINTF_HWDATW = 0x00FF0000, 928 SMBINTF_HWADDR = 0x0000FF00, 929 SMBINTF_HWRWN = 0x00000020, 930 SMBINTF_HWCMD = 0x00000010, 931 SMBINTF_FASTM = 0x00000008, 932 SMBINTF_GPIOSCL = 0x00000004, 933 SMBINTF_GPIOSDA = 0x00000002, 934 SMBINTF_GPIOEN = 0x00000001, 935}; 936 937enum jme_smbintf_vals { 938 SMBINTF_HWRWN_READ = 0x00000020, 939 SMBINTF_HWRWN_WRITE = 0x00000000, 940}; 941 942enum jme_smbintf_shifts { 943 SMBINTF_HWDATR_SHIFT = 24, 944 SMBINTF_HWDATW_SHIFT = 16, 945 SMBINTF_HWADDR_SHIFT = 8, 946}; 947 948#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */ 949#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */ 950#define JME_SMB_LEN 256 951#define JME_EEPROM_MAGIC 0x250 952 953/* 954 * Timer Control/Status Register 955 */ 956enum jme_tmcsr_bit_masks { 957 TMCSR_SWIT = 0x80000000, 958 TMCSR_EN = 0x01000000, 959 TMCSR_CNT = 0x00FFFFFF, 960}; 961 962/* 963 * General Purpose REG-0 964 */ 965enum jme_gpreg0_masks { 966 GPREG0_DISSH = 0xFF000000, 967 GPREG0_PCIRLMT = 0x00300000, 968 GPREG0_PCCNOMUTCLR = 0x00040000, 969 GPREG0_LNKINTPOLL = 0x00001000, 970 GPREG0_PCCTMR = 0x00000300, 971 GPREG0_PHYADDR = 0x0000001F, 972}; 973 974enum jme_gpreg0_vals { 975 GPREG0_DISSH_DW7 = 0x80000000, 976 GPREG0_DISSH_DW6 = 0x40000000, 977 GPREG0_DISSH_DW5 = 0x20000000, 978 GPREG0_DISSH_DW4 = 0x10000000, 979 GPREG0_DISSH_DW3 = 0x08000000, 980 GPREG0_DISSH_DW2 = 0x04000000, 981 GPREG0_DISSH_DW1 = 0x02000000, 982 GPREG0_DISSH_DW0 = 0x01000000, 983 GPREG0_DISSH_ALL = 0xFF000000, 984 985 GPREG0_PCIRLMT_8 = 0x00000000, 986 GPREG0_PCIRLMT_6 = 0x00100000, 987 GPREG0_PCIRLMT_5 = 0x00200000, 988 GPREG0_PCIRLMT_4 = 0x00300000, 989 990 GPREG0_PCCTMR_16ns = 0x00000000, 991 GPREG0_PCCTMR_256ns = 0x00000100, 992 GPREG0_PCCTMR_1us = 0x00000200, 993 GPREG0_PCCTMR_1ms = 0x00000300, 994 995 GPREG0_PHYADDR_1 = 0x00000001, 996 997 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 | 998 GPREG0_PCCTMR_1us | 999 GPREG0_PHYADDR_1, 1000}; 1001 1002/* 1003 * General Purpose REG-1 1004 */ 1005enum jme_gpreg1_bit_masks { 1006 GPREG1_RXCLKOFF = 0x04000000, 1007 GPREG1_PCREQN = 0x00020000, 1008 GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */ 1009 GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */ 1010 GPREG1_INTRDELAYUNIT = 0x00000018, 1011 GPREG1_INTRDELAYENABLE = 0x00000007, 1012}; 1013 1014enum jme_gpreg1_vals { 1015 GPREG1_INTDLYUNIT_16NS = 0x00000000, 1016 GPREG1_INTDLYUNIT_256NS = 0x00000008, 1017 GPREG1_INTDLYUNIT_1US = 0x00000010, 1018 GPREG1_INTDLYUNIT_16US = 0x00000018, 1019 1020 GPREG1_INTDLYEN_1U = 0x00000001, 1021 GPREG1_INTDLYEN_2U = 0x00000002, 1022 GPREG1_INTDLYEN_3U = 0x00000003, 1023 GPREG1_INTDLYEN_4U = 0x00000004, 1024 GPREG1_INTDLYEN_5U = 0x00000005, 1025 GPREG1_INTDLYEN_6U = 0x00000006, 1026 GPREG1_INTDLYEN_7U = 0x00000007, 1027 1028 GPREG1_DEFAULT = GPREG1_PCREQN, 1029}; 1030 1031/* 1032 * Interrupt Status Bits 1033 */ 1034enum jme_interrupt_bits { 1035 INTR_SWINTR = 0x80000000, 1036 INTR_TMINTR = 0x40000000, 1037 INTR_LINKCH = 0x20000000, 1038 INTR_PAUSERCV = 0x10000000, 1039 INTR_MAGICRCV = 0x08000000, 1040 INTR_WAKERCV = 0x04000000, 1041 INTR_PCCRX0TO = 0x02000000, 1042 INTR_PCCRX1TO = 0x01000000, 1043 INTR_PCCRX2TO = 0x00800000, 1044 INTR_PCCRX3TO = 0x00400000, 1045 INTR_PCCTXTO = 0x00200000, 1046 INTR_PCCRX0 = 0x00100000, 1047 INTR_PCCRX1 = 0x00080000, 1048 INTR_PCCRX2 = 0x00040000, 1049 INTR_PCCRX3 = 0x00020000, 1050 INTR_PCCTX = 0x00010000, 1051 INTR_RX3EMP = 0x00008000, 1052 INTR_RX2EMP = 0x00004000, 1053 INTR_RX1EMP = 0x00002000, 1054 INTR_RX0EMP = 0x00001000, 1055 INTR_RX3 = 0x00000800, 1056 INTR_RX2 = 0x00000400, 1057 INTR_RX1 = 0x00000200, 1058 INTR_RX0 = 0x00000100, 1059 INTR_TX7 = 0x00000080, 1060 INTR_TX6 = 0x00000040, 1061 INTR_TX5 = 0x00000020, 1062 INTR_TX4 = 0x00000010, 1063 INTR_TX3 = 0x00000008, 1064 INTR_TX2 = 0x00000004, 1065 INTR_TX1 = 0x00000002, 1066 INTR_TX0 = 0x00000001, 1067}; 1068 1069static const u32 INTR_ENABLE = INTR_SWINTR | 1070 INTR_TMINTR | 1071 INTR_LINKCH | 1072 INTR_PCCRX0TO | 1073 INTR_PCCRX0 | 1074 INTR_PCCTXTO | 1075 INTR_PCCTX | 1076 INTR_RX0EMP; 1077 1078/* 1079 * PCC Control Registers 1080 */ 1081enum jme_pccrx_masks { 1082 PCCRXTO_MASK = 0xFFFF0000, 1083 PCCRX_MASK = 0x0000FF00, 1084}; 1085 1086enum jme_pcctx_masks { 1087 PCCTXTO_MASK = 0xFFFF0000, 1088 PCCTX_MASK = 0x0000FF00, 1089 PCCTX_QS_MASK = 0x000000FF, 1090}; 1091 1092enum jme_pccrx_shifts { 1093 PCCRXTO_SHIFT = 16, 1094 PCCRX_SHIFT = 8, 1095}; 1096 1097enum jme_pcctx_shifts { 1098 PCCTXTO_SHIFT = 16, 1099 PCCTX_SHIFT = 8, 1100}; 1101 1102enum jme_pcctx_bits { 1103 PCCTXQ0_EN = 0x00000001, 1104 PCCTXQ1_EN = 0x00000002, 1105 PCCTXQ2_EN = 0x00000004, 1106 PCCTXQ3_EN = 0x00000008, 1107 PCCTXQ4_EN = 0x00000010, 1108 PCCTXQ5_EN = 0x00000020, 1109 PCCTXQ6_EN = 0x00000040, 1110 PCCTXQ7_EN = 0x00000080, 1111}; 1112 1113/* 1114 * Chip Mode Register 1115 */ 1116enum jme_chipmode_bit_masks { 1117 CM_FPGAVER_MASK = 0xFFFF0000, 1118 CM_CHIPREV_MASK = 0x0000FF00, 1119 CM_CHIPMODE_MASK = 0x0000000F, 1120}; 1121 1122enum jme_chipmode_shifts { 1123 CM_FPGAVER_SHIFT = 16, 1124 CM_CHIPREV_SHIFT = 8, 1125}; 1126 1127/* 1128 * Aggressive Power Mode Control 1129 */ 1130enum jme_apmc_bits { 1131 JME_APMC_PCIE_SD_EN = 0x40000000, 1132 JME_APMC_PSEUDO_HP_EN = 0x20000000, 1133 JME_APMC_EPIEN = 0x04000000, 1134 JME_APMC_EPIEN_CTRL = 0x03000000, 1135}; 1136 1137enum jme_apmc_values { 1138 JME_APMC_EPIEN_CTRL_EN = 0x02000000, 1139 JME_APMC_EPIEN_CTRL_DIS = 0x01000000, 1140}; 1141 1142#define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000) 1143 1144#ifdef REG_DEBUG 1145static char *MAC_REG_NAME[] = { 1146 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC", 1147 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD", 1148 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC", 1149 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI", 1150 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI", 1151 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN", 1152 "JME_PMCS"}; 1153 1154static char *PE_REG_NAME[] = { 1155 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", 1156 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", 1157 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN", 1158 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN", 1159 "JME_SMBCSR", "JME_SMBINTF"}; 1160 1161static char *MISC_REG_NAME[] = { 1162 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1", 1163 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC", 1164 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3", 1165 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO", 1166 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", 1167 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", 1168 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", 1169 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC", 1170 "JME_PCCSRX0"}; 1171 1172static inline void reg_dbg(const struct jme_adapter *jme, 1173 const char *msg, u32 val, u32 reg) 1174{ 1175 const char *regname; 1176 switch (reg & 0xF00) { 1177 case 0x000: 1178 regname = MAC_REG_NAME[(reg & 0xFF) >> 2]; 1179 break; 1180 case 0x400: 1181 regname = PE_REG_NAME[(reg & 0xFF) >> 2]; 1182 break; 1183 case 0x800: 1184 regname = MISC_REG_NAME[(reg & 0xFF) >> 2]; 1185 break; 1186 default: 1187 regname = PE_REG_NAME[0]; 1188 } 1189 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name, 1190 msg, val, regname); 1191} 1192#else 1193static inline void reg_dbg(const struct jme_adapter *jme, 1194 const char *msg, u32 val, u32 reg) {} 1195#endif 1196 1197/* 1198 * Read/Write MMaped I/O Registers 1199 */ 1200static inline u32 jread32(struct jme_adapter *jme, u32 reg) 1201{ 1202 return readl(jme->regs + reg); 1203} 1204 1205static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val) 1206{ 1207 reg_dbg(jme, "REG WRITE", val, reg); 1208 writel(val, jme->regs + reg); 1209 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg); 1210} 1211 1212static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val) 1213{ 1214 /* 1215 * Read after write should cause flush 1216 */ 1217 reg_dbg(jme, "REG WRITE FLUSH", val, reg); 1218 writel(val, jme->regs + reg); 1219 readl(jme->regs + reg); 1220 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg); 1221} 1222 1223/* 1224 * PHY Regs 1225 */ 1226enum jme_phy_reg17_bit_masks { 1227 PREG17_SPEED = 0xC000, 1228 PREG17_DUPLEX = 0x2000, 1229 PREG17_SPDRSV = 0x0800, 1230 PREG17_LNKUP = 0x0400, 1231 PREG17_MDI = 0x0040, 1232}; 1233 1234enum jme_phy_reg17_vals { 1235 PREG17_SPEED_10M = 0x0000, 1236 PREG17_SPEED_100M = 0x4000, 1237 PREG17_SPEED_1000M = 0x8000, 1238}; 1239 1240#define BMSR_ANCOMP 0x0020 1241 1242/* 1243 * Workaround 1244 */ 1245static inline int is_buggy250(unsigned short device, u8 chiprev) 1246{ 1247 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11; 1248} 1249 1250static inline int new_phy_power_ctrl(u8 chip_main_rev) 1251{ 1252 return chip_main_rev >= 5; 1253} 1254 1255/* 1256 * Function prototypes 1257 */ 1258static int jme_set_link_ksettings(struct net_device *netdev, 1259 const struct ethtool_link_ksettings *cmd); 1260static void jme_set_unicastaddr(struct net_device *netdev); 1261static void jme_set_multi(struct net_device *netdev); 1262 1263#endif 1264