1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4#include <linux/pci.h> 5#include <linux/delay.h> 6#include <linux/sched.h> 7#include <linux/netdevice.h> 8 9#include "ixgbe.h" 10#include "ixgbe_common.h" 11#include "ixgbe_phy.h" 12 13static int ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 14static int ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 15static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 16static int ixgbe_ready_eeprom(struct ixgbe_hw *hw); 17static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 18static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 19 u16 count); 20static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 21static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 22static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 23static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 24 25static int ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 26static int ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 27static int ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 28 u16 words, u16 *data); 29static int ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 30 u16 words, u16 *data); 31static int ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 32 u16 offset); 33static int ixgbe_disable_pcie_primary(struct ixgbe_hw *hw); 34 35/* Base table for registers values that change by MAC */ 36const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = { 37 IXGBE_MVALS_INIT(8259X) 38}; 39 40/** 41 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow 42 * control 43 * @hw: pointer to hardware structure 44 * 45 * There are several phys that do not support autoneg flow control. This 46 * function check the device id to see if the associated phy supports 47 * autoneg flow control. 48 **/ 49bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 50{ 51 bool supported = false; 52 ixgbe_link_speed speed; 53 bool link_up; 54 55 switch (hw->phy.media_type) { 56 case ixgbe_media_type_fiber: 57 /* flow control autoneg black list */ 58 switch (hw->device_id) { 59 case IXGBE_DEV_ID_X550EM_A_SFP: 60 case IXGBE_DEV_ID_X550EM_A_SFP_N: 61 supported = false; 62 break; 63 default: 64 hw->mac.ops.check_link(hw, &speed, &link_up, false); 65 /* if link is down, assume supported */ 66 if (link_up) 67 supported = speed == IXGBE_LINK_SPEED_1GB_FULL; 68 else 69 supported = true; 70 } 71 72 break; 73 case ixgbe_media_type_backplane: 74 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 75 supported = false; 76 else 77 supported = true; 78 break; 79 case ixgbe_media_type_copper: 80 /* only some copper devices support flow control autoneg */ 81 switch (hw->device_id) { 82 case IXGBE_DEV_ID_82599_T3_LOM: 83 case IXGBE_DEV_ID_X540T: 84 case IXGBE_DEV_ID_X540T1: 85 case IXGBE_DEV_ID_X550T: 86 case IXGBE_DEV_ID_X550T1: 87 case IXGBE_DEV_ID_X550EM_X_10G_T: 88 case IXGBE_DEV_ID_X550EM_A_10G_T: 89 case IXGBE_DEV_ID_X550EM_A_1G_T: 90 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 91 supported = true; 92 break; 93 default: 94 break; 95 } 96 break; 97 default: 98 break; 99 } 100 101 if (!supported) 102 hw_dbg(hw, "Device %x does not support flow control autoneg\n", 103 hw->device_id); 104 105 return supported; 106} 107 108/** 109 * ixgbe_setup_fc_generic - Set up flow control 110 * @hw: pointer to hardware structure 111 * 112 * Called at init time to set up flow control. 113 **/ 114int ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 115{ 116 u32 reg = 0, reg_bp = 0; 117 bool locked = false; 118 int ret_val = 0; 119 u16 reg_cu = 0; 120 121 /* 122 * Validate the requested mode. Strict IEEE mode does not allow 123 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 124 */ 125 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 126 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 127 return -EINVAL; 128 } 129 130 /* 131 * 10gig parts do not have a word in the EEPROM to determine the 132 * default flow control setting, so we explicitly set it to full. 133 */ 134 if (hw->fc.requested_mode == ixgbe_fc_default) 135 hw->fc.requested_mode = ixgbe_fc_full; 136 137 /* 138 * Set up the 1G and 10G flow control advertisement registers so the 139 * HW will be able to do fc autoneg once the cable is plugged in. If 140 * we link at 10G, the 1G advertisement is harmless and vice versa. 141 */ 142 switch (hw->phy.media_type) { 143 case ixgbe_media_type_backplane: 144 /* some MAC's need RMW protection on AUTOC */ 145 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 146 if (ret_val) 147 return ret_val; 148 149 fallthrough; /* only backplane uses autoc */ 150 case ixgbe_media_type_fiber: 151 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 152 153 break; 154 case ixgbe_media_type_copper: 155 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 156 MDIO_MMD_AN, ®_cu); 157 break; 158 default: 159 break; 160 } 161 162 /* 163 * The possible values of fc.requested_mode are: 164 * 0: Flow control is completely disabled 165 * 1: Rx flow control is enabled (we can receive pause frames, 166 * but not send pause frames). 167 * 2: Tx flow control is enabled (we can send pause frames but 168 * we do not support receiving pause frames). 169 * 3: Both Rx and Tx flow control (symmetric) are enabled. 170 * other: Invalid. 171 */ 172 switch (hw->fc.requested_mode) { 173 case ixgbe_fc_none: 174 /* Flow control completely disabled by software override. */ 175 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 176 if (hw->phy.media_type == ixgbe_media_type_backplane) 177 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 178 IXGBE_AUTOC_ASM_PAUSE); 179 else if (hw->phy.media_type == ixgbe_media_type_copper) 180 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 181 break; 182 case ixgbe_fc_tx_pause: 183 /* 184 * Tx Flow control is enabled, and Rx Flow control is 185 * disabled by software override. 186 */ 187 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 188 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 189 if (hw->phy.media_type == ixgbe_media_type_backplane) { 190 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 191 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 192 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 193 reg_cu |= IXGBE_TAF_ASM_PAUSE; 194 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 195 } 196 break; 197 case ixgbe_fc_rx_pause: 198 /* 199 * Rx Flow control is enabled and Tx Flow control is 200 * disabled by software override. Since there really 201 * isn't a way to advertise that we are capable of RX 202 * Pause ONLY, we will advertise that we support both 203 * symmetric and asymmetric Rx PAUSE, as such we fall 204 * through to the fc_full statement. Later, we will 205 * disable the adapter's ability to send PAUSE frames. 206 */ 207 case ixgbe_fc_full: 208 /* Flow control (both Rx and Tx) is enabled by SW override. */ 209 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 210 if (hw->phy.media_type == ixgbe_media_type_backplane) 211 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 212 IXGBE_AUTOC_ASM_PAUSE; 213 else if (hw->phy.media_type == ixgbe_media_type_copper) 214 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 215 break; 216 default: 217 hw_dbg(hw, "Flow control param set incorrectly\n"); 218 return -EIO; 219 } 220 221 if (hw->mac.type != ixgbe_mac_X540) { 222 /* 223 * Enable auto-negotiation between the MAC & PHY; 224 * the MAC will advertise clause 37 flow control. 225 */ 226 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 227 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 228 229 /* Disable AN timeout */ 230 if (hw->fc.strict_ieee) 231 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 232 233 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 234 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); 235 } 236 237 /* 238 * AUTOC restart handles negotiation of 1G and 10G on backplane 239 * and copper. There is no need to set the PCS1GCTL register. 240 * 241 */ 242 if (hw->phy.media_type == ixgbe_media_type_backplane) { 243 /* Need the SW/FW semaphore around AUTOC writes if 82599 and 244 * LESM is on, likewise reset_pipeline requries the lock as 245 * it also writes AUTOC. 246 */ 247 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 248 if (ret_val) 249 return ret_val; 250 251 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 252 ixgbe_device_supports_autoneg_fc(hw)) { 253 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 254 MDIO_MMD_AN, reg_cu); 255 } 256 257 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 258 return ret_val; 259} 260 261/** 262 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 263 * @hw: pointer to hardware structure 264 * 265 * Starts the hardware by filling the bus info structure and media type, clears 266 * all on chip counters, initializes receive address registers, multicast 267 * table, VLAN filter table, calls routine to set up link and flow control 268 * settings, and leaves transmit and receive units disabled and uninitialized 269 **/ 270int ixgbe_start_hw_generic(struct ixgbe_hw *hw) 271{ 272 u16 device_caps; 273 u32 ctrl_ext; 274 int ret_val; 275 276 /* Set the media type */ 277 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 278 279 /* Identify the PHY */ 280 hw->phy.ops.identify(hw); 281 282 /* Clear the VLAN filter table */ 283 hw->mac.ops.clear_vfta(hw); 284 285 /* Clear statistics registers */ 286 hw->mac.ops.clear_hw_cntrs(hw); 287 288 /* Set No Snoop Disable */ 289 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 290 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 291 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 292 IXGBE_WRITE_FLUSH(hw); 293 294 /* Setup flow control if method for doing so */ 295 if (hw->mac.ops.setup_fc) { 296 ret_val = hw->mac.ops.setup_fc(hw); 297 if (ret_val) 298 return ret_val; 299 } 300 301 /* Cashe bit indicating need for crosstalk fix */ 302 switch (hw->mac.type) { 303 case ixgbe_mac_82599EB: 304 case ixgbe_mac_X550EM_x: 305 case ixgbe_mac_x550em_a: 306 hw->mac.ops.get_device_caps(hw, &device_caps); 307 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 308 hw->need_crosstalk_fix = false; 309 else 310 hw->need_crosstalk_fix = true; 311 break; 312 default: 313 hw->need_crosstalk_fix = false; 314 break; 315 } 316 317 /* Clear adapter stopped flag */ 318 hw->adapter_stopped = false; 319 320 return 0; 321} 322 323/** 324 * ixgbe_start_hw_gen2 - Init sequence for common device family 325 * @hw: pointer to hw structure 326 * 327 * Performs the init sequence common to the second generation 328 * of 10 GbE devices. 329 * Devices in the second generation: 330 * 82599 331 * X540 332 **/ 333int ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 334{ 335 u32 i; 336 337 /* Clear the rate limiters */ 338 for (i = 0; i < hw->mac.max_tx_queues; i++) { 339 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 340 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 341 } 342 IXGBE_WRITE_FLUSH(hw); 343 344 return 0; 345} 346 347/** 348 * ixgbe_init_hw_generic - Generic hardware initialization 349 * @hw: pointer to hardware structure 350 * 351 * Initialize the hardware by resetting the hardware, filling the bus info 352 * structure and media type, clears all on chip counters, initializes receive 353 * address registers, multicast table, VLAN filter table, calls routine to set 354 * up link and flow control settings, and leaves transmit and receive units 355 * disabled and uninitialized 356 **/ 357int ixgbe_init_hw_generic(struct ixgbe_hw *hw) 358{ 359 int status; 360 361 /* Reset the hardware */ 362 status = hw->mac.ops.reset_hw(hw); 363 364 if (status == 0) { 365 /* Start the HW */ 366 status = hw->mac.ops.start_hw(hw); 367 } 368 369 /* Initialize the LED link active for LED blink support */ 370 if (hw->mac.ops.init_led_link_act) 371 hw->mac.ops.init_led_link_act(hw); 372 373 return status; 374} 375 376/** 377 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 378 * @hw: pointer to hardware structure 379 * 380 * Clears all hardware statistics counters by reading them from the hardware 381 * Statistics counters are clear on read. 382 **/ 383int ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 384{ 385 u16 i = 0; 386 387 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 388 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 389 IXGBE_READ_REG(hw, IXGBE_ERRBC); 390 IXGBE_READ_REG(hw, IXGBE_MSPDC); 391 for (i = 0; i < 8; i++) 392 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 393 394 IXGBE_READ_REG(hw, IXGBE_MLFC); 395 IXGBE_READ_REG(hw, IXGBE_MRFC); 396 IXGBE_READ_REG(hw, IXGBE_RLEC); 397 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 398 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 399 if (hw->mac.type >= ixgbe_mac_82599EB) { 400 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 401 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 402 } else { 403 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 404 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 405 } 406 407 for (i = 0; i < 8; i++) { 408 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 409 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 410 if (hw->mac.type >= ixgbe_mac_82599EB) { 411 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 412 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 413 } else { 414 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 415 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 416 } 417 } 418 if (hw->mac.type >= ixgbe_mac_82599EB) 419 for (i = 0; i < 8; i++) 420 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 421 IXGBE_READ_REG(hw, IXGBE_PRC64); 422 IXGBE_READ_REG(hw, IXGBE_PRC127); 423 IXGBE_READ_REG(hw, IXGBE_PRC255); 424 IXGBE_READ_REG(hw, IXGBE_PRC511); 425 IXGBE_READ_REG(hw, IXGBE_PRC1023); 426 IXGBE_READ_REG(hw, IXGBE_PRC1522); 427 IXGBE_READ_REG(hw, IXGBE_GPRC); 428 IXGBE_READ_REG(hw, IXGBE_BPRC); 429 IXGBE_READ_REG(hw, IXGBE_MPRC); 430 IXGBE_READ_REG(hw, IXGBE_GPTC); 431 IXGBE_READ_REG(hw, IXGBE_GORCL); 432 IXGBE_READ_REG(hw, IXGBE_GORCH); 433 IXGBE_READ_REG(hw, IXGBE_GOTCL); 434 IXGBE_READ_REG(hw, IXGBE_GOTCH); 435 if (hw->mac.type == ixgbe_mac_82598EB) 436 for (i = 0; i < 8; i++) 437 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 438 IXGBE_READ_REG(hw, IXGBE_RUC); 439 IXGBE_READ_REG(hw, IXGBE_RFC); 440 IXGBE_READ_REG(hw, IXGBE_ROC); 441 IXGBE_READ_REG(hw, IXGBE_RJC); 442 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 443 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 444 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 445 IXGBE_READ_REG(hw, IXGBE_TORL); 446 IXGBE_READ_REG(hw, IXGBE_TORH); 447 IXGBE_READ_REG(hw, IXGBE_TPR); 448 IXGBE_READ_REG(hw, IXGBE_TPT); 449 IXGBE_READ_REG(hw, IXGBE_PTC64); 450 IXGBE_READ_REG(hw, IXGBE_PTC127); 451 IXGBE_READ_REG(hw, IXGBE_PTC255); 452 IXGBE_READ_REG(hw, IXGBE_PTC511); 453 IXGBE_READ_REG(hw, IXGBE_PTC1023); 454 IXGBE_READ_REG(hw, IXGBE_PTC1522); 455 IXGBE_READ_REG(hw, IXGBE_MPTC); 456 IXGBE_READ_REG(hw, IXGBE_BPTC); 457 for (i = 0; i < 16; i++) { 458 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 459 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 460 if (hw->mac.type >= ixgbe_mac_82599EB) { 461 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 462 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 463 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 464 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 465 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 466 } else { 467 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 468 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 469 } 470 } 471 472 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 473 if (hw->phy.id == 0) 474 hw->phy.ops.identify(hw); 475 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); 476 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); 477 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); 478 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); 479 } 480 481 return 0; 482} 483 484/** 485 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 486 * @hw: pointer to hardware structure 487 * @pba_num: stores the part number string from the EEPROM 488 * @pba_num_size: part number string buffer length 489 * 490 * Reads the part number string from the EEPROM. 491 **/ 492int ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 493 u32 pba_num_size) 494{ 495 int ret_val; 496 u16 pba_ptr; 497 u16 offset; 498 u16 length; 499 u16 data; 500 501 if (pba_num == NULL) { 502 hw_dbg(hw, "PBA string buffer was null\n"); 503 return -EINVAL; 504 } 505 506 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 507 if (ret_val) { 508 hw_dbg(hw, "NVM Read Error\n"); 509 return ret_val; 510 } 511 512 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 513 if (ret_val) { 514 hw_dbg(hw, "NVM Read Error\n"); 515 return ret_val; 516 } 517 518 /* 519 * if data is not ptr guard the PBA must be in legacy format which 520 * means pba_ptr is actually our second data word for the PBA number 521 * and we can decode it into an ascii string 522 */ 523 if (data != IXGBE_PBANUM_PTR_GUARD) { 524 hw_dbg(hw, "NVM PBA number is not stored as string\n"); 525 526 /* we will need 11 characters to store the PBA */ 527 if (pba_num_size < 11) { 528 hw_dbg(hw, "PBA string buffer too small\n"); 529 return -ENOSPC; 530 } 531 532 /* extract hex string from data and pba_ptr */ 533 pba_num[0] = (data >> 12) & 0xF; 534 pba_num[1] = (data >> 8) & 0xF; 535 pba_num[2] = (data >> 4) & 0xF; 536 pba_num[3] = data & 0xF; 537 pba_num[4] = (pba_ptr >> 12) & 0xF; 538 pba_num[5] = (pba_ptr >> 8) & 0xF; 539 pba_num[6] = '-'; 540 pba_num[7] = 0; 541 pba_num[8] = (pba_ptr >> 4) & 0xF; 542 pba_num[9] = pba_ptr & 0xF; 543 544 /* put a null character on the end of our string */ 545 pba_num[10] = '\0'; 546 547 /* switch all the data but the '-' to hex char */ 548 for (offset = 0; offset < 10; offset++) { 549 if (pba_num[offset] < 0xA) 550 pba_num[offset] += '0'; 551 else if (pba_num[offset] < 0x10) 552 pba_num[offset] += 'A' - 0xA; 553 } 554 555 return 0; 556 } 557 558 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 559 if (ret_val) { 560 hw_dbg(hw, "NVM Read Error\n"); 561 return ret_val; 562 } 563 564 if (length == 0xFFFF || length == 0) { 565 hw_dbg(hw, "NVM PBA number section invalid length\n"); 566 return -EIO; 567 } 568 569 /* check if pba_num buffer is big enough */ 570 if (pba_num_size < (((u32)length * 2) - 1)) { 571 hw_dbg(hw, "PBA string buffer too small\n"); 572 return -ENOSPC; 573 } 574 575 /* trim pba length from start of string */ 576 pba_ptr++; 577 length--; 578 579 for (offset = 0; offset < length; offset++) { 580 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 581 if (ret_val) { 582 hw_dbg(hw, "NVM Read Error\n"); 583 return ret_val; 584 } 585 pba_num[offset * 2] = (u8)(data >> 8); 586 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 587 } 588 pba_num[offset * 2] = '\0'; 589 590 return 0; 591} 592 593/** 594 * ixgbe_get_mac_addr_generic - Generic get MAC address 595 * @hw: pointer to hardware structure 596 * @mac_addr: Adapter MAC address 597 * 598 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 599 * A reset of the adapter must be performed prior to calling this function 600 * in order for the MAC address to have been loaded from the EEPROM into RAR0 601 **/ 602int ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 603{ 604 u32 rar_high; 605 u32 rar_low; 606 u16 i; 607 608 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 609 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 610 611 for (i = 0; i < 4; i++) 612 mac_addr[i] = (u8)(rar_low >> (i*8)); 613 614 for (i = 0; i < 2; i++) 615 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 616 617 return 0; 618} 619 620enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status) 621{ 622 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 623 case IXGBE_PCI_LINK_WIDTH_1: 624 return ixgbe_bus_width_pcie_x1; 625 case IXGBE_PCI_LINK_WIDTH_2: 626 return ixgbe_bus_width_pcie_x2; 627 case IXGBE_PCI_LINK_WIDTH_4: 628 return ixgbe_bus_width_pcie_x4; 629 case IXGBE_PCI_LINK_WIDTH_8: 630 return ixgbe_bus_width_pcie_x8; 631 default: 632 return ixgbe_bus_width_unknown; 633 } 634} 635 636enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status) 637{ 638 switch (link_status & IXGBE_PCI_LINK_SPEED) { 639 case IXGBE_PCI_LINK_SPEED_2500: 640 return ixgbe_bus_speed_2500; 641 case IXGBE_PCI_LINK_SPEED_5000: 642 return ixgbe_bus_speed_5000; 643 case IXGBE_PCI_LINK_SPEED_8000: 644 return ixgbe_bus_speed_8000; 645 default: 646 return ixgbe_bus_speed_unknown; 647 } 648} 649 650/** 651 * ixgbe_get_bus_info_generic - Generic set PCI bus info 652 * @hw: pointer to hardware structure 653 * 654 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 655 **/ 656int ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 657{ 658 u16 link_status; 659 660 hw->bus.type = ixgbe_bus_type_pci_express; 661 662 /* Get the negotiated link width and speed from PCI config space */ 663 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); 664 665 hw->bus.width = ixgbe_convert_bus_width(link_status); 666 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 667 668 hw->mac.ops.set_lan_id(hw); 669 670 return 0; 671} 672 673/** 674 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 675 * @hw: pointer to the HW structure 676 * 677 * Determines the LAN function id by reading memory-mapped registers 678 * and swaps the port value if requested. 679 **/ 680void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 681{ 682 struct ixgbe_bus_info *bus = &hw->bus; 683 u16 ee_ctrl_4; 684 u32 reg; 685 686 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 687 bus->func = FIELD_GET(IXGBE_STATUS_LAN_ID, reg); 688 bus->lan_id = bus->func; 689 690 /* check for a port swap */ 691 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 692 if (reg & IXGBE_FACTPS_LFS) 693 bus->func ^= 0x1; 694 695 /* Get MAC instance from EEPROM for configuring CS4227 */ 696 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 697 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 698 bus->instance_id = FIELD_GET(IXGBE_EE_CTRL_4_INST_ID, 699 ee_ctrl_4); 700 } 701} 702 703/** 704 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 705 * @hw: pointer to hardware structure 706 * 707 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 708 * disables transmit and receive units. The adapter_stopped flag is used by 709 * the shared code and drivers to determine if the adapter is in a stopped 710 * state and should not touch the hardware. 711 **/ 712int ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 713{ 714 u32 reg_val; 715 u16 i; 716 717 /* 718 * Set the adapter_stopped flag so other driver functions stop touching 719 * the hardware 720 */ 721 hw->adapter_stopped = true; 722 723 /* Disable the receive unit */ 724 hw->mac.ops.disable_rx(hw); 725 726 /* Clear interrupt mask to stop interrupts from being generated */ 727 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 728 729 /* Clear any pending interrupts, flush previous writes */ 730 IXGBE_READ_REG(hw, IXGBE_EICR); 731 732 /* Disable the transmit unit. Each queue must be disabled. */ 733 for (i = 0; i < hw->mac.max_tx_queues; i++) 734 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 735 736 /* Disable the receive unit by stopping each queue */ 737 for (i = 0; i < hw->mac.max_rx_queues; i++) { 738 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 739 reg_val &= ~IXGBE_RXDCTL_ENABLE; 740 reg_val |= IXGBE_RXDCTL_SWFLSH; 741 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 742 } 743 744 /* flush all queues disables */ 745 IXGBE_WRITE_FLUSH(hw); 746 usleep_range(1000, 2000); 747 748 /* 749 * Prevent the PCI-E bus from hanging by disabling PCI-E primary 750 * access and verify no pending requests 751 */ 752 return ixgbe_disable_pcie_primary(hw); 753} 754 755/** 756 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 757 * @hw: pointer to hardware structure 758 * 759 * Store the index for the link active LED. This will be used to support 760 * blinking the LED. 761 **/ 762int ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 763{ 764 struct ixgbe_mac_info *mac = &hw->mac; 765 u32 led_reg, led_mode; 766 u16 i; 767 768 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 769 770 /* Get LED link active from the LEDCTL register */ 771 for (i = 0; i < 4; i++) { 772 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 773 774 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 775 IXGBE_LED_LINK_ACTIVE) { 776 mac->led_link_act = i; 777 return 0; 778 } 779 } 780 781 /* If LEDCTL register does not have the LED link active set, then use 782 * known MAC defaults. 783 */ 784 switch (hw->mac.type) { 785 case ixgbe_mac_x550em_a: 786 mac->led_link_act = 0; 787 break; 788 case ixgbe_mac_X550EM_x: 789 mac->led_link_act = 1; 790 break; 791 default: 792 mac->led_link_act = 2; 793 } 794 795 return 0; 796} 797 798/** 799 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 800 * @hw: pointer to hardware structure 801 * @index: led number to turn on 802 **/ 803int ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 804{ 805 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 806 807 if (index > 3) 808 return -EINVAL; 809 810 /* To turn on the LED, set mode to ON. */ 811 led_reg &= ~IXGBE_LED_MODE_MASK(index); 812 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 813 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 814 IXGBE_WRITE_FLUSH(hw); 815 816 return 0; 817} 818 819/** 820 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 821 * @hw: pointer to hardware structure 822 * @index: led number to turn off 823 **/ 824int ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 825{ 826 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 827 828 if (index > 3) 829 return -EINVAL; 830 831 /* To turn off the LED, set mode to OFF. */ 832 led_reg &= ~IXGBE_LED_MODE_MASK(index); 833 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 834 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 835 IXGBE_WRITE_FLUSH(hw); 836 837 return 0; 838} 839 840/** 841 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 842 * @hw: pointer to hardware structure 843 * 844 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 845 * ixgbe_hw struct in order to set up EEPROM access. 846 **/ 847int ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 848{ 849 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 850 u32 eec; 851 u16 eeprom_size; 852 853 if (eeprom->type == ixgbe_eeprom_uninitialized) { 854 eeprom->type = ixgbe_eeprom_none; 855 /* Set default semaphore delay to 10ms which is a well 856 * tested value */ 857 eeprom->semaphore_delay = 10; 858 /* Clear EEPROM page size, it will be initialized as needed */ 859 eeprom->word_page_size = 0; 860 861 /* 862 * Check for EEPROM present first. 863 * If not present leave as none 864 */ 865 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 866 if (eec & IXGBE_EEC_PRES) { 867 eeprom->type = ixgbe_eeprom_spi; 868 869 /* 870 * SPI EEPROM is assumed here. This code would need to 871 * change if a future EEPROM is not SPI. 872 */ 873 eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec); 874 eeprom->word_size = BIT(eeprom_size + 875 IXGBE_EEPROM_WORD_SIZE_SHIFT); 876 } 877 878 if (eec & IXGBE_EEC_ADDR_SIZE) 879 eeprom->address_bits = 16; 880 else 881 eeprom->address_bits = 8; 882 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", 883 eeprom->type, eeprom->word_size, eeprom->address_bits); 884 } 885 886 return 0; 887} 888 889/** 890 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 891 * @hw: pointer to hardware structure 892 * @offset: offset within the EEPROM to write 893 * @words: number of words 894 * @data: 16 bit word(s) to write to EEPROM 895 * 896 * Reads 16 bit word(s) from EEPROM through bit-bang method 897 **/ 898int ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 899 u16 words, u16 *data) 900{ 901 u16 i, count; 902 int status; 903 904 hw->eeprom.ops.init_params(hw); 905 906 if (words == 0 || (offset + words > hw->eeprom.word_size)) 907 return -EINVAL; 908 909 /* 910 * The EEPROM page size cannot be queried from the chip. We do lazy 911 * initialization. It is worth to do that when we write large buffer. 912 */ 913 if ((hw->eeprom.word_page_size == 0) && 914 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 915 ixgbe_detect_eeprom_page_size_generic(hw, offset); 916 917 /* 918 * We cannot hold synchronization semaphores for too long 919 * to avoid other entity starvation. However it is more efficient 920 * to read in bursts than synchronizing access for each word. 921 */ 922 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 923 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 924 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 925 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 926 count, &data[i]); 927 928 if (status != 0) 929 break; 930 } 931 932 return status; 933} 934 935/** 936 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 937 * @hw: pointer to hardware structure 938 * @offset: offset within the EEPROM to be written to 939 * @words: number of word(s) 940 * @data: 16 bit word(s) to be written to the EEPROM 941 * 942 * If ixgbe_eeprom_update_checksum is not called after this function, the 943 * EEPROM will most likely contain an invalid checksum. 944 **/ 945static int ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 946 u16 words, u16 *data) 947{ 948 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 949 u16 page_size; 950 int status; 951 u16 word; 952 u16 i; 953 954 /* Prepare the EEPROM for writing */ 955 status = ixgbe_acquire_eeprom(hw); 956 if (status) 957 return status; 958 959 if (ixgbe_ready_eeprom(hw) != 0) { 960 ixgbe_release_eeprom(hw); 961 return -EIO; 962 } 963 964 for (i = 0; i < words; i++) { 965 ixgbe_standby_eeprom(hw); 966 967 /* Send the WRITE ENABLE command (8 bit opcode) */ 968 ixgbe_shift_out_eeprom_bits(hw, 969 IXGBE_EEPROM_WREN_OPCODE_SPI, 970 IXGBE_EEPROM_OPCODE_BITS); 971 972 ixgbe_standby_eeprom(hw); 973 974 /* Some SPI eeproms use the 8th address bit embedded 975 * in the opcode 976 */ 977 if ((hw->eeprom.address_bits == 8) && 978 ((offset + i) >= 128)) 979 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 980 981 /* Send the Write command (8-bit opcode + addr) */ 982 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 983 IXGBE_EEPROM_OPCODE_BITS); 984 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 985 hw->eeprom.address_bits); 986 987 page_size = hw->eeprom.word_page_size; 988 989 /* Send the data in burst via SPI */ 990 do { 991 word = data[i]; 992 word = (word >> 8) | (word << 8); 993 ixgbe_shift_out_eeprom_bits(hw, word, 16); 994 995 if (page_size == 0) 996 break; 997 998 /* do not wrap around page */ 999 if (((offset + i) & (page_size - 1)) == 1000 (page_size - 1)) 1001 break; 1002 } while (++i < words); 1003 1004 ixgbe_standby_eeprom(hw); 1005 usleep_range(10000, 20000); 1006 } 1007 /* Done with writing - release the EEPROM */ 1008 ixgbe_release_eeprom(hw); 1009 1010 return 0; 1011} 1012 1013/** 1014 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1015 * @hw: pointer to hardware structure 1016 * @offset: offset within the EEPROM to be written to 1017 * @data: 16 bit word to be written to the EEPROM 1018 * 1019 * If ixgbe_eeprom_update_checksum is not called after this function, the 1020 * EEPROM will most likely contain an invalid checksum. 1021 **/ 1022int ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1023{ 1024 hw->eeprom.ops.init_params(hw); 1025 1026 if (offset >= hw->eeprom.word_size) 1027 return -EINVAL; 1028 1029 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1030} 1031 1032/** 1033 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1034 * @hw: pointer to hardware structure 1035 * @offset: offset within the EEPROM to be read 1036 * @words: number of word(s) 1037 * @data: read 16 bit words(s) from EEPROM 1038 * 1039 * Reads 16 bit word(s) from EEPROM through bit-bang method 1040 **/ 1041int ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1042 u16 words, u16 *data) 1043{ 1044 u16 i, count; 1045 int status; 1046 1047 hw->eeprom.ops.init_params(hw); 1048 1049 if (words == 0 || (offset + words > hw->eeprom.word_size)) 1050 return -EINVAL; 1051 1052 /* 1053 * We cannot hold synchronization semaphores for too long 1054 * to avoid other entity starvation. However it is more efficient 1055 * to read in bursts than synchronizing access for each word. 1056 */ 1057 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1058 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1059 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1060 1061 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1062 count, &data[i]); 1063 1064 if (status) 1065 return status; 1066 } 1067 1068 return 0; 1069} 1070 1071/** 1072 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1073 * @hw: pointer to hardware structure 1074 * @offset: offset within the EEPROM to be read 1075 * @words: number of word(s) 1076 * @data: read 16 bit word(s) from EEPROM 1077 * 1078 * Reads 16 bit word(s) from EEPROM through bit-bang method 1079 **/ 1080static int ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1081 u16 words, u16 *data) 1082{ 1083 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1084 u16 word_in; 1085 int status; 1086 u16 i; 1087 1088 /* Prepare the EEPROM for reading */ 1089 status = ixgbe_acquire_eeprom(hw); 1090 if (status) 1091 return status; 1092 1093 if (ixgbe_ready_eeprom(hw) != 0) { 1094 ixgbe_release_eeprom(hw); 1095 return -EIO; 1096 } 1097 1098 for (i = 0; i < words; i++) { 1099 ixgbe_standby_eeprom(hw); 1100 /* Some SPI eeproms use the 8th address bit embedded 1101 * in the opcode 1102 */ 1103 if ((hw->eeprom.address_bits == 8) && 1104 ((offset + i) >= 128)) 1105 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1106 1107 /* Send the READ command (opcode + addr) */ 1108 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1109 IXGBE_EEPROM_OPCODE_BITS); 1110 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1111 hw->eeprom.address_bits); 1112 1113 /* Read the data. */ 1114 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1115 data[i] = (word_in >> 8) | (word_in << 8); 1116 } 1117 1118 /* End this read operation */ 1119 ixgbe_release_eeprom(hw); 1120 1121 return 0; 1122} 1123 1124/** 1125 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1126 * @hw: pointer to hardware structure 1127 * @offset: offset within the EEPROM to be read 1128 * @data: read 16 bit value from EEPROM 1129 * 1130 * Reads 16 bit value from EEPROM through bit-bang method 1131 **/ 1132int ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1133 u16 *data) 1134{ 1135 hw->eeprom.ops.init_params(hw); 1136 1137 if (offset >= hw->eeprom.word_size) 1138 return -EINVAL; 1139 1140 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1141} 1142 1143/** 1144 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1145 * @hw: pointer to hardware structure 1146 * @offset: offset of word in the EEPROM to read 1147 * @words: number of word(s) 1148 * @data: 16 bit word(s) from the EEPROM 1149 * 1150 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1151 **/ 1152int ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1153 u16 words, u16 *data) 1154{ 1155 int status; 1156 u32 eerd; 1157 u32 i; 1158 1159 hw->eeprom.ops.init_params(hw); 1160 1161 if (words == 0 || offset >= hw->eeprom.word_size) 1162 return -EINVAL; 1163 1164 for (i = 0; i < words; i++) { 1165 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1166 IXGBE_EEPROM_RW_REG_START; 1167 1168 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1169 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1170 1171 if (status == 0) { 1172 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1173 IXGBE_EEPROM_RW_REG_DATA); 1174 } else { 1175 hw_dbg(hw, "Eeprom read timed out\n"); 1176 return status; 1177 } 1178 } 1179 1180 return 0; 1181} 1182 1183/** 1184 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1185 * @hw: pointer to hardware structure 1186 * @offset: offset within the EEPROM to be used as a scratch pad 1187 * 1188 * Discover EEPROM page size by writing marching data at given offset. 1189 * This function is called only when we are writing a new large buffer 1190 * at given offset so the data would be overwritten anyway. 1191 **/ 1192static int ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1193 u16 offset) 1194{ 1195 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1196 int status; 1197 u16 i; 1198 1199 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1200 data[i] = i; 1201 1202 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1203 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1204 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1205 hw->eeprom.word_page_size = 0; 1206 if (status) 1207 return status; 1208 1209 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1210 if (status) 1211 return status; 1212 1213 /* 1214 * When writing in burst more than the actual page size 1215 * EEPROM address wraps around current page. 1216 */ 1217 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1218 1219 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", 1220 hw->eeprom.word_page_size); 1221 return 0; 1222} 1223 1224/** 1225 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1226 * @hw: pointer to hardware structure 1227 * @offset: offset of word in the EEPROM to read 1228 * @data: word read from the EEPROM 1229 * 1230 * Reads a 16 bit word from the EEPROM using the EERD register. 1231 **/ 1232int ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1233{ 1234 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1235} 1236 1237/** 1238 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1239 * @hw: pointer to hardware structure 1240 * @offset: offset of word in the EEPROM to write 1241 * @words: number of words 1242 * @data: word(s) write to the EEPROM 1243 * 1244 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1245 **/ 1246int ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1247 u16 words, u16 *data) 1248{ 1249 int status; 1250 u32 eewr; 1251 u16 i; 1252 1253 hw->eeprom.ops.init_params(hw); 1254 1255 if (words == 0 || offset >= hw->eeprom.word_size) 1256 return -EINVAL; 1257 1258 for (i = 0; i < words; i++) { 1259 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1260 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1261 IXGBE_EEPROM_RW_REG_START; 1262 1263 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1264 if (status) { 1265 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1266 return status; 1267 } 1268 1269 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1270 1271 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1272 if (status) { 1273 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1274 return status; 1275 } 1276 } 1277 1278 return 0; 1279} 1280 1281/** 1282 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1283 * @hw: pointer to hardware structure 1284 * @offset: offset of word in the EEPROM to write 1285 * @data: word write to the EEPROM 1286 * 1287 * Write a 16 bit word to the EEPROM using the EEWR register. 1288 **/ 1289int ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1290{ 1291 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1292} 1293 1294/** 1295 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1296 * @hw: pointer to hardware structure 1297 * @ee_reg: EEPROM flag for polling 1298 * 1299 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1300 * read or write is done respectively. 1301 **/ 1302static int ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1303{ 1304 u32 i; 1305 u32 reg; 1306 1307 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1308 if (ee_reg == IXGBE_NVM_POLL_READ) 1309 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1310 else 1311 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1312 1313 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1314 return 0; 1315 } 1316 udelay(5); 1317 } 1318 return -EIO; 1319} 1320 1321/** 1322 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1323 * @hw: pointer to hardware structure 1324 * 1325 * Prepares EEPROM for access using bit-bang method. This function should 1326 * be called before issuing a command to the EEPROM. 1327 **/ 1328static int ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1329{ 1330 u32 eec; 1331 u32 i; 1332 1333 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) 1334 return -EBUSY; 1335 1336 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1337 1338 /* Request EEPROM Access */ 1339 eec |= IXGBE_EEC_REQ; 1340 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1341 1342 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1343 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1344 if (eec & IXGBE_EEC_GNT) 1345 break; 1346 udelay(5); 1347 } 1348 1349 /* Release if grant not acquired */ 1350 if (!(eec & IXGBE_EEC_GNT)) { 1351 eec &= ~IXGBE_EEC_REQ; 1352 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1353 hw_dbg(hw, "Could not acquire EEPROM grant\n"); 1354 1355 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1356 return -EIO; 1357 } 1358 1359 /* Setup EEPROM for Read/Write */ 1360 /* Clear CS and SK */ 1361 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1362 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1363 IXGBE_WRITE_FLUSH(hw); 1364 udelay(1); 1365 return 0; 1366} 1367 1368/** 1369 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1370 * @hw: pointer to hardware structure 1371 * 1372 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1373 **/ 1374static int ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1375{ 1376 u32 timeout = 2000; 1377 u32 i; 1378 u32 swsm; 1379 1380 /* Get SMBI software semaphore between device drivers first */ 1381 for (i = 0; i < timeout; i++) { 1382 /* 1383 * If the SMBI bit is 0 when we read it, then the bit will be 1384 * set and we have the semaphore 1385 */ 1386 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1387 if (!(swsm & IXGBE_SWSM_SMBI)) 1388 break; 1389 usleep_range(50, 100); 1390 } 1391 1392 if (i == timeout) { 1393 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); 1394 /* this release is particularly important because our attempts 1395 * above to get the semaphore may have succeeded, and if there 1396 * was a timeout, we should unconditionally clear the semaphore 1397 * bits to free the driver to make progress 1398 */ 1399 ixgbe_release_eeprom_semaphore(hw); 1400 1401 usleep_range(50, 100); 1402 /* one last try 1403 * If the SMBI bit is 0 when we read it, then the bit will be 1404 * set and we have the semaphore 1405 */ 1406 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1407 if (swsm & IXGBE_SWSM_SMBI) { 1408 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); 1409 return -EIO; 1410 } 1411 } 1412 1413 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1414 for (i = 0; i < timeout; i++) { 1415 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1416 1417 /* Set the SW EEPROM semaphore bit to request access */ 1418 swsm |= IXGBE_SWSM_SWESMBI; 1419 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1420 1421 /* If we set the bit successfully then we got the 1422 * semaphore. 1423 */ 1424 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1425 if (swsm & IXGBE_SWSM_SWESMBI) 1426 break; 1427 1428 usleep_range(50, 100); 1429 } 1430 1431 /* Release semaphores and return error if SW EEPROM semaphore 1432 * was not granted because we don't have access to the EEPROM 1433 */ 1434 if (i >= timeout) { 1435 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); 1436 ixgbe_release_eeprom_semaphore(hw); 1437 return -EIO; 1438 } 1439 1440 return 0; 1441} 1442 1443/** 1444 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1445 * @hw: pointer to hardware structure 1446 * 1447 * This function clears hardware semaphore bits. 1448 **/ 1449static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1450{ 1451 u32 swsm; 1452 1453 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1454 1455 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1456 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1457 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1458 IXGBE_WRITE_FLUSH(hw); 1459} 1460 1461/** 1462 * ixgbe_ready_eeprom - Polls for EEPROM ready 1463 * @hw: pointer to hardware structure 1464 **/ 1465static int ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1466{ 1467 u16 i; 1468 u8 spi_stat_reg; 1469 1470 /* 1471 * Read "Status Register" repeatedly until the LSB is cleared. The 1472 * EEPROM will signal that the command has been completed by clearing 1473 * bit 0 of the internal status register. If it's not cleared within 1474 * 5 milliseconds, then error out. 1475 */ 1476 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1477 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1478 IXGBE_EEPROM_OPCODE_BITS); 1479 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1480 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1481 break; 1482 1483 udelay(5); 1484 ixgbe_standby_eeprom(hw); 1485 } 1486 1487 /* 1488 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1489 * devices (and only 0-5mSec on 5V devices) 1490 */ 1491 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1492 hw_dbg(hw, "SPI EEPROM Status error\n"); 1493 return -EIO; 1494 } 1495 1496 return 0; 1497} 1498 1499/** 1500 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1501 * @hw: pointer to hardware structure 1502 **/ 1503static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1504{ 1505 u32 eec; 1506 1507 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1508 1509 /* Toggle CS to flush commands */ 1510 eec |= IXGBE_EEC_CS; 1511 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1512 IXGBE_WRITE_FLUSH(hw); 1513 udelay(1); 1514 eec &= ~IXGBE_EEC_CS; 1515 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1516 IXGBE_WRITE_FLUSH(hw); 1517 udelay(1); 1518} 1519 1520/** 1521 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1522 * @hw: pointer to hardware structure 1523 * @data: data to send to the EEPROM 1524 * @count: number of bits to shift out 1525 **/ 1526static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1527 u16 count) 1528{ 1529 u32 eec; 1530 u32 mask; 1531 u32 i; 1532 1533 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1534 1535 /* 1536 * Mask is used to shift "count" bits of "data" out to the EEPROM 1537 * one bit at a time. Determine the starting bit based on count 1538 */ 1539 mask = BIT(count - 1); 1540 1541 for (i = 0; i < count; i++) { 1542 /* 1543 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1544 * "1", and then raising and then lowering the clock (the SK 1545 * bit controls the clock input to the EEPROM). A "0" is 1546 * shifted out to the EEPROM by setting "DI" to "0" and then 1547 * raising and then lowering the clock. 1548 */ 1549 if (data & mask) 1550 eec |= IXGBE_EEC_DI; 1551 else 1552 eec &= ~IXGBE_EEC_DI; 1553 1554 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1555 IXGBE_WRITE_FLUSH(hw); 1556 1557 udelay(1); 1558 1559 ixgbe_raise_eeprom_clk(hw, &eec); 1560 ixgbe_lower_eeprom_clk(hw, &eec); 1561 1562 /* 1563 * Shift mask to signify next bit of data to shift in to the 1564 * EEPROM 1565 */ 1566 mask = mask >> 1; 1567 } 1568 1569 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1570 eec &= ~IXGBE_EEC_DI; 1571 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1572 IXGBE_WRITE_FLUSH(hw); 1573} 1574 1575/** 1576 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1577 * @hw: pointer to hardware structure 1578 * @count: number of bits to shift 1579 **/ 1580static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1581{ 1582 u32 eec; 1583 u32 i; 1584 u16 data = 0; 1585 1586 /* 1587 * In order to read a register from the EEPROM, we need to shift 1588 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1589 * the clock input to the EEPROM (setting the SK bit), and then reading 1590 * the value of the "DO" bit. During this "shifting in" process the 1591 * "DI" bit should always be clear. 1592 */ 1593 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1594 1595 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1596 1597 for (i = 0; i < count; i++) { 1598 data = data << 1; 1599 ixgbe_raise_eeprom_clk(hw, &eec); 1600 1601 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1602 1603 eec &= ~(IXGBE_EEC_DI); 1604 if (eec & IXGBE_EEC_DO) 1605 data |= 1; 1606 1607 ixgbe_lower_eeprom_clk(hw, &eec); 1608 } 1609 1610 return data; 1611} 1612 1613/** 1614 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1615 * @hw: pointer to hardware structure 1616 * @eec: EEC register's current value 1617 **/ 1618static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1619{ 1620 /* 1621 * Raise the clock input to the EEPROM 1622 * (setting the SK bit), then delay 1623 */ 1624 *eec = *eec | IXGBE_EEC_SK; 1625 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1626 IXGBE_WRITE_FLUSH(hw); 1627 udelay(1); 1628} 1629 1630/** 1631 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1632 * @hw: pointer to hardware structure 1633 * @eec: EEC's current value 1634 **/ 1635static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1636{ 1637 /* 1638 * Lower the clock input to the EEPROM (clearing the SK bit), then 1639 * delay 1640 */ 1641 *eec = *eec & ~IXGBE_EEC_SK; 1642 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1643 IXGBE_WRITE_FLUSH(hw); 1644 udelay(1); 1645} 1646 1647/** 1648 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1649 * @hw: pointer to hardware structure 1650 **/ 1651static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1652{ 1653 u32 eec; 1654 1655 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1656 1657 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1658 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1659 1660 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1661 IXGBE_WRITE_FLUSH(hw); 1662 1663 udelay(1); 1664 1665 /* Stop requesting EEPROM access */ 1666 eec &= ~IXGBE_EEC_REQ; 1667 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1668 1669 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1670 1671 /* 1672 * Delay before attempt to obtain semaphore again to allow FW 1673 * access. semaphore_delay is in ms we need us for usleep_range 1674 */ 1675 usleep_range(hw->eeprom.semaphore_delay * 1000, 1676 hw->eeprom.semaphore_delay * 2000); 1677} 1678 1679/** 1680 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1681 * @hw: pointer to hardware structure 1682 **/ 1683int ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1684{ 1685 u16 i; 1686 u16 j; 1687 u16 checksum = 0; 1688 u16 length = 0; 1689 u16 pointer = 0; 1690 u16 word = 0; 1691 1692 /* Include 0x0-0x3F in the checksum */ 1693 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1694 if (hw->eeprom.ops.read(hw, i, &word)) { 1695 hw_dbg(hw, "EEPROM read failed\n"); 1696 break; 1697 } 1698 checksum += word; 1699 } 1700 1701 /* Include all data from pointers except for the fw pointer */ 1702 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1703 if (hw->eeprom.ops.read(hw, i, &pointer)) { 1704 hw_dbg(hw, "EEPROM read failed\n"); 1705 return -EIO; 1706 } 1707 1708 /* If the pointer seems invalid */ 1709 if (pointer == 0xFFFF || pointer == 0) 1710 continue; 1711 1712 if (hw->eeprom.ops.read(hw, pointer, &length)) { 1713 hw_dbg(hw, "EEPROM read failed\n"); 1714 return -EIO; 1715 } 1716 1717 if (length == 0xFFFF || length == 0) 1718 continue; 1719 1720 for (j = pointer + 1; j <= pointer + length; j++) { 1721 if (hw->eeprom.ops.read(hw, j, &word)) { 1722 hw_dbg(hw, "EEPROM read failed\n"); 1723 return -EIO; 1724 } 1725 checksum += word; 1726 } 1727 } 1728 1729 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1730 1731 return (int)checksum; 1732} 1733 1734/** 1735 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1736 * @hw: pointer to hardware structure 1737 * @checksum_val: calculated checksum 1738 * 1739 * Performs checksum calculation and validates the EEPROM checksum. If the 1740 * caller does not need checksum_val, the value can be NULL. 1741 **/ 1742int ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1743 u16 *checksum_val) 1744{ 1745 u16 read_checksum = 0; 1746 u16 checksum; 1747 int status; 1748 1749 /* 1750 * Read the first word from the EEPROM. If this times out or fails, do 1751 * not continue or we could be in for a very long wait while every 1752 * EEPROM read fails 1753 */ 1754 status = hw->eeprom.ops.read(hw, 0, &checksum); 1755 if (status) { 1756 hw_dbg(hw, "EEPROM read failed\n"); 1757 return status; 1758 } 1759 1760 status = hw->eeprom.ops.calc_checksum(hw); 1761 if (status < 0) 1762 return status; 1763 1764 checksum = (u16)(status & 0xffff); 1765 1766 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1767 if (status) { 1768 hw_dbg(hw, "EEPROM read failed\n"); 1769 return status; 1770 } 1771 1772 /* Verify read checksum from EEPROM is the same as 1773 * calculated checksum 1774 */ 1775 if (read_checksum != checksum) 1776 status = -EIO; 1777 1778 /* If the user cares, return the calculated checksum */ 1779 if (checksum_val) 1780 *checksum_val = checksum; 1781 1782 return status; 1783} 1784 1785/** 1786 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1787 * @hw: pointer to hardware structure 1788 **/ 1789int ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1790{ 1791 u16 checksum; 1792 int status; 1793 1794 /* 1795 * Read the first word from the EEPROM. If this times out or fails, do 1796 * not continue or we could be in for a very long wait while every 1797 * EEPROM read fails 1798 */ 1799 status = hw->eeprom.ops.read(hw, 0, &checksum); 1800 if (status) { 1801 hw_dbg(hw, "EEPROM read failed\n"); 1802 return status; 1803 } 1804 1805 status = hw->eeprom.ops.calc_checksum(hw); 1806 if (status < 0) 1807 return status; 1808 1809 checksum = (u16)(status & 0xffff); 1810 1811 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 1812 1813 return status; 1814} 1815 1816/** 1817 * ixgbe_set_rar_generic - Set Rx address register 1818 * @hw: pointer to hardware structure 1819 * @index: Receive address register to write 1820 * @addr: Address to put into receive address register 1821 * @vmdq: VMDq "set" or "pool" index 1822 * @enable_addr: set flag that address is active 1823 * 1824 * Puts an ethernet address into a receive address register. 1825 **/ 1826int ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1827 u32 enable_addr) 1828{ 1829 u32 rar_low, rar_high; 1830 u32 rar_entries = hw->mac.num_rar_entries; 1831 1832 /* Make sure we are using a valid rar index range */ 1833 if (index >= rar_entries) { 1834 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1835 return -EINVAL; 1836 } 1837 1838 /* setup VMDq pool selection before this RAR gets enabled */ 1839 hw->mac.ops.set_vmdq(hw, index, vmdq); 1840 1841 /* 1842 * HW expects these in little endian so we reverse the byte 1843 * order from network order (big endian) to little endian 1844 */ 1845 rar_low = ((u32)addr[0] | 1846 ((u32)addr[1] << 8) | 1847 ((u32)addr[2] << 16) | 1848 ((u32)addr[3] << 24)); 1849 /* 1850 * Some parts put the VMDq setting in the extra RAH bits, 1851 * so save everything except the lower 16 bits that hold part 1852 * of the address and the address valid bit. 1853 */ 1854 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1855 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1856 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1857 1858 if (enable_addr != 0) 1859 rar_high |= IXGBE_RAH_AV; 1860 1861 /* Record lower 32 bits of MAC address and then make 1862 * sure that write is flushed to hardware before writing 1863 * the upper 16 bits and setting the valid bit. 1864 */ 1865 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1866 IXGBE_WRITE_FLUSH(hw); 1867 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1868 1869 return 0; 1870} 1871 1872/** 1873 * ixgbe_clear_rar_generic - Remove Rx address register 1874 * @hw: pointer to hardware structure 1875 * @index: Receive address register to write 1876 * 1877 * Clears an ethernet address from a receive address register. 1878 **/ 1879int ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1880{ 1881 u32 rar_high; 1882 u32 rar_entries = hw->mac.num_rar_entries; 1883 1884 /* Make sure we are using a valid rar index range */ 1885 if (index >= rar_entries) { 1886 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1887 return -EINVAL; 1888 } 1889 1890 /* 1891 * Some parts put the VMDq setting in the extra RAH bits, 1892 * so save everything except the lower 16 bits that hold part 1893 * of the address and the address valid bit. 1894 */ 1895 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1896 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1897 1898 /* Clear the address valid bit and upper 16 bits of the address 1899 * before clearing the lower bits. This way we aren't updating 1900 * a live filter. 1901 */ 1902 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1903 IXGBE_WRITE_FLUSH(hw); 1904 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1905 1906 /* clear VMDq pool/queue selection for this RAR */ 1907 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1908 1909 return 0; 1910} 1911 1912/** 1913 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1914 * @hw: pointer to hardware structure 1915 * 1916 * Places the MAC address in receive address register 0 and clears the rest 1917 * of the receive address registers. Clears the multicast table. Assumes 1918 * the receiver is in reset when the routine is called. 1919 **/ 1920int ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1921{ 1922 u32 i; 1923 u32 rar_entries = hw->mac.num_rar_entries; 1924 1925 /* 1926 * If the current mac address is valid, assume it is a software override 1927 * to the permanent address. 1928 * Otherwise, use the permanent address from the eeprom. 1929 */ 1930 if (!is_valid_ether_addr(hw->mac.addr)) { 1931 /* Get the MAC address from the RAR0 for later reference */ 1932 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1933 1934 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); 1935 } else { 1936 /* Setup the receive address. */ 1937 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); 1938 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); 1939 1940 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1941 } 1942 1943 /* clear VMDq pool/queue selection for RAR 0 */ 1944 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 1945 1946 hw->addr_ctrl.overflow_promisc = 0; 1947 1948 hw->addr_ctrl.rar_used_count = 1; 1949 1950 /* Zero out the other receive addresses. */ 1951 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); 1952 for (i = 1; i < rar_entries; i++) { 1953 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1954 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1955 } 1956 1957 /* Clear the MTA */ 1958 hw->addr_ctrl.mta_in_use = 0; 1959 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1960 1961 hw_dbg(hw, " Clearing MTA\n"); 1962 for (i = 0; i < hw->mac.mcft_size; i++) 1963 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1964 1965 if (hw->mac.ops.init_uta_tables) 1966 hw->mac.ops.init_uta_tables(hw); 1967 1968 return 0; 1969} 1970 1971/** 1972 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1973 * @hw: pointer to hardware structure 1974 * @mc_addr: the multicast address 1975 * 1976 * Extracts the 12 bits, from a multicast address, to determine which 1977 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1978 * incoming rx multicast addresses, to determine the bit-vector to check in 1979 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1980 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1981 * to mc_filter_type. 1982 **/ 1983static int ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1984{ 1985 u32 vector = 0; 1986 1987 switch (hw->mac.mc_filter_type) { 1988 case 0: /* use bits [47:36] of the address */ 1989 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1990 break; 1991 case 1: /* use bits [46:35] of the address */ 1992 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1993 break; 1994 case 2: /* use bits [45:34] of the address */ 1995 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1996 break; 1997 case 3: /* use bits [43:32] of the address */ 1998 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1999 break; 2000 default: /* Invalid mc_filter_type */ 2001 hw_dbg(hw, "MC filter type param set incorrectly\n"); 2002 break; 2003 } 2004 2005 /* vector can only be 12-bits or boundary will be exceeded */ 2006 vector &= 0xFFF; 2007 return vector; 2008} 2009 2010/** 2011 * ixgbe_set_mta - Set bit-vector in multicast table 2012 * @hw: pointer to hardware structure 2013 * @mc_addr: Multicast address 2014 * 2015 * Sets the bit-vector in the multicast table. 2016 **/ 2017static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2018{ 2019 u32 vector; 2020 u32 vector_bit; 2021 u32 vector_reg; 2022 2023 hw->addr_ctrl.mta_in_use++; 2024 2025 vector = ixgbe_mta_vector(hw, mc_addr); 2026 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); 2027 2028 /* 2029 * The MTA is a register array of 128 32-bit registers. It is treated 2030 * like an array of 4096 bits. We want to set bit 2031 * BitArray[vector_value]. So we figure out what register the bit is 2032 * in, read it, OR in the new bit, then write back the new value. The 2033 * register is determined by the upper 7 bits of the vector value and 2034 * the bit within that register are determined by the lower 5 bits of 2035 * the value. 2036 */ 2037 vector_reg = (vector >> 5) & 0x7F; 2038 vector_bit = vector & 0x1F; 2039 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); 2040} 2041 2042/** 2043 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2044 * @hw: pointer to hardware structure 2045 * @netdev: pointer to net device structure 2046 * 2047 * The given list replaces any existing list. Clears the MC addrs from receive 2048 * address registers and the multicast table. Uses unused receive address 2049 * registers for the first multicast addresses, and hashes the rest into the 2050 * multicast table. 2051 **/ 2052int ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, 2053 struct net_device *netdev) 2054{ 2055 struct netdev_hw_addr *ha; 2056 u32 i; 2057 2058 /* 2059 * Set the new number of MC addresses that we are being requested to 2060 * use. 2061 */ 2062 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 2063 hw->addr_ctrl.mta_in_use = 0; 2064 2065 /* Clear mta_shadow */ 2066 hw_dbg(hw, " Clearing MTA\n"); 2067 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2068 2069 /* Update mta shadow */ 2070 netdev_for_each_mc_addr(ha, netdev) { 2071 hw_dbg(hw, " Adding the multicast addresses:\n"); 2072 ixgbe_set_mta(hw, ha->addr); 2073 } 2074 2075 /* Enable mta */ 2076 for (i = 0; i < hw->mac.mcft_size; i++) 2077 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2078 hw->mac.mta_shadow[i]); 2079 2080 if (hw->addr_ctrl.mta_in_use > 0) 2081 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2082 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2083 2084 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); 2085 return 0; 2086} 2087 2088/** 2089 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2090 * @hw: pointer to hardware structure 2091 * 2092 * Enables multicast address in RAR and the use of the multicast hash table. 2093 **/ 2094int ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2095{ 2096 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2097 2098 if (a->mta_in_use > 0) 2099 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2100 hw->mac.mc_filter_type); 2101 2102 return 0; 2103} 2104 2105/** 2106 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2107 * @hw: pointer to hardware structure 2108 * 2109 * Disables multicast address in RAR and the use of the multicast hash table. 2110 **/ 2111int ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2112{ 2113 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2114 2115 if (a->mta_in_use > 0) 2116 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2117 2118 return 0; 2119} 2120 2121/** 2122 * ixgbe_fc_enable_generic - Enable flow control 2123 * @hw: pointer to hardware structure 2124 * 2125 * Enable flow control according to the current settings. 2126 **/ 2127int ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2128{ 2129 u32 mflcn_reg, fccfg_reg; 2130 u32 reg; 2131 u32 fcrtl, fcrth; 2132 int i; 2133 2134 /* Validate the water mark configuration. */ 2135 if (!hw->fc.pause_time) 2136 return -EINVAL; 2137 2138 /* Low water mark of zero causes XOFF floods */ 2139 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2140 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2141 hw->fc.high_water[i]) { 2142 if (!hw->fc.low_water[i] || 2143 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2144 hw_dbg(hw, "Invalid water mark configuration\n"); 2145 return -EINVAL; 2146 } 2147 } 2148 } 2149 2150 /* Negotiate the fc mode to use */ 2151 hw->mac.ops.fc_autoneg(hw); 2152 2153 /* Disable any previous flow control settings */ 2154 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2155 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2156 2157 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2158 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2159 2160 /* 2161 * The possible values of fc.current_mode are: 2162 * 0: Flow control is completely disabled 2163 * 1: Rx flow control is enabled (we can receive pause frames, 2164 * but not send pause frames). 2165 * 2: Tx flow control is enabled (we can send pause frames but 2166 * we do not support receiving pause frames). 2167 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2168 * other: Invalid. 2169 */ 2170 switch (hw->fc.current_mode) { 2171 case ixgbe_fc_none: 2172 /* 2173 * Flow control is disabled by software override or autoneg. 2174 * The code below will actually disable it in the HW. 2175 */ 2176 break; 2177 case ixgbe_fc_rx_pause: 2178 /* 2179 * Rx Flow control is enabled and Tx Flow control is 2180 * disabled by software override. Since there really 2181 * isn't a way to advertise that we are capable of RX 2182 * Pause ONLY, we will advertise that we support both 2183 * symmetric and asymmetric Rx PAUSE. Later, we will 2184 * disable the adapter's ability to send PAUSE frames. 2185 */ 2186 mflcn_reg |= IXGBE_MFLCN_RFCE; 2187 break; 2188 case ixgbe_fc_tx_pause: 2189 /* 2190 * Tx Flow control is enabled, and Rx Flow control is 2191 * disabled by software override. 2192 */ 2193 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2194 break; 2195 case ixgbe_fc_full: 2196 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2197 mflcn_reg |= IXGBE_MFLCN_RFCE; 2198 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2199 break; 2200 default: 2201 hw_dbg(hw, "Flow control param set incorrectly\n"); 2202 return -EIO; 2203 } 2204 2205 /* Set 802.3x based flow control settings. */ 2206 mflcn_reg |= IXGBE_MFLCN_DPF; 2207 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2208 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2209 2210 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2211 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2212 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2213 hw->fc.high_water[i]) { 2214 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2215 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2216 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2217 } else { 2218 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2219 /* 2220 * In order to prevent Tx hangs when the internal Tx 2221 * switch is enabled we must set the high water mark 2222 * to the Rx packet buffer size - 24KB. This allows 2223 * the Tx switch to function even under heavy Rx 2224 * workloads. 2225 */ 2226 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2227 } 2228 2229 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2230 } 2231 2232 /* Configure pause time (2 TCs per register) */ 2233 reg = hw->fc.pause_time * 0x00010001U; 2234 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 2235 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2236 2237 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2238 2239 return 0; 2240} 2241 2242/** 2243 * ixgbe_negotiate_fc - Negotiate flow control 2244 * @hw: pointer to hardware structure 2245 * @adv_reg: flow control advertised settings 2246 * @lp_reg: link partner's flow control settings 2247 * @adv_sym: symmetric pause bit in advertisement 2248 * @adv_asm: asymmetric pause bit in advertisement 2249 * @lp_sym: symmetric pause bit in link partner advertisement 2250 * @lp_asm: asymmetric pause bit in link partner advertisement 2251 * 2252 * Find the intersection between advertised settings and link partner's 2253 * advertised settings 2254 **/ 2255int ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2256 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2257{ 2258 if ((!(adv_reg)) || (!(lp_reg))) 2259 return -EINVAL; 2260 2261 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2262 /* 2263 * Now we need to check if the user selected Rx ONLY 2264 * of pause frames. In this case, we had to advertise 2265 * FULL flow control because we could not advertise RX 2266 * ONLY. Hence, we must now check to see if we need to 2267 * turn OFF the TRANSMISSION of PAUSE frames. 2268 */ 2269 if (hw->fc.requested_mode == ixgbe_fc_full) { 2270 hw->fc.current_mode = ixgbe_fc_full; 2271 hw_dbg(hw, "Flow Control = FULL.\n"); 2272 } else { 2273 hw->fc.current_mode = ixgbe_fc_rx_pause; 2274 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); 2275 } 2276 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2277 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2278 hw->fc.current_mode = ixgbe_fc_tx_pause; 2279 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 2280 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2281 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2282 hw->fc.current_mode = ixgbe_fc_rx_pause; 2283 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 2284 } else { 2285 hw->fc.current_mode = ixgbe_fc_none; 2286 hw_dbg(hw, "Flow Control = NONE.\n"); 2287 } 2288 return 0; 2289} 2290 2291/** 2292 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2293 * @hw: pointer to hardware structure 2294 * 2295 * Enable flow control according on 1 gig fiber. 2296 **/ 2297static int ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2298{ 2299 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2300 int ret_val; 2301 2302 /* 2303 * On multispeed fiber at 1g, bail out if 2304 * - link is up but AN did not complete, or if 2305 * - link is up and AN completed but timed out 2306 */ 2307 2308 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2309 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2310 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) 2311 return -EIO; 2312 2313 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2314 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2315 2316 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2317 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2318 IXGBE_PCS1GANA_ASM_PAUSE, 2319 IXGBE_PCS1GANA_SYM_PAUSE, 2320 IXGBE_PCS1GANA_ASM_PAUSE); 2321 2322 return ret_val; 2323} 2324 2325/** 2326 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2327 * @hw: pointer to hardware structure 2328 * 2329 * Enable flow control according to IEEE clause 37. 2330 **/ 2331static int ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2332{ 2333 u32 links2, anlp1_reg, autoc_reg, links; 2334 int ret_val; 2335 2336 /* 2337 * On backplane, bail out if 2338 * - backplane autoneg was not completed, or if 2339 * - we are 82599 and link partner is not AN enabled 2340 */ 2341 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2342 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) 2343 return -EIO; 2344 2345 if (hw->mac.type == ixgbe_mac_82599EB) { 2346 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2347 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) 2348 return -EIO; 2349 } 2350 /* 2351 * Read the 10g AN autoc and LP ability registers and resolve 2352 * local flow control settings accordingly 2353 */ 2354 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2355 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2356 2357 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2358 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2359 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2360 2361 return ret_val; 2362} 2363 2364/** 2365 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2366 * @hw: pointer to hardware structure 2367 * 2368 * Enable flow control according to IEEE clause 37. 2369 **/ 2370static int ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2371{ 2372 u16 technology_ability_reg = 0; 2373 u16 lp_technology_ability_reg = 0; 2374 2375 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 2376 MDIO_MMD_AN, 2377 &technology_ability_reg); 2378 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, 2379 MDIO_MMD_AN, 2380 &lp_technology_ability_reg); 2381 2382 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2383 (u32)lp_technology_ability_reg, 2384 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2385 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2386} 2387 2388/** 2389 * ixgbe_fc_autoneg - Configure flow control 2390 * @hw: pointer to hardware structure 2391 * 2392 * Compares our advertised flow control capabilities to those advertised by 2393 * our link partner, and determines the proper flow control mode to use. 2394 **/ 2395void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2396{ 2397 ixgbe_link_speed speed; 2398 int ret_val = -EIO; 2399 bool link_up; 2400 2401 /* 2402 * AN should have completed when the cable was plugged in. 2403 * Look for reasons to bail out. Bail out if: 2404 * - FC autoneg is disabled, or if 2405 * - link is not up. 2406 * 2407 * Since we're being called from an LSC, link is already known to be up. 2408 * So use link_up_wait_to_complete=false. 2409 */ 2410 if (hw->fc.disable_fc_autoneg) 2411 goto out; 2412 2413 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2414 if (!link_up) 2415 goto out; 2416 2417 switch (hw->phy.media_type) { 2418 /* Autoneg flow control on fiber adapters */ 2419 case ixgbe_media_type_fiber: 2420 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 2421 ret_val = ixgbe_fc_autoneg_fiber(hw); 2422 break; 2423 2424 /* Autoneg flow control on backplane adapters */ 2425 case ixgbe_media_type_backplane: 2426 ret_val = ixgbe_fc_autoneg_backplane(hw); 2427 break; 2428 2429 /* Autoneg flow control on copper adapters */ 2430 case ixgbe_media_type_copper: 2431 if (ixgbe_device_supports_autoneg_fc(hw)) 2432 ret_val = ixgbe_fc_autoneg_copper(hw); 2433 break; 2434 2435 default: 2436 break; 2437 } 2438 2439out: 2440 if (ret_val == 0) { 2441 hw->fc.fc_was_autonegged = true; 2442 } else { 2443 hw->fc.fc_was_autonegged = false; 2444 hw->fc.current_mode = hw->fc.requested_mode; 2445 } 2446} 2447 2448/** 2449 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 2450 * @hw: pointer to hardware structure 2451 * 2452 * System-wide timeout range is encoded in PCIe Device Control2 register. 2453 * 2454 * Add 10% to specified maximum and return the number of times to poll for 2455 * completion timeout, in units of 100 microsec. Never return less than 2456 * 800 = 80 millisec. 2457 **/ 2458static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 2459{ 2460 s16 devctl2; 2461 u32 pollcnt; 2462 2463 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); 2464 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 2465 2466 switch (devctl2) { 2467 case IXGBE_PCIDEVCTRL2_65_130ms: 2468 pollcnt = 1300; /* 130 millisec */ 2469 break; 2470 case IXGBE_PCIDEVCTRL2_260_520ms: 2471 pollcnt = 5200; /* 520 millisec */ 2472 break; 2473 case IXGBE_PCIDEVCTRL2_1_2s: 2474 pollcnt = 20000; /* 2 sec */ 2475 break; 2476 case IXGBE_PCIDEVCTRL2_4_8s: 2477 pollcnt = 80000; /* 8 sec */ 2478 break; 2479 case IXGBE_PCIDEVCTRL2_17_34s: 2480 pollcnt = 34000; /* 34 sec */ 2481 break; 2482 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 2483 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 2484 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 2485 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 2486 default: 2487 pollcnt = 800; /* 80 millisec minimum */ 2488 break; 2489 } 2490 2491 /* add 10% to spec maximum */ 2492 return (pollcnt * 11) / 10; 2493} 2494 2495/** 2496 * ixgbe_disable_pcie_primary - Disable PCI-express primary access 2497 * @hw: pointer to hardware structure 2498 * 2499 * Disables PCI-Express primary access and verifies there are no pending 2500 * requests. -EALREADY is returned if primary disable 2501 * bit hasn't caused the primary requests to be disabled, else 0 2502 * is returned signifying primary requests disabled. 2503 **/ 2504static int ixgbe_disable_pcie_primary(struct ixgbe_hw *hw) 2505{ 2506 u32 i, poll; 2507 u16 value; 2508 2509 /* Always set this bit to ensure any future transactions are blocked */ 2510 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 2511 2512 /* Poll for bit to read as set */ 2513 for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) { 2514 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) 2515 break; 2516 usleep_range(100, 120); 2517 } 2518 if (i >= IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT) { 2519 hw_dbg(hw, "GIO disable did not set - requesting resets\n"); 2520 goto gio_disable_fail; 2521 } 2522 2523 /* Exit if primary requests are blocked */ 2524 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 2525 ixgbe_removed(hw->hw_addr)) 2526 return 0; 2527 2528 /* Poll for primary request bit to clear */ 2529 for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) { 2530 udelay(100); 2531 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2532 return 0; 2533 } 2534 2535 /* 2536 * Two consecutive resets are required via CTRL.RST per datasheet 2537 * 5.2.5.3.2 Primary Disable. We set a flag to inform the reset routine 2538 * of this need. The first reset prevents new primary requests from 2539 * being issued by our device. We then must wait 1usec or more for any 2540 * remaining completions from the PCIe bus to trickle in, and then reset 2541 * again to clear out any effects they may have had on our device. 2542 */ 2543 hw_dbg(hw, "GIO Primary Disable bit didn't clear - requesting resets\n"); 2544gio_disable_fail: 2545 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2546 2547 if (hw->mac.type >= ixgbe_mac_X550) 2548 return 0; 2549 2550 /* 2551 * Before proceeding, make sure that the PCIe block does not have 2552 * transactions pending. 2553 */ 2554 poll = ixgbe_pcie_timeout_poll(hw); 2555 for (i = 0; i < poll; i++) { 2556 udelay(100); 2557 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 2558 if (ixgbe_removed(hw->hw_addr)) 2559 return 0; 2560 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2561 return 0; 2562 } 2563 2564 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); 2565 return -EALREADY; 2566} 2567 2568/** 2569 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2570 * @hw: pointer to hardware structure 2571 * @mask: Mask to specify which semaphore to acquire 2572 * 2573 * Acquires the SWFW semaphore through the GSSR register for the specified 2574 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2575 **/ 2576int ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2577{ 2578 u32 gssr = 0; 2579 u32 swmask = mask; 2580 u32 fwmask = mask << 5; 2581 u32 timeout = 200; 2582 u32 i; 2583 2584 for (i = 0; i < timeout; i++) { 2585 /* 2586 * SW NVM semaphore bit is used for access to all 2587 * SW_FW_SYNC bits (not just NVM) 2588 */ 2589 if (ixgbe_get_eeprom_semaphore(hw)) 2590 return -EBUSY; 2591 2592 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2593 if (!(gssr & (fwmask | swmask))) { 2594 gssr |= swmask; 2595 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2596 ixgbe_release_eeprom_semaphore(hw); 2597 return 0; 2598 } else { 2599 /* Resource is currently in use by FW or SW */ 2600 ixgbe_release_eeprom_semaphore(hw); 2601 usleep_range(5000, 10000); 2602 } 2603 } 2604 2605 /* If time expired clear the bits holding the lock and retry */ 2606 if (gssr & (fwmask | swmask)) 2607 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 2608 2609 usleep_range(5000, 10000); 2610 return -EBUSY; 2611} 2612 2613/** 2614 * ixgbe_release_swfw_sync - Release SWFW semaphore 2615 * @hw: pointer to hardware structure 2616 * @mask: Mask to specify which semaphore to release 2617 * 2618 * Releases the SWFW semaphore through the GSSR register for the specified 2619 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2620 **/ 2621void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2622{ 2623 u32 gssr; 2624 u32 swmask = mask; 2625 2626 ixgbe_get_eeprom_semaphore(hw); 2627 2628 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2629 gssr &= ~swmask; 2630 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2631 2632 ixgbe_release_eeprom_semaphore(hw); 2633} 2634 2635/** 2636 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 2637 * @hw: pointer to hardware structure 2638 * @reg_val: Value we read from AUTOC 2639 * @locked: bool to indicate whether the SW/FW lock should be taken. Never 2640 * true in this the generic case. 2641 * 2642 * The default case requires no protection so just to the register read. 2643 **/ 2644int prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 2645{ 2646 *locked = false; 2647 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2648 return 0; 2649} 2650 2651/** 2652 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 2653 * @hw: pointer to hardware structure 2654 * @reg_val: value to write to AUTOC 2655 * @locked: bool to indicate whether the SW/FW lock was already taken by 2656 * previous read. 2657 **/ 2658int prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 2659{ 2660 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 2661 return 0; 2662} 2663 2664/** 2665 * ixgbe_disable_rx_buff_generic - Stops the receive data path 2666 * @hw: pointer to hardware structure 2667 * 2668 * Stops the receive data path and waits for the HW to internally 2669 * empty the Rx security block. 2670 **/ 2671int ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) 2672{ 2673#define IXGBE_MAX_SECRX_POLL 40 2674 int i; 2675 int secrxreg; 2676 2677 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2678 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2679 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2680 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2681 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2682 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2683 break; 2684 else 2685 /* Use interrupt-safe sleep just in case */ 2686 udelay(1000); 2687 } 2688 2689 /* For informational purposes only */ 2690 if (i >= IXGBE_MAX_SECRX_POLL) 2691 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); 2692 2693 return 0; 2694 2695} 2696 2697/** 2698 * ixgbe_enable_rx_buff_generic - Enables the receive data path 2699 * @hw: pointer to hardware structure 2700 * 2701 * Enables the receive data path 2702 **/ 2703int ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) 2704{ 2705 u32 secrxreg; 2706 2707 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2708 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2709 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2710 IXGBE_WRITE_FLUSH(hw); 2711 2712 return 0; 2713} 2714 2715/** 2716 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2717 * @hw: pointer to hardware structure 2718 * @regval: register value to write to RXCTRL 2719 * 2720 * Enables the Rx DMA unit 2721 **/ 2722int ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2723{ 2724 if (regval & IXGBE_RXCTRL_RXEN) 2725 hw->mac.ops.enable_rx(hw); 2726 else 2727 hw->mac.ops.disable_rx(hw); 2728 2729 return 0; 2730} 2731 2732/** 2733 * ixgbe_blink_led_start_generic - Blink LED based on index. 2734 * @hw: pointer to hardware structure 2735 * @index: led number to blink 2736 **/ 2737int ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2738{ 2739 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2740 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2741 ixgbe_link_speed speed = 0; 2742 bool link_up = false; 2743 bool locked = false; 2744 int ret_val; 2745 2746 if (index > 3) 2747 return -EINVAL; 2748 2749 /* 2750 * Link must be up to auto-blink the LEDs; 2751 * Force it if link is down. 2752 */ 2753 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2754 2755 if (!link_up) { 2756 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2757 if (ret_val) 2758 return ret_val; 2759 2760 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2761 autoc_reg |= IXGBE_AUTOC_FLU; 2762 2763 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2764 if (ret_val) 2765 return ret_val; 2766 2767 IXGBE_WRITE_FLUSH(hw); 2768 2769 usleep_range(10000, 20000); 2770 } 2771 2772 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2773 led_reg |= IXGBE_LED_BLINK(index); 2774 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2775 IXGBE_WRITE_FLUSH(hw); 2776 2777 return 0; 2778} 2779 2780/** 2781 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2782 * @hw: pointer to hardware structure 2783 * @index: led number to stop blinking 2784 **/ 2785int ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2786{ 2787 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2788 bool locked = false; 2789 u32 autoc_reg = 0; 2790 int ret_val; 2791 2792 if (index > 3) 2793 return -EINVAL; 2794 2795 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2796 if (ret_val) 2797 return ret_val; 2798 2799 autoc_reg &= ~IXGBE_AUTOC_FLU; 2800 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2801 2802 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2803 if (ret_val) 2804 return ret_val; 2805 2806 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2807 led_reg &= ~IXGBE_LED_BLINK(index); 2808 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2809 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2810 IXGBE_WRITE_FLUSH(hw); 2811 2812 return 0; 2813} 2814 2815/** 2816 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2817 * @hw: pointer to hardware structure 2818 * @san_mac_offset: SAN MAC address offset 2819 * 2820 * This function will read the EEPROM location for the SAN MAC address 2821 * pointer, and returns the value at that location. This is used in both 2822 * get and set mac_addr routines. 2823 **/ 2824static int ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2825 u16 *san_mac_offset) 2826{ 2827 int ret_val; 2828 2829 /* 2830 * First read the EEPROM pointer to see if the MAC addresses are 2831 * available. 2832 */ 2833 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 2834 san_mac_offset); 2835 if (ret_val) 2836 hw_err(hw, "eeprom read at offset %d failed\n", 2837 IXGBE_SAN_MAC_ADDR_PTR); 2838 2839 return ret_val; 2840} 2841 2842/** 2843 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2844 * @hw: pointer to hardware structure 2845 * @san_mac_addr: SAN MAC address 2846 * 2847 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2848 * per-port, so set_lan_id() must be called before reading the addresses. 2849 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2850 * upon for non-SFP connections, so we must call it here. 2851 **/ 2852int ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2853{ 2854 u16 san_mac_data, san_mac_offset; 2855 int ret_val; 2856 u8 i; 2857 2858 /* 2859 * First read the EEPROM pointer to see if the MAC addresses are 2860 * available. If they're not, no point in calling set_lan_id() here. 2861 */ 2862 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2863 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 2864 2865 goto san_mac_addr_clr; 2866 2867 /* make sure we know which port we need to program */ 2868 hw->mac.ops.set_lan_id(hw); 2869 /* apply the port offset to the address offset */ 2870 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2871 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2872 for (i = 0; i < 3; i++) { 2873 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 2874 &san_mac_data); 2875 if (ret_val) { 2876 hw_err(hw, "eeprom read at offset %d failed\n", 2877 san_mac_offset); 2878 goto san_mac_addr_clr; 2879 } 2880 san_mac_addr[i * 2] = (u8)(san_mac_data); 2881 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2882 san_mac_offset++; 2883 } 2884 return 0; 2885 2886san_mac_addr_clr: 2887 /* No addresses available in this EEPROM. It's not necessarily an 2888 * error though, so just wipe the local address and return. 2889 */ 2890 for (i = 0; i < 6; i++) 2891 san_mac_addr[i] = 0xFF; 2892 return ret_val; 2893} 2894 2895/** 2896 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2897 * @hw: pointer to hardware structure 2898 * 2899 * Read PCIe configuration space, and get the MSI-X vector count from 2900 * the capabilities table. 2901 **/ 2902u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2903{ 2904 u16 msix_count; 2905 u16 max_msix_count; 2906 u16 pcie_offset; 2907 2908 switch (hw->mac.type) { 2909 case ixgbe_mac_82598EB: 2910 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 2911 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 2912 break; 2913 case ixgbe_mac_82599EB: 2914 case ixgbe_mac_X540: 2915 case ixgbe_mac_X550: 2916 case ixgbe_mac_X550EM_x: 2917 case ixgbe_mac_x550em_a: 2918 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 2919 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 2920 break; 2921 default: 2922 return 1; 2923 } 2924 2925 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); 2926 if (ixgbe_removed(hw->hw_addr)) 2927 msix_count = 0; 2928 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2929 2930 /* MSI-X count is zero-based in HW */ 2931 msix_count++; 2932 2933 if (msix_count > max_msix_count) 2934 msix_count = max_msix_count; 2935 2936 return msix_count; 2937} 2938 2939/** 2940 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2941 * @hw: pointer to hardware struct 2942 * @rar: receive address register index to disassociate 2943 * @vmdq: VMDq pool index to remove from the rar 2944 **/ 2945int ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2946{ 2947 u32 mpsar_lo, mpsar_hi; 2948 u32 rar_entries = hw->mac.num_rar_entries; 2949 2950 /* Make sure we are using a valid rar index range */ 2951 if (rar >= rar_entries) { 2952 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2953 return -EINVAL; 2954 } 2955 2956 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2957 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2958 2959 if (ixgbe_removed(hw->hw_addr)) 2960 return 0; 2961 2962 if (!mpsar_lo && !mpsar_hi) 2963 return 0; 2964 2965 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2966 if (mpsar_lo) { 2967 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2968 mpsar_lo = 0; 2969 } 2970 if (mpsar_hi) { 2971 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2972 mpsar_hi = 0; 2973 } 2974 } else if (vmdq < 32) { 2975 mpsar_lo &= ~BIT(vmdq); 2976 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 2977 } else { 2978 mpsar_hi &= ~BIT(vmdq - 32); 2979 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 2980 } 2981 2982 /* was that the last pool using this rar? */ 2983 if (mpsar_lo == 0 && mpsar_hi == 0 && 2984 rar != 0 && rar != hw->mac.san_mac_rar_index) 2985 hw->mac.ops.clear_rar(hw, rar); 2986 2987 return 0; 2988} 2989 2990/** 2991 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 2992 * @hw: pointer to hardware struct 2993 * @rar: receive address register index to associate with a VMDq index 2994 * @vmdq: VMDq pool index 2995 **/ 2996int ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2997{ 2998 u32 mpsar; 2999 u32 rar_entries = hw->mac.num_rar_entries; 3000 3001 /* Make sure we are using a valid rar index range */ 3002 if (rar >= rar_entries) { 3003 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 3004 return -EINVAL; 3005 } 3006 3007 if (vmdq < 32) { 3008 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3009 mpsar |= BIT(vmdq); 3010 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3011 } else { 3012 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3013 mpsar |= BIT(vmdq - 32); 3014 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3015 } 3016 return 0; 3017} 3018 3019/** 3020 * ixgbe_set_vmdq_san_mac_generic - Associate VMDq pool index with a rx address 3021 * @hw: pointer to hardware struct 3022 * @vmdq: VMDq pool index 3023 * 3024 * This function should only be involved in the IOV mode. 3025 * In IOV mode, Default pool is next pool after the number of 3026 * VFs advertized and not 0. 3027 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3028 **/ 3029int ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3030{ 3031 u32 rar = hw->mac.san_mac_rar_index; 3032 3033 if (vmdq < 32) { 3034 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); 3035 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3036 } else { 3037 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3038 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); 3039 } 3040 3041 return 0; 3042} 3043 3044/** 3045 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3046 * @hw: pointer to hardware structure 3047 **/ 3048int ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3049{ 3050 int i; 3051 3052 for (i = 0; i < 128; i++) 3053 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3054 3055 return 0; 3056} 3057 3058/** 3059 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3060 * @hw: pointer to hardware structure 3061 * @vlan: VLAN id to write to VLAN filter 3062 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if 3063 * vlanid not found 3064 * 3065 * return the VLVF index where this VLAN id should be placed 3066 * 3067 **/ 3068static int ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3069{ 3070 int regindex, first_empty_slot; 3071 u32 bits; 3072 3073 /* short cut the special case */ 3074 if (vlan == 0) 3075 return 0; 3076 3077 /* if vlvf_bypass is set we don't want to use an empty slot, we 3078 * will simply bypass the VLVF if there are no entries present in the 3079 * VLVF that contain our VLAN 3080 */ 3081 first_empty_slot = vlvf_bypass ? -ENOSPC : 0; 3082 3083 /* add VLAN enable bit for comparison */ 3084 vlan |= IXGBE_VLVF_VIEN; 3085 3086 /* Search for the vlan id in the VLVF entries. Save off the first empty 3087 * slot found along the way. 3088 * 3089 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3090 */ 3091 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3092 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3093 if (bits == vlan) 3094 return regindex; 3095 if (!first_empty_slot && !bits) 3096 first_empty_slot = regindex; 3097 } 3098 3099 /* If we are here then we didn't find the VLAN. Return first empty 3100 * slot we found during our search, else error. 3101 */ 3102 if (!first_empty_slot) 3103 hw_dbg(hw, "No space in VLVF.\n"); 3104 3105 return first_empty_slot ? : -ENOSPC; 3106} 3107 3108/** 3109 * ixgbe_set_vfta_generic - Set VLAN filter table 3110 * @hw: pointer to hardware structure 3111 * @vlan: VLAN id to write to VLAN filter 3112 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3113 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3114 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3115 * 3116 * Turn on/off specified VLAN in the VLAN filter table. 3117 **/ 3118int ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3119 bool vlan_on, bool vlvf_bypass) 3120{ 3121 u32 regidx, vfta_delta, vfta, bits; 3122 int vlvf_index; 3123 3124 if ((vlan > 4095) || (vind > 63)) 3125 return -EINVAL; 3126 3127 /* 3128 * this is a 2 part operation - first the VFTA, then the 3129 * VLVF and VLVFB if VT Mode is set 3130 * We don't write the VFTA until we know the VLVF part succeeded. 3131 */ 3132 3133 /* Part 1 3134 * The VFTA is a bitstring made up of 128 32-bit registers 3135 * that enable the particular VLAN id, much like the MTA: 3136 * bits[11-5]: which register 3137 * bits[4-0]: which bit in the register 3138 */ 3139 regidx = vlan / 32; 3140 vfta_delta = BIT(vlan % 32); 3141 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 3142 3143 /* vfta_delta represents the difference between the current value 3144 * of vfta and the value we want in the register. Since the diff 3145 * is an XOR mask we can just update vfta using an XOR. 3146 */ 3147 vfta_delta &= vlan_on ? ~vfta : vfta; 3148 vfta ^= vfta_delta; 3149 3150 /* Part 2 3151 * If VT Mode is set 3152 * Either vlan_on 3153 * make sure the vlan is in VLVF 3154 * set the vind bit in the matching VLVFB 3155 * Or !vlan_on 3156 * clear the pool bit and possibly the vind 3157 */ 3158 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 3159 goto vfta_update; 3160 3161 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 3162 if (vlvf_index < 0) { 3163 if (vlvf_bypass) 3164 goto vfta_update; 3165 return vlvf_index; 3166 } 3167 3168 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 3169 3170 /* set the pool bit */ 3171 bits |= BIT(vind % 32); 3172 if (vlan_on) 3173 goto vlvf_update; 3174 3175 /* clear the pool bit */ 3176 bits ^= BIT(vind % 32); 3177 3178 if (!bits && 3179 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 3180 /* Clear VFTA first, then disable VLVF. Otherwise 3181 * we run the risk of stray packets leaking into 3182 * the PF via the default pool 3183 */ 3184 if (vfta_delta) 3185 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3186 3187 /* disable VLVF and clear remaining bit from pool */ 3188 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3189 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 3190 3191 return 0; 3192 } 3193 3194 /* If there are still bits set in the VLVFB registers 3195 * for the VLAN ID indicated we need to see if the 3196 * caller is requesting that we clear the VFTA entry bit. 3197 * If the caller has requested that we clear the VFTA 3198 * entry bit but there are still pools/VFs using this VLAN 3199 * ID entry then ignore the request. We're not worried 3200 * about the case where we're turning the VFTA VLAN ID 3201 * entry bit on, only when requested to turn it off as 3202 * there may be multiple pools and/or VFs using the 3203 * VLAN ID entry. In that case we cannot clear the 3204 * VFTA bit until all pools/VFs using that VLAN ID have also 3205 * been cleared. This will be indicated by "bits" being 3206 * zero. 3207 */ 3208 vfta_delta = 0; 3209 3210vlvf_update: 3211 /* record pool change and enable VLAN ID if not already enabled */ 3212 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 3213 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 3214 3215vfta_update: 3216 /* Update VFTA now that we are ready for traffic */ 3217 if (vfta_delta) 3218 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3219 3220 return 0; 3221} 3222 3223/** 3224 * ixgbe_clear_vfta_generic - Clear VLAN filter table 3225 * @hw: pointer to hardware structure 3226 * 3227 * Clears the VLAN filter table, and the VMDq index associated with the filter 3228 **/ 3229int ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3230{ 3231 u32 offset; 3232 3233 for (offset = 0; offset < hw->mac.vft_size; offset++) 3234 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3235 3236 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3237 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3238 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 3239 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 3240 } 3241 3242 return 0; 3243} 3244 3245/** 3246 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 3247 * @hw: pointer to hardware structure 3248 * 3249 * Contains the logic to identify if we need to verify link for the 3250 * crosstalk fix 3251 **/ 3252static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 3253{ 3254 /* Does FW say we need the fix */ 3255 if (!hw->need_crosstalk_fix) 3256 return false; 3257 3258 /* Only consider SFP+ PHYs i.e. media type fiber */ 3259 switch (hw->mac.ops.get_media_type(hw)) { 3260 case ixgbe_media_type_fiber: 3261 case ixgbe_media_type_fiber_qsfp: 3262 break; 3263 default: 3264 return false; 3265 } 3266 3267 return true; 3268} 3269 3270/** 3271 * ixgbe_check_mac_link_generic - Determine link and speed status 3272 * @hw: pointer to hardware structure 3273 * @speed: pointer to link speed 3274 * @link_up: true when link is up 3275 * @link_up_wait_to_complete: bool used to wait for link up or not 3276 * 3277 * Reads the links register to determine if link is up and the current speed 3278 **/ 3279int ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3280 bool *link_up, bool link_up_wait_to_complete) 3281{ 3282 bool crosstalk_fix_active = ixgbe_need_crosstalk_fix(hw); 3283 u32 links_reg, links_orig; 3284 u32 i; 3285 3286 /* If Crosstalk fix enabled do the sanity check of making sure 3287 * the SFP+ cage is full. 3288 */ 3289 if (crosstalk_fix_active) { 3290 u32 sfp_cage_full; 3291 3292 switch (hw->mac.type) { 3293 case ixgbe_mac_82599EB: 3294 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3295 IXGBE_ESDP_SDP2; 3296 break; 3297 case ixgbe_mac_X550EM_x: 3298 case ixgbe_mac_x550em_a: 3299 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3300 IXGBE_ESDP_SDP0; 3301 break; 3302 default: 3303 /* sanity check - No SFP+ devices here */ 3304 sfp_cage_full = false; 3305 break; 3306 } 3307 3308 if (!sfp_cage_full) { 3309 *link_up = false; 3310 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3311 return 0; 3312 } 3313 } 3314 3315 /* clear the old state */ 3316 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 3317 3318 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3319 3320 if (links_orig != links_reg) { 3321 hw_dbg(hw, "LINKS changed from %08X to %08X\n", 3322 links_orig, links_reg); 3323 } 3324 3325 if (link_up_wait_to_complete) { 3326 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3327 if (links_reg & IXGBE_LINKS_UP) { 3328 *link_up = true; 3329 break; 3330 } else { 3331 *link_up = false; 3332 } 3333 msleep(100); 3334 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3335 } 3336 } else { 3337 if (links_reg & IXGBE_LINKS_UP) { 3338 if (crosstalk_fix_active) { 3339 /* Check the link state again after a delay 3340 * to filter out spurious link up 3341 * notifications. 3342 */ 3343 mdelay(5); 3344 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3345 if (!(links_reg & IXGBE_LINKS_UP)) { 3346 *link_up = false; 3347 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3348 return 0; 3349 } 3350 } 3351 *link_up = true; 3352 } else { 3353 *link_up = false; 3354 } 3355 } 3356 3357 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3358 case IXGBE_LINKS_SPEED_10G_82599: 3359 if ((hw->mac.type >= ixgbe_mac_X550) && 3360 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3361 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 3362 else 3363 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3364 break; 3365 case IXGBE_LINKS_SPEED_1G_82599: 3366 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3367 break; 3368 case IXGBE_LINKS_SPEED_100_82599: 3369 if ((hw->mac.type >= ixgbe_mac_X550) && 3370 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3371 *speed = IXGBE_LINK_SPEED_5GB_FULL; 3372 else 3373 *speed = IXGBE_LINK_SPEED_100_FULL; 3374 break; 3375 case IXGBE_LINKS_SPEED_10_X550EM_A: 3376 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3377 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3378 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { 3379 *speed = IXGBE_LINK_SPEED_10_FULL; 3380 } 3381 break; 3382 default: 3383 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3384 } 3385 3386 return 0; 3387} 3388 3389/** 3390 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 3391 * the EEPROM 3392 * @hw: pointer to hardware structure 3393 * @wwnn_prefix: the alternative WWNN prefix 3394 * @wwpn_prefix: the alternative WWPN prefix 3395 * 3396 * This function will read the EEPROM from the alternative SAN MAC address 3397 * block to check the support for the alternative WWNN/WWPN prefix support. 3398 **/ 3399int ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3400 u16 *wwpn_prefix) 3401{ 3402 u16 offset, caps; 3403 u16 alt_san_mac_blk_offset; 3404 3405 /* clear output first */ 3406 *wwnn_prefix = 0xFFFF; 3407 *wwpn_prefix = 0xFFFF; 3408 3409 /* check if alternative SAN MAC is supported */ 3410 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 3411 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 3412 goto wwn_prefix_err; 3413 3414 if ((alt_san_mac_blk_offset == 0) || 3415 (alt_san_mac_blk_offset == 0xFFFF)) 3416 return 0; 3417 3418 /* check capability in alternative san mac address block */ 3419 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3420 if (hw->eeprom.ops.read(hw, offset, &caps)) 3421 goto wwn_prefix_err; 3422 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3423 return 0; 3424 3425 /* get the corresponding prefix for WWNN/WWPN */ 3426 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3427 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) 3428 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3429 3430 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3431 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 3432 goto wwn_prefix_err; 3433 3434 return 0; 3435 3436wwn_prefix_err: 3437 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3438 return 0; 3439} 3440 3441/** 3442 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3443 * @hw: pointer to hardware structure 3444 * @enable: enable or disable switch for MAC anti-spoofing 3445 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 3446 * 3447 **/ 3448void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3449{ 3450 int vf_target_reg = vf >> 3; 3451 int vf_target_shift = vf % 8; 3452 u32 pfvfspoof; 3453 3454 if (hw->mac.type == ixgbe_mac_82598EB) 3455 return; 3456 3457 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3458 if (enable) 3459 pfvfspoof |= BIT(vf_target_shift); 3460 else 3461 pfvfspoof &= ~BIT(vf_target_shift); 3462 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3463} 3464 3465/** 3466 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 3467 * @hw: pointer to hardware structure 3468 * @enable: enable or disable switch for VLAN anti-spoofing 3469 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 3470 * 3471 **/ 3472void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3473{ 3474 int vf_target_reg = vf >> 3; 3475 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 3476 u32 pfvfspoof; 3477 3478 if (hw->mac.type == ixgbe_mac_82598EB) 3479 return; 3480 3481 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3482 if (enable) 3483 pfvfspoof |= BIT(vf_target_shift); 3484 else 3485 pfvfspoof &= ~BIT(vf_target_shift); 3486 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3487} 3488 3489/** 3490 * ixgbe_get_device_caps_generic - Get additional device capabilities 3491 * @hw: pointer to hardware structure 3492 * @device_caps: the EEPROM word with the extra device capabilities 3493 * 3494 * This function will read the EEPROM location for the device capabilities, 3495 * and return the word through device_caps. 3496 **/ 3497int ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3498{ 3499 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3500 3501 return 0; 3502} 3503 3504/** 3505 * ixgbe_set_rxpba_generic - Initialize RX packet buffer 3506 * @hw: pointer to hardware structure 3507 * @num_pb: number of packet buffers to allocate 3508 * @headroom: reserve n KB of headroom 3509 * @strategy: packet buffer allocation strategy 3510 **/ 3511void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, 3512 int num_pb, 3513 u32 headroom, 3514 int strategy) 3515{ 3516 u32 pbsize = hw->mac.rx_pb_size; 3517 int i = 0; 3518 u32 rxpktsize, txpktsize, txpbthresh; 3519 3520 /* Reserve headroom */ 3521 pbsize -= headroom; 3522 3523 if (!num_pb) 3524 num_pb = 1; 3525 3526 /* Divide remaining packet buffer space amongst the number 3527 * of packet buffers requested using supplied strategy. 3528 */ 3529 switch (strategy) { 3530 case (PBA_STRATEGY_WEIGHTED): 3531 /* pba_80_48 strategy weight first half of packet buffer with 3532 * 5/8 of the packet buffer space. 3533 */ 3534 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8)); 3535 pbsize -= rxpktsize * (num_pb / 2); 3536 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 3537 for (; i < (num_pb / 2); i++) 3538 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3539 fallthrough; /* configure remaining packet buffers */ 3540 case (PBA_STRATEGY_EQUAL): 3541 /* Divide the remaining Rx packet buffer evenly among the TCs */ 3542 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 3543 for (; i < num_pb; i++) 3544 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3545 break; 3546 default: 3547 break; 3548 } 3549 3550 /* 3551 * Setup Tx packet buffer and threshold equally for all TCs 3552 * TXPBTHRESH register is set in K so divide by 1024 and subtract 3553 * 10 since the largest packet we support is just over 9K. 3554 */ 3555 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 3556 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 3557 for (i = 0; i < num_pb; i++) { 3558 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 3559 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 3560 } 3561 3562 /* Clear unused TCs, if any, to zero buffer size*/ 3563 for (; i < IXGBE_MAX_PB; i++) { 3564 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 3565 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 3566 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 3567 } 3568} 3569 3570/** 3571 * ixgbe_calculate_checksum - Calculate checksum for buffer 3572 * @buffer: pointer to EEPROM 3573 * @length: size of EEPROM to calculate a checksum for 3574 * 3575 * Calculates the checksum for some buffer on a specified length. The 3576 * checksum calculated is returned. 3577 **/ 3578u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 3579{ 3580 u32 i; 3581 u8 sum = 0; 3582 3583 if (!buffer) 3584 return 0; 3585 3586 for (i = 0; i < length; i++) 3587 sum += buffer[i]; 3588 3589 return (u8) (0 - sum); 3590} 3591 3592/** 3593 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 3594 * @hw: pointer to the HW structure 3595 * @buffer: command to write and where the return status will be placed 3596 * @length: length of buffer, must be multiple of 4 bytes 3597 * @timeout: time in ms to wait for command completion 3598 * 3599 * Communicates with the manageability block. On success return 0 3600 * else returns semaphore error when encountering an error acquiring 3601 * semaphore, -EINVAL when incorrect parameters passed or -EIO when 3602 * command fails. 3603 * 3604 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 3605 * by the caller. 3606 **/ 3607int ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 3608 u32 timeout) 3609{ 3610 u32 hicr, i, fwsts; 3611 u16 dword_len; 3612 3613 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3614 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3615 return -EINVAL; 3616 } 3617 3618 /* Set bit 9 of FWSTS clearing FW reset indication */ 3619 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 3620 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 3621 3622 /* Check that the host interface is enabled. */ 3623 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3624 if (!(hicr & IXGBE_HICR_EN)) { 3625 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); 3626 return -EIO; 3627 } 3628 3629 /* Calculate length in DWORDs. We must be DWORD aligned */ 3630 if (length % sizeof(u32)) { 3631 hw_dbg(hw, "Buffer length failure, not aligned to dword"); 3632 return -EINVAL; 3633 } 3634 3635 dword_len = length >> 2; 3636 3637 /* The device driver writes the relevant command block 3638 * into the ram area. 3639 */ 3640 for (i = 0; i < dword_len; i++) 3641 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3642 i, (__force u32)cpu_to_le32(buffer[i])); 3643 3644 /* Setting this bit tells the ARC that a new command is pending. */ 3645 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 3646 3647 for (i = 0; i < timeout; i++) { 3648 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3649 if (!(hicr & IXGBE_HICR_C)) 3650 break; 3651 usleep_range(1000, 2000); 3652 } 3653 3654 /* Check command successful completion. */ 3655 if ((timeout && i == timeout) || 3656 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) 3657 return -EIO; 3658 3659 return 0; 3660} 3661 3662/** 3663 * ixgbe_host_interface_command - Issue command to manageability block 3664 * @hw: pointer to the HW structure 3665 * @buffer: contains the command to write and where the return status will 3666 * be placed 3667 * @length: length of buffer, must be multiple of 4 bytes 3668 * @timeout: time in ms to wait for command completion 3669 * @return_data: read and return data from the buffer (true) or not (false) 3670 * Needed because FW structures are big endian and decoding of 3671 * these fields can be 8 bit or 16 bit based on command. Decoding 3672 * is not easily understood without making a table of commands. 3673 * So we will leave this up to the caller to read back the data 3674 * in these cases. 3675 * 3676 * Communicates with the manageability block. On success return 0 3677 * else return -EIO or -EINVAL. 3678 **/ 3679int ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer, 3680 u32 length, u32 timeout, 3681 bool return_data) 3682{ 3683 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 3684 struct ixgbe_hic_hdr *hdr = buffer; 3685 u16 buf_len, dword_len; 3686 u32 *u32arr = buffer; 3687 int status; 3688 u32 bi; 3689 3690 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3691 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3692 return -EINVAL; 3693 } 3694 /* Take management host interface semaphore */ 3695 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3696 if (status) 3697 return status; 3698 3699 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 3700 if (status) 3701 goto rel_out; 3702 3703 if (!return_data) 3704 goto rel_out; 3705 3706 /* Calculate length in DWORDs */ 3707 dword_len = hdr_size >> 2; 3708 3709 /* first pull in the header so we know the buffer length */ 3710 for (bi = 0; bi < dword_len; bi++) { 3711 u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3712 le32_to_cpus(&u32arr[bi]); 3713 } 3714 3715 /* If there is any thing in data position pull it in */ 3716 buf_len = hdr->buf_len; 3717 if (!buf_len) 3718 goto rel_out; 3719 3720 if (length < round_up(buf_len, 4) + hdr_size) { 3721 hw_dbg(hw, "Buffer not large enough for reply message.\n"); 3722 status = -EIO; 3723 goto rel_out; 3724 } 3725 3726 /* Calculate length in DWORDs, add 3 for odd lengths */ 3727 dword_len = (buf_len + 3) >> 2; 3728 3729 /* Pull in the rest of the buffer (bi is where we left off) */ 3730 for (; bi <= dword_len; bi++) { 3731 u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3732 le32_to_cpus(&u32arr[bi]); 3733 } 3734 3735rel_out: 3736 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3737 3738 return status; 3739} 3740 3741/** 3742 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 3743 * @hw: pointer to the HW structure 3744 * @maj: driver version major number 3745 * @min: driver version minor number 3746 * @build: driver version build number 3747 * @sub: driver version sub build number 3748 * @len: length of driver_ver string 3749 * @driver_ver: driver string 3750 * 3751 * Sends driver version number to firmware through the manageability 3752 * block. On success return 0 3753 * else returns -EBUSY when encountering an error acquiring 3754 * semaphore or -EIO when command fails. 3755 **/ 3756int ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 3757 u8 build, u8 sub, __always_unused u16 len, 3758 __always_unused const char *driver_ver) 3759{ 3760 struct ixgbe_hic_drv_info fw_cmd; 3761 int ret_val; 3762 int i; 3763 3764 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 3765 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 3766 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 3767 fw_cmd.port_num = hw->bus.func; 3768 fw_cmd.ver_maj = maj; 3769 fw_cmd.ver_min = min; 3770 fw_cmd.ver_build = build; 3771 fw_cmd.ver_sub = sub; 3772 fw_cmd.hdr.checksum = 0; 3773 fw_cmd.pad = 0; 3774 fw_cmd.pad2 = 0; 3775 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 3776 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 3777 3778 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 3779 ret_val = ixgbe_host_interface_command(hw, &fw_cmd, 3780 sizeof(fw_cmd), 3781 IXGBE_HI_COMMAND_TIMEOUT, 3782 true); 3783 if (ret_val != 0) 3784 continue; 3785 3786 if (fw_cmd.hdr.cmd_or_resp.ret_status == 3787 FW_CEM_RESP_STATUS_SUCCESS) 3788 ret_val = 0; 3789 else 3790 ret_val = -EIO; 3791 3792 break; 3793 } 3794 3795 return ret_val; 3796} 3797 3798/** 3799 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 3800 * @hw: pointer to the hardware structure 3801 * 3802 * The 82599 and x540 MACs can experience issues if TX work is still pending 3803 * when a reset occurs. This function prevents this by flushing the PCIe 3804 * buffers on the system. 3805 **/ 3806void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 3807{ 3808 u32 gcr_ext, hlreg0, i, poll; 3809 u16 value; 3810 3811 /* 3812 * If double reset is not requested then all transactions should 3813 * already be clear and as such there is no work to do 3814 */ 3815 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 3816 return; 3817 3818 /* 3819 * Set loopback enable to prevent any transmits from being sent 3820 * should the link come up. This assumes that the RXCTRL.RXEN bit 3821 * has already been cleared. 3822 */ 3823 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3824 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 3825 3826 /* wait for a last completion before clearing buffers */ 3827 IXGBE_WRITE_FLUSH(hw); 3828 usleep_range(3000, 6000); 3829 3830 /* Before proceeding, make sure that the PCIe block does not have 3831 * transactions pending. 3832 */ 3833 poll = ixgbe_pcie_timeout_poll(hw); 3834 for (i = 0; i < poll; i++) { 3835 usleep_range(100, 200); 3836 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 3837 if (ixgbe_removed(hw->hw_addr)) 3838 break; 3839 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3840 break; 3841 } 3842 3843 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 3844 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 3845 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 3846 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 3847 3848 /* Flush all writes and allow 20usec for all transactions to clear */ 3849 IXGBE_WRITE_FLUSH(hw); 3850 udelay(20); 3851 3852 /* restore previous register values */ 3853 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3854 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3855} 3856 3857static const u8 ixgbe_emc_temp_data[4] = { 3858 IXGBE_EMC_INTERNAL_DATA, 3859 IXGBE_EMC_DIODE1_DATA, 3860 IXGBE_EMC_DIODE2_DATA, 3861 IXGBE_EMC_DIODE3_DATA 3862}; 3863static const u8 ixgbe_emc_therm_limit[4] = { 3864 IXGBE_EMC_INTERNAL_THERM_LIMIT, 3865 IXGBE_EMC_DIODE1_THERM_LIMIT, 3866 IXGBE_EMC_DIODE2_THERM_LIMIT, 3867 IXGBE_EMC_DIODE3_THERM_LIMIT 3868}; 3869 3870/** 3871 * ixgbe_get_ets_data - Extracts the ETS bit data 3872 * @hw: pointer to hardware structure 3873 * @ets_cfg: extected ETS data 3874 * @ets_offset: offset of ETS data 3875 * 3876 * Returns error code. 3877 **/ 3878static int ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, 3879 u16 *ets_offset) 3880{ 3881 int status; 3882 3883 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); 3884 if (status) 3885 return status; 3886 3887 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) 3888 return -EOPNOTSUPP; 3889 3890 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); 3891 if (status) 3892 return status; 3893 3894 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) 3895 return -EOPNOTSUPP; 3896 3897 return 0; 3898} 3899 3900/** 3901 * ixgbe_get_thermal_sensor_data_generic - Gathers thermal sensor data 3902 * @hw: pointer to hardware structure 3903 * 3904 * Returns the thermal sensor data structure 3905 **/ 3906int ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 3907{ 3908 u16 ets_offset; 3909 u16 ets_sensor; 3910 u8 num_sensors; 3911 u16 ets_cfg; 3912 int status; 3913 u8 i; 3914 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3915 3916 /* Only support thermal sensors attached to physical port 0 */ 3917 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3918 return -EOPNOTSUPP; 3919 3920 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3921 if (status) 3922 return status; 3923 3924 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3925 if (num_sensors > IXGBE_MAX_SENSORS) 3926 num_sensors = IXGBE_MAX_SENSORS; 3927 3928 for (i = 0; i < num_sensors; i++) { 3929 u8 sensor_index; 3930 u8 sensor_location; 3931 3932 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 3933 &ets_sensor); 3934 if (status) 3935 return status; 3936 3937 sensor_index = FIELD_GET(IXGBE_ETS_DATA_INDEX_MASK, 3938 ets_sensor); 3939 sensor_location = FIELD_GET(IXGBE_ETS_DATA_LOC_MASK, 3940 ets_sensor); 3941 3942 if (sensor_location != 0) { 3943 status = hw->phy.ops.read_i2c_byte(hw, 3944 ixgbe_emc_temp_data[sensor_index], 3945 IXGBE_I2C_THERMAL_SENSOR_ADDR, 3946 &data->sensor[i].temp); 3947 if (status) 3948 return status; 3949 } 3950 } 3951 3952 return 0; 3953} 3954 3955/** 3956 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 3957 * @hw: pointer to hardware structure 3958 * 3959 * Inits the thermal sensor thresholds according to the NVM map 3960 * and save off the threshold and location values into mac.thermal_sensor_data 3961 **/ 3962int ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 3963{ 3964 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3965 u8 low_thresh_delta; 3966 u8 num_sensors; 3967 u8 therm_limit; 3968 u16 ets_sensor; 3969 u16 ets_offset; 3970 u16 ets_cfg; 3971 int status; 3972 u8 i; 3973 3974 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 3975 3976 /* Only support thermal sensors attached to physical port 0 */ 3977 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3978 return -EOPNOTSUPP; 3979 3980 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3981 if (status) 3982 return status; 3983 3984 low_thresh_delta = FIELD_GET(IXGBE_ETS_LTHRES_DELTA_MASK, ets_cfg); 3985 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3986 if (num_sensors > IXGBE_MAX_SENSORS) 3987 num_sensors = IXGBE_MAX_SENSORS; 3988 3989 for (i = 0; i < num_sensors; i++) { 3990 u8 sensor_index; 3991 u8 sensor_location; 3992 3993 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { 3994 hw_err(hw, "eeprom read at offset %d failed\n", 3995 ets_offset + 1 + i); 3996 continue; 3997 } 3998 sensor_index = FIELD_GET(IXGBE_ETS_DATA_INDEX_MASK, 3999 ets_sensor); 4000 sensor_location = FIELD_GET(IXGBE_ETS_DATA_LOC_MASK, 4001 ets_sensor); 4002 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 4003 4004 hw->phy.ops.write_i2c_byte(hw, 4005 ixgbe_emc_therm_limit[sensor_index], 4006 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 4007 4008 if (sensor_location == 0) 4009 continue; 4010 4011 data->sensor[i].location = sensor_location; 4012 data->sensor[i].caution_thresh = therm_limit; 4013 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta; 4014 } 4015 4016 return 0; 4017} 4018 4019/** 4020 * ixgbe_get_orom_version - Return option ROM from EEPROM 4021 * 4022 * @hw: pointer to hardware structure 4023 * @nvm_ver: pointer to output structure 4024 * 4025 * if valid option ROM version, nvm_ver->or_valid set to true 4026 * else nvm_ver->or_valid is false. 4027 **/ 4028void ixgbe_get_orom_version(struct ixgbe_hw *hw, 4029 struct ixgbe_nvm_version *nvm_ver) 4030{ 4031 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; 4032 4033 nvm_ver->or_valid = false; 4034 /* Option Rom may or may not be present. Start with pointer */ 4035 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); 4036 4037 /* make sure offset is valid */ 4038 if (offset == 0x0 || offset == NVM_INVALID_PTR) 4039 return; 4040 4041 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); 4042 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); 4043 4044 /* option rom exists and is valid */ 4045 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || 4046 eeprom_cfg_blkl == NVM_VER_INVALID || 4047 eeprom_cfg_blkh == NVM_VER_INVALID) 4048 return; 4049 4050 nvm_ver->or_valid = true; 4051 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; 4052 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | 4053 (eeprom_cfg_blkh >> NVM_OROM_SHIFT); 4054 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; 4055} 4056 4057/** 4058 * ixgbe_get_oem_prod_version - Etrack ID from EEPROM 4059 * @hw: pointer to hardware structure 4060 * @nvm_ver: pointer to output structure 4061 * 4062 * if valid OEM product version, nvm_ver->oem_valid set to true 4063 * else nvm_ver->oem_valid is false. 4064 **/ 4065void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, 4066 struct ixgbe_nvm_version *nvm_ver) 4067{ 4068 u16 rel_num, prod_ver, mod_len, cap, offset; 4069 4070 nvm_ver->oem_valid = false; 4071 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); 4072 4073 /* Return is offset to OEM Product Version block is invalid */ 4074 if (offset == 0x0 || offset == NVM_INVALID_PTR) 4075 return; 4076 4077 /* Read product version block */ 4078 hw->eeprom.ops.read(hw, offset, &mod_len); 4079 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); 4080 4081 /* Return if OEM product version block is invalid */ 4082 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || 4083 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) 4084 return; 4085 4086 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); 4087 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); 4088 4089 /* Return if version is invalid */ 4090 if ((rel_num | prod_ver) == 0x0 || 4091 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) 4092 return; 4093 4094 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; 4095 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; 4096 nvm_ver->oem_release = rel_num; 4097 nvm_ver->oem_valid = true; 4098} 4099 4100/** 4101 * ixgbe_get_etk_id - Return Etrack ID from EEPROM 4102 * 4103 * @hw: pointer to hardware structure 4104 * @nvm_ver: pointer to output structure 4105 * 4106 * word read errors will return 0xFFFF 4107 **/ 4108void ixgbe_get_etk_id(struct ixgbe_hw *hw, 4109 struct ixgbe_nvm_version *nvm_ver) 4110{ 4111 u16 etk_id_l, etk_id_h; 4112 4113 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) 4114 etk_id_l = NVM_VER_INVALID; 4115 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) 4116 etk_id_h = NVM_VER_INVALID; 4117 4118 /* The word order for the version format is determined by high order 4119 * word bit 15. 4120 */ 4121 if ((etk_id_h & NVM_ETK_VALID) == 0) { 4122 nvm_ver->etk_id = etk_id_h; 4123 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT); 4124 } else { 4125 nvm_ver->etk_id = etk_id_l; 4126 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT); 4127 } 4128} 4129 4130void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 4131{ 4132 u32 rxctrl; 4133 4134 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4135 if (rxctrl & IXGBE_RXCTRL_RXEN) { 4136 if (hw->mac.type != ixgbe_mac_82598EB) { 4137 u32 pfdtxgswc; 4138 4139 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4140 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 4141 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 4142 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4143 hw->mac.set_lben = true; 4144 } else { 4145 hw->mac.set_lben = false; 4146 } 4147 } 4148 rxctrl &= ~IXGBE_RXCTRL_RXEN; 4149 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 4150 } 4151} 4152 4153void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 4154{ 4155 u32 rxctrl; 4156 4157 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4158 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 4159 4160 if (hw->mac.type != ixgbe_mac_82598EB) { 4161 if (hw->mac.set_lben) { 4162 u32 pfdtxgswc; 4163 4164 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4165 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 4166 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4167 hw->mac.set_lben = false; 4168 } 4169 } 4170} 4171 4172/** ixgbe_mng_present - returns true when management capability is present 4173 * @hw: pointer to hardware structure 4174 **/ 4175bool ixgbe_mng_present(struct ixgbe_hw *hw) 4176{ 4177 u32 fwsm; 4178 4179 if (hw->mac.type < ixgbe_mac_82599EB) 4180 return false; 4181 4182 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 4183 4184 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 4185} 4186 4187/** 4188 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 4189 * @hw: pointer to hardware structure 4190 * @speed: new link speed 4191 * @autoneg_wait_to_complete: true when waiting for completion is needed 4192 * 4193 * Set the link speed in the MAC and/or PHY register and restarts link. 4194 */ 4195int ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 4196 ixgbe_link_speed speed, 4197 bool autoneg_wait_to_complete) 4198{ 4199 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4200 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4201 bool autoneg, link_up = false; 4202 u32 speedcnt = 0; 4203 int status = 0; 4204 u32 i = 0; 4205 4206 /* Mask off requested but non-supported speeds */ 4207 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); 4208 if (status) 4209 return status; 4210 4211 speed &= link_speed; 4212 4213 /* Try each speed one by one, highest priority first. We do this in 4214 * software because 10Gb fiber doesn't support speed autonegotiation. 4215 */ 4216 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 4217 speedcnt++; 4218 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 4219 4220 /* Set the module link speed */ 4221 switch (hw->phy.media_type) { 4222 case ixgbe_media_type_fiber: 4223 hw->mac.ops.set_rate_select_speed(hw, 4224 IXGBE_LINK_SPEED_10GB_FULL); 4225 break; 4226 case ixgbe_media_type_fiber_qsfp: 4227 /* QSFP module automatically detects MAC link speed */ 4228 break; 4229 default: 4230 hw_dbg(hw, "Unexpected media type\n"); 4231 break; 4232 } 4233 4234 /* Allow module to change analog characteristics (1G->10G) */ 4235 msleep(40); 4236 4237 status = hw->mac.ops.setup_mac_link(hw, 4238 IXGBE_LINK_SPEED_10GB_FULL, 4239 autoneg_wait_to_complete); 4240 if (status) 4241 return status; 4242 4243 /* Flap the Tx laser if it has not already been done */ 4244 if (hw->mac.ops.flap_tx_laser) 4245 hw->mac.ops.flap_tx_laser(hw); 4246 4247 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 4248 * Section 73.10.2, we may have to wait up to 500ms if KR is 4249 * attempted. 82599 uses the same timing for 10g SFI. 4250 */ 4251 for (i = 0; i < 5; i++) { 4252 /* Wait for the link partner to also set speed */ 4253 msleep(100); 4254 4255 /* If we have link, just jump out */ 4256 status = hw->mac.ops.check_link(hw, &link_speed, 4257 &link_up, false); 4258 if (status) 4259 return status; 4260 4261 if (link_up) 4262 goto out; 4263 } 4264 } 4265 4266 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 4267 speedcnt++; 4268 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 4269 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 4270 4271 /* Set the module link speed */ 4272 switch (hw->phy.media_type) { 4273 case ixgbe_media_type_fiber: 4274 hw->mac.ops.set_rate_select_speed(hw, 4275 IXGBE_LINK_SPEED_1GB_FULL); 4276 break; 4277 case ixgbe_media_type_fiber_qsfp: 4278 /* QSFP module automatically detects link speed */ 4279 break; 4280 default: 4281 hw_dbg(hw, "Unexpected media type\n"); 4282 break; 4283 } 4284 4285 /* Allow module to change analog characteristics (10G->1G) */ 4286 msleep(40); 4287 4288 status = hw->mac.ops.setup_mac_link(hw, 4289 IXGBE_LINK_SPEED_1GB_FULL, 4290 autoneg_wait_to_complete); 4291 if (status) 4292 return status; 4293 4294 /* Flap the Tx laser if it has not already been done */ 4295 if (hw->mac.ops.flap_tx_laser) 4296 hw->mac.ops.flap_tx_laser(hw); 4297 4298 /* Wait for the link partner to also set speed */ 4299 msleep(100); 4300 4301 /* If we have link, just jump out */ 4302 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4303 false); 4304 if (status) 4305 return status; 4306 4307 if (link_up) 4308 goto out; 4309 } 4310 4311 /* We didn't get link. Configure back to the highest speed we tried, 4312 * (if there was more than one). We call ourselves back with just the 4313 * single highest speed that the user requested. 4314 */ 4315 if (speedcnt > 1) 4316 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 4317 highest_link_speed, 4318 autoneg_wait_to_complete); 4319 4320out: 4321 /* Set autoneg_advertised value based on input link speed */ 4322 hw->phy.autoneg_advertised = 0; 4323 4324 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4325 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 4326 4327 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 4328 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 4329 4330 return status; 4331} 4332 4333/** 4334 * ixgbe_set_soft_rate_select_speed - Set module link speed 4335 * @hw: pointer to hardware structure 4336 * @speed: link speed to set 4337 * 4338 * Set module link speed via the soft rate select. 4339 */ 4340void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 4341 ixgbe_link_speed speed) 4342{ 4343 u8 rs, eeprom_data; 4344 int status; 4345 4346 switch (speed) { 4347 case IXGBE_LINK_SPEED_10GB_FULL: 4348 /* one bit mask same as setting on */ 4349 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 4350 break; 4351 case IXGBE_LINK_SPEED_1GB_FULL: 4352 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 4353 break; 4354 default: 4355 hw_dbg(hw, "Invalid fixed module speed\n"); 4356 return; 4357 } 4358 4359 /* Set RS0 */ 4360 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4361 IXGBE_I2C_EEPROM_DEV_ADDR2, 4362 &eeprom_data); 4363 if (status) { 4364 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); 4365 return; 4366 } 4367 4368 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4369 4370 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4371 IXGBE_I2C_EEPROM_DEV_ADDR2, 4372 eeprom_data); 4373 if (status) { 4374 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); 4375 return; 4376 } 4377 4378 /* Set RS1 */ 4379 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4380 IXGBE_I2C_EEPROM_DEV_ADDR2, 4381 &eeprom_data); 4382 if (status) { 4383 hw_dbg(hw, "Failed to read Rx Rate Select RS1\n"); 4384 return; 4385 } 4386 4387 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4388 4389 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4390 IXGBE_I2C_EEPROM_DEV_ADDR2, 4391 eeprom_data); 4392 if (status) { 4393 hw_dbg(hw, "Failed to write Rx Rate Select RS1\n"); 4394 return; 4395 } 4396} 4397