1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (C) 2018-2021, Intel Corporation. */ 3 4#ifndef _ICE_PTP_CONSTS_H_ 5#define _ICE_PTP_CONSTS_H_ 6 7/* Constant definitions related to the hardware clock used for PTP 1588 8 * features and functionality. 9 */ 10/* Constants defined for the PTP 1588 clock hardware. */ 11 12/* struct ice_time_ref_info_e82x 13 * 14 * E822 hardware can use different sources as the reference for the PTP 15 * hardware clock. Each clock has different characteristics such as a slightly 16 * different frequency, etc. 17 * 18 * This lookup table defines several constants that depend on the current time 19 * reference. See the struct ice_time_ref_info_e82x for information about the 20 * meaning of each constant. 21 */ 22const struct ice_time_ref_info_e82x e822_time_ref[NUM_ICE_TIME_REF_FREQ] = { 23 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */ 24 { 25 /* pll_freq */ 26 823437500, /* 823.4375 MHz PLL */ 27 /* nominal_incval */ 28 0x136e44fabULL, 29 /* pps_delay */ 30 11, 31 }, 32 33 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */ 34 { 35 /* pll_freq */ 36 783360000, /* 783.36 MHz */ 37 /* nominal_incval */ 38 0x146cc2177ULL, 39 /* pps_delay */ 40 12, 41 }, 42 43 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */ 44 { 45 /* pll_freq */ 46 796875000, /* 796.875 MHz */ 47 /* nominal_incval */ 48 0x141414141ULL, 49 /* pps_delay */ 50 12, 51 }, 52 53 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */ 54 { 55 /* pll_freq */ 56 816000000, /* 816 MHz */ 57 /* nominal_incval */ 58 0x139b9b9baULL, 59 /* pps_delay */ 60 12, 61 }, 62 63 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */ 64 { 65 /* pll_freq */ 66 830078125, /* 830.78125 MHz */ 67 /* nominal_incval */ 68 0x134679aceULL, 69 /* pps_delay */ 70 11, 71 }, 72 73 /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */ 74 { 75 /* pll_freq */ 76 783360000, /* 783.36 MHz */ 77 /* nominal_incval */ 78 0x146cc2177ULL, 79 /* pps_delay */ 80 12, 81 }, 82}; 83 84const struct ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = { 85 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */ 86 { 87 /* refclk_pre_div */ 88 1, 89 /* feedback_div */ 90 197, 91 /* frac_n_div */ 92 2621440, 93 /* post_pll_div */ 94 6, 95 }, 96 97 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */ 98 { 99 /* refclk_pre_div */ 100 5, 101 /* feedback_div */ 102 223, 103 /* frac_n_div */ 104 524288, 105 /* post_pll_div */ 106 7, 107 }, 108 109 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */ 110 { 111 /* refclk_pre_div */ 112 5, 113 /* feedback_div */ 114 223, 115 /* frac_n_div */ 116 524288, 117 /* post_pll_div */ 118 7, 119 }, 120 121 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */ 122 { 123 /* refclk_pre_div */ 124 5, 125 /* feedback_div */ 126 159, 127 /* frac_n_div */ 128 1572864, 129 /* post_pll_div */ 130 6, 131 }, 132 133 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */ 134 { 135 /* refclk_pre_div */ 136 5, 137 /* feedback_div */ 138 159, 139 /* frac_n_div */ 140 1572864, 141 /* post_pll_div */ 142 6, 143 }, 144 145 /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */ 146 { 147 /* refclk_pre_div */ 148 10, 149 /* feedback_div */ 150 223, 151 /* frac_n_div */ 152 524288, 153 /* post_pll_div */ 154 7, 155 }, 156}; 157 158/* struct ice_vernier_info_e82x 159 * 160 * E822 hardware calibrates the delay of the timestamp indication from the 161 * actual packet transmission or reception during the initialization of the 162 * PHY. To do this, the hardware mechanism uses some conversions between the 163 * various clocks within the PHY block. This table defines constants used to 164 * calculate the correct conversion ratios in the PHY registers. 165 * 166 * Many of the values relate to the PAR/PCS clock conversion registers. For 167 * these registers, a value of 0 means that the associated register is not 168 * used by this link speed, and that the register should be cleared by writing 169 * 0. Other values specify the clock frequency in Hz. 170 */ 171const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD] = { 172 /* ICE_PTP_LNK_SPD_1G */ 173 { 174 /* tx_par_clk */ 175 31250000, /* 31.25 MHz */ 176 /* rx_par_clk */ 177 31250000, /* 31.25 MHz */ 178 /* tx_pcs_clk */ 179 125000000, /* 125 MHz */ 180 /* rx_pcs_clk */ 181 125000000, /* 125 MHz */ 182 /* tx_desk_rsgb_par */ 183 0, /* unused */ 184 /* rx_desk_rsgb_par */ 185 0, /* unused */ 186 /* tx_desk_rsgb_pcs */ 187 0, /* unused */ 188 /* rx_desk_rsgb_pcs */ 189 0, /* unused */ 190 /* tx_fixed_delay */ 191 25140, 192 /* pmd_adj_divisor */ 193 10000000, 194 /* rx_fixed_delay */ 195 17372, 196 }, 197 /* ICE_PTP_LNK_SPD_10G */ 198 { 199 /* tx_par_clk */ 200 257812500, /* 257.8125 MHz */ 201 /* rx_par_clk */ 202 257812500, /* 257.8125 MHz */ 203 /* tx_pcs_clk */ 204 156250000, /* 156.25 MHz */ 205 /* rx_pcs_clk */ 206 156250000, /* 156.25 MHz */ 207 /* tx_desk_rsgb_par */ 208 0, /* unused */ 209 /* rx_desk_rsgb_par */ 210 0, /* unused */ 211 /* tx_desk_rsgb_pcs */ 212 0, /* unused */ 213 /* rx_desk_rsgb_pcs */ 214 0, /* unused */ 215 /* tx_fixed_delay */ 216 6938, 217 /* pmd_adj_divisor */ 218 82500000, 219 /* rx_fixed_delay */ 220 6212, 221 }, 222 /* ICE_PTP_LNK_SPD_25G */ 223 { 224 /* tx_par_clk */ 225 644531250, /* 644.53125 MHZ */ 226 /* rx_par_clk */ 227 644531250, /* 644.53125 MHz */ 228 /* tx_pcs_clk */ 229 390625000, /* 390.625 MHz */ 230 /* rx_pcs_clk */ 231 390625000, /* 390.625 MHz */ 232 /* tx_desk_rsgb_par */ 233 0, /* unused */ 234 /* rx_desk_rsgb_par */ 235 0, /* unused */ 236 /* tx_desk_rsgb_pcs */ 237 0, /* unused */ 238 /* rx_desk_rsgb_pcs */ 239 0, /* unused */ 240 /* tx_fixed_delay */ 241 2778, 242 /* pmd_adj_divisor */ 243 206250000, 244 /* rx_fixed_delay */ 245 2491, 246 }, 247 /* ICE_PTP_LNK_SPD_25G_RS */ 248 { 249 /* tx_par_clk */ 250 0, /* unused */ 251 /* rx_par_clk */ 252 0, /* unused */ 253 /* tx_pcs_clk */ 254 0, /* unused */ 255 /* rx_pcs_clk */ 256 0, /* unused */ 257 /* tx_desk_rsgb_par */ 258 161132812, /* 162.1328125 MHz Reed Solomon gearbox */ 259 /* rx_desk_rsgb_par */ 260 161132812, /* 162.1328125 MHz Reed Solomon gearbox */ 261 /* tx_desk_rsgb_pcs */ 262 97656250, /* 97.62625 MHz Reed Solomon gearbox */ 263 /* rx_desk_rsgb_pcs */ 264 97656250, /* 97.62625 MHz Reed Solomon gearbox */ 265 /* tx_fixed_delay */ 266 3928, 267 /* pmd_adj_divisor */ 268 206250000, 269 /* rx_fixed_delay */ 270 29535, 271 }, 272 /* ICE_PTP_LNK_SPD_40G */ 273 { 274 /* tx_par_clk */ 275 257812500, 276 /* rx_par_clk */ 277 257812500, 278 /* tx_pcs_clk */ 279 156250000, /* 156.25 MHz */ 280 /* rx_pcs_clk */ 281 156250000, /* 156.25 MHz */ 282 /* tx_desk_rsgb_par */ 283 0, /* unused */ 284 /* rx_desk_rsgb_par */ 285 156250000, /* 156.25 MHz deskew clock */ 286 /* tx_desk_rsgb_pcs */ 287 0, /* unused */ 288 /* rx_desk_rsgb_pcs */ 289 156250000, /* 156.25 MHz deskew clock */ 290 /* tx_fixed_delay */ 291 5666, 292 /* pmd_adj_divisor */ 293 82500000, 294 /* rx_fixed_delay */ 295 4244, 296 }, 297 /* ICE_PTP_LNK_SPD_50G */ 298 { 299 /* tx_par_clk */ 300 644531250, /* 644.53125 MHZ */ 301 /* rx_par_clk */ 302 644531250, /* 644.53125 MHZ */ 303 /* tx_pcs_clk */ 304 390625000, /* 390.625 MHz */ 305 /* rx_pcs_clk */ 306 390625000, /* 390.625 MHz */ 307 /* tx_desk_rsgb_par */ 308 0, /* unused */ 309 /* rx_desk_rsgb_par */ 310 195312500, /* 193.3125 MHz deskew clock */ 311 /* tx_desk_rsgb_pcs */ 312 0, /* unused */ 313 /* rx_desk_rsgb_pcs */ 314 195312500, /* 193.3125 MHz deskew clock */ 315 /* tx_fixed_delay */ 316 2778, 317 /* pmd_adj_divisor */ 318 206250000, 319 /* rx_fixed_delay */ 320 2868, 321 }, 322 /* ICE_PTP_LNK_SPD_50G_RS */ 323 { 324 /* tx_par_clk */ 325 0, /* unused */ 326 /* rx_par_clk */ 327 644531250, /* 644.53125 MHz */ 328 /* tx_pcs_clk */ 329 0, /* unused */ 330 /* rx_pcs_clk */ 331 644531250, /* 644.53125 MHz */ 332 /* tx_desk_rsgb_par */ 333 322265625, /* 322.265625 MHz Reed Solomon gearbox */ 334 /* rx_desk_rsgb_par */ 335 322265625, /* 322.265625 MHz Reed Solomon gearbox */ 336 /* tx_desk_rsgb_pcs */ 337 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 338 /* rx_desk_rsgb_pcs */ 339 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 340 /* tx_fixed_delay */ 341 2095, 342 /* pmd_adj_divisor */ 343 206250000, 344 /* rx_fixed_delay */ 345 14524, 346 }, 347 /* ICE_PTP_LNK_SPD_100G_RS */ 348 { 349 /* tx_par_clk */ 350 0, /* unused */ 351 /* rx_par_clk */ 352 644531250, /* 644.53125 MHz */ 353 /* tx_pcs_clk */ 354 0, /* unused */ 355 /* rx_pcs_clk */ 356 644531250, /* 644.53125 MHz */ 357 /* tx_desk_rsgb_par */ 358 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 359 /* rx_desk_rsgb_par */ 360 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 361 /* tx_desk_rsgb_pcs */ 362 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 363 /* rx_desk_rsgb_pcs */ 364 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 365 /* tx_fixed_delay */ 366 1620, 367 /* pmd_adj_divisor */ 368 206250000, 369 /* rx_fixed_delay */ 370 7775, 371 }, 372}; 373 374#endif /* _ICE_PTP_CONSTS_H_ */ 375