1181421Sedwin/* SPDX-License-Identifier: GPL-2.0-or-later */ 2153761Swollman/* 364499Swollman * Faraday FTMAC100 10/100 Ethernet 42742Swollman * 52742Swollman * (C) Copyright 2009-2011 Faraday Technology 62742Swollman * Po-Yu Chuang <ratbert@faraday-tech.com> 72742Swollman */ 8158421Swollman 92742Swollman#ifndef __FTMAC100_H 102742Swollman#define __FTMAC100_H 11158421Swollman 12158421Swollman#define FTMAC100_OFFSET_ISR 0x00 132742Swollman#define FTMAC100_OFFSET_IMR 0x04 1486222Swollman#define FTMAC100_OFFSET_MAC_MADR 0x08 1520094Swollman#define FTMAC100_OFFSET_MAC_LADR 0x0c 1620094Swollman#define FTMAC100_OFFSET_MAHT0 0x10 1720094Swollman#define FTMAC100_OFFSET_MAHT1 0x14 1820094Swollman#define FTMAC100_OFFSET_TXPD 0x18 1920094Swollman#define FTMAC100_OFFSET_RXPD 0x1c 20158421Swollman#define FTMAC100_OFFSET_TXR_BADR 0x20 21158421Swollman#define FTMAC100_OFFSET_RXR_BADR 0x24 2220094Swollman#define FTMAC100_OFFSET_ITC 0x28 232742Swollman#define FTMAC100_OFFSET_APTC 0x2c 242742Swollman#define FTMAC100_OFFSET_DBLAC 0x30 252742Swollman#define FTMAC100_OFFSET_MACCR 0x88 262742Swollman#define FTMAC100_OFFSET_MACSR 0x8c 272742Swollman#define FTMAC100_OFFSET_PHYCR 0x90 2858787Sru#define FTMAC100_OFFSET_PHYWDATA 0x94 292742Swollman#define FTMAC100_OFFSET_FCR 0x98 302742Swollman#define FTMAC100_OFFSET_BPR 0x9c 312742Swollman#define FTMAC100_OFFSET_TS 0xc4 322742Swollman#define FTMAC100_OFFSET_DMAFIFOS 0xc8 33114173Swollman#define FTMAC100_OFFSET_TM 0xcc 34114173Swollman#define FTMAC100_OFFSET_TX_MCOL_SCOL 0xd4 35114173Swollman#define FTMAC100_OFFSET_RPF_AEP 0xd8 36114173Swollman#define FTMAC100_OFFSET_XM_PG 0xdc 37114173Swollman#define FTMAC100_OFFSET_RUNT_TLCC 0xe0 38114173Swollman#define FTMAC100_OFFSET_CRCER_FTL 0xe4 39114173Swollman#define FTMAC100_OFFSET_RLC_RCC 0xe8 40114173Swollman#define FTMAC100_OFFSET_BROC 0xec 41114173Swollman#define FTMAC100_OFFSET_MULCA 0xf0 42114173Swollman#define FTMAC100_OFFSET_RP 0xf4 43114173Swollman#define FTMAC100_OFFSET_XP 0xf8 44114173Swollman 45114173Swollman/* 46114173Swollman * Interrupt status register & interrupt mask register 47149590Swollman */ 48149590Swollman#define FTMAC100_INT_RPKT_FINISH (1 << 0) 49114173Swollman#define FTMAC100_INT_NORXBUF (1 << 1) 502742Swollman#define FTMAC100_INT_XPKT_FINISH (1 << 2) 519908Swollman#define FTMAC100_INT_NOTXBUF (1 << 3) 522742Swollman#define FTMAC100_INT_XPKT_OK (1 << 4) 532742Swollman#define FTMAC100_INT_XPKT_LOST (1 << 5) 542742Swollman#define FTMAC100_INT_RPKT_SAV (1 << 6) 552742Swollman#define FTMAC100_INT_RPKT_LOST (1 << 7) 562742Swollman#define FTMAC100_INT_AHB_ERR (1 << 8) 572742Swollman#define FTMAC100_INT_PHYSTS_CHG (1 << 9) 582742Swollman 592742Swollman/* 602742Swollman * Interrupt timer control register 6120094Swollman */ 622742Swollman#define FTMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) 6320094Swollman#define FTMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) 64158421Swollman#define FTMAC100_ITC_RXINT_TIME_SEL (1 << 7) 6520094Swollman#define FTMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) 6620094Swollman#define FTMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) 6720094Swollman#define FTMAC100_ITC_TXINT_TIME_SEL (1 << 15) 6820094Swollman 6920094Swollman/* 7020094Swollman * Automatic polling timer control register 7120094Swollman */ 7220094Swollman#define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) 7320094Swollman#define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) 7420094Swollman#define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) 7520094Swollman#define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) 7620094Swollman 7720094Swollman/* 782742Swollman * DMA burst length and arbitration control register 792742Swollman */ 802742Swollman#define FTMAC100_DBLAC_INCR4_EN (1 << 0) 812742Swollman#define FTMAC100_DBLAC_INCR8_EN (1 << 1) 8219878Swollman#define FTMAC100_DBLAC_INCR16_EN (1 << 2) 832742Swollman#define FTMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 3) 842742Swollman#define FTMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 6) 852742Swollman#define FTMAC100_DBLAC_RX_THR_EN (1 << 9) 86158421Swollman 87158421Swollman/* 88158421Swollman * MAC control register 89158421Swollman */ 90158421Swollman#define FTMAC100_MACCR_XDMA_EN (1 << 0) 91153670Swollman#define FTMAC100_MACCR_RDMA_EN (1 << 1) 9243014Swollman#define FTMAC100_MACCR_SW_RST (1 << 2) 9343014Swollman#define FTMAC100_MACCR_LOOP_EN (1 << 3) 9443014Swollman#define FTMAC100_MACCR_CRC_DIS (1 << 4) 952742Swollman#define FTMAC100_MACCR_XMT_EN (1 << 5) 962742Swollman#define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6) 9719878Swollman#define FTMAC100_MACCR_RCV_EN (1 << 8) 9819878Swollman#define FTMAC100_MACCR_HT_MULTI_EN (1 << 9) 9919878Swollman#define FTMAC100_MACCR_RX_RUNT (1 << 10) 10058787Sru#define FTMAC100_MACCR_RX_FTL (1 << 11) 10143014Swollman#define FTMAC100_MACCR_RCV_ALL (1 << 12) 10275267Swollman#define FTMAC100_MACCR_CRC_APD (1 << 14) 1032742Swollman#define FTMAC100_MACCR_FULLDUP (1 << 15) 1042742Swollman#define FTMAC100_MACCR_RX_MULTIPKT (1 << 16) 105153670Swollman#define FTMAC100_MACCR_RX_BROADPKT (1 << 17) 106153670Swollman 107153670Swollman/* 10843014Swollman * PHY control register 109153670Swollman */ 110153670Swollman#define FTMAC100_PHYCR_MIIRDATA 0xffff 1112742Swollman#define FTMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) 1122742Swollman#define FTMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) 11319878Swollman#define FTMAC100_PHYCR_MIIRD (1 << 26) 11419878Swollman#define FTMAC100_PHYCR_MIIWR (1 << 27) 11519878Swollman 116149514Swollman/* 11720094Swollman * PHY write data register 11843014Swollman */ 11943014Swollman#define FTMAC100_PHYWDATA_MIIWDATA(x) ((x) & 0xffff) 1202742Swollman 1212742Swollman/* 1222742Swollman * Transmit descriptor, aligned to 16 bytes 12367578Swollman */ 1242742Swollmanstruct ftmac100_txdes { 1252742Swollman __le32 txdes0; 1262742Swollman __le32 txdes1; 1272742Swollman __le32 txdes2; /* TXBUF_BADR */ 1282742Swollman unsigned int txdes3; /* not used by HW */ 12975267Swollman} __attribute__ ((aligned(16))); 13019878Swollman 13119878Swollman#define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0) 1322742Swollman#define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1) 13319878Swollman#define FTMAC100_TXDES0_TXDMA_OWN (1 << 31) 13419878Swollman 13519878Swollman#define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff) 1362742Swollman#define FTMAC100_TXDES1_LTS (1 << 27) 1372742Swollman#define FTMAC100_TXDES1_FTS (1 << 28) 1382742Swollman#define FTMAC100_TXDES1_TX2FIC (1 << 29) 13967578Swollman#define FTMAC100_TXDES1_TXIC (1 << 30) 1402742Swollman#define FTMAC100_TXDES1_EDOTR (1 << 31) 14119878Swollman 1422742Swollman/* 1432742Swollman * Receive descriptor, aligned to 16 bytes 14486222Swollman */ 14586222Swollmanstruct ftmac100_rxdes { 146149514Swollman __le32 rxdes0; 147149514Swollman __le32 rxdes1; 148149514Swollman __le32 rxdes2; /* RXBUF_BADR */ 1492742Swollman unsigned int rxdes3; /* not used by HW */ 150149514Swollman} __attribute__ ((aligned(16))); 151149514Swollman 15286222Swollman#define FTMAC100_RXDES0_RFL 0x7ff 1532742Swollman#define FTMAC100_RXDES0_MULTICAST (1 << 16) 1542742Swollman#define FTMAC100_RXDES0_BROADCAST (1 << 17) 1552742Swollman#define FTMAC100_RXDES0_RX_ERR (1 << 18) 1562742Swollman#define FTMAC100_RXDES0_CRC_ERR (1 << 19) 1572742Swollman#define FTMAC100_RXDES0_FTL (1 << 20) 1582742Swollman#define FTMAC100_RXDES0_RUNT (1 << 21) 1592742Swollman#define FTMAC100_RXDES0_RX_ODD_NB (1 << 22) 16014343Swollman#define FTMAC100_RXDES0_LRS (1 << 28) 1612742Swollman#define FTMAC100_RXDES0_FRS (1 << 29) 16217200Swollman#define FTMAC100_RXDES0_RXDMA_OWN (1 << 31) 16319878Swollman 16419878Swollman#define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff) 1652742Swollman#define FTMAC100_RXDES1_EDORR (1 << 31) 16619878Swollman 1672742Swollman#endif /* __FTMAC100_H */ 1682742Swollman