1/* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#ifndef __T4_MSG_H 36#define __T4_MSG_H 37 38#include <linux/types.h> 39 40enum { 41 CPL_PASS_OPEN_REQ = 0x1, 42 CPL_PASS_ACCEPT_RPL = 0x2, 43 CPL_ACT_OPEN_REQ = 0x3, 44 CPL_SET_TCB_FIELD = 0x5, 45 CPL_GET_TCB = 0x6, 46 CPL_CLOSE_CON_REQ = 0x8, 47 CPL_CLOSE_LISTSRV_REQ = 0x9, 48 CPL_ABORT_REQ = 0xA, 49 CPL_ABORT_RPL = 0xB, 50 CPL_TX_DATA = 0xC, 51 CPL_RX_DATA_ACK = 0xD, 52 CPL_TX_PKT = 0xE, 53 CPL_L2T_WRITE_REQ = 0x12, 54 CPL_SMT_WRITE_REQ = 0x14, 55 CPL_TID_RELEASE = 0x1A, 56 CPL_SRQ_TABLE_REQ = 0x1C, 57 CPL_TX_DATA_ISO = 0x1F, 58 59 CPL_CLOSE_LISTSRV_RPL = 0x20, 60 CPL_GET_TCB_RPL = 0x22, 61 CPL_L2T_WRITE_RPL = 0x23, 62 CPL_PASS_OPEN_RPL = 0x24, 63 CPL_ACT_OPEN_RPL = 0x25, 64 CPL_PEER_CLOSE = 0x26, 65 CPL_ABORT_REQ_RSS = 0x2B, 66 CPL_ABORT_RPL_RSS = 0x2D, 67 CPL_SMT_WRITE_RPL = 0x2E, 68 69 CPL_RX_PHYS_ADDR = 0x30, 70 CPL_CLOSE_CON_RPL = 0x32, 71 CPL_ISCSI_HDR = 0x33, 72 CPL_RDMA_CQE = 0x35, 73 CPL_RDMA_CQE_READ_RSP = 0x36, 74 CPL_RDMA_CQE_ERR = 0x37, 75 CPL_RX_DATA = 0x39, 76 CPL_SET_TCB_RPL = 0x3A, 77 CPL_RX_PKT = 0x3B, 78 CPL_RX_DDP_COMPLETE = 0x3F, 79 80 CPL_ACT_ESTABLISH = 0x40, 81 CPL_PASS_ESTABLISH = 0x41, 82 CPL_RX_DATA_DDP = 0x42, 83 CPL_PASS_ACCEPT_REQ = 0x44, 84 CPL_RX_ISCSI_CMP = 0x45, 85 CPL_TRACE_PKT_T5 = 0x48, 86 CPL_RX_ISCSI_DDP = 0x49, 87 CPL_RX_TLS_CMP = 0x4E, 88 89 CPL_RDMA_READ_REQ = 0x60, 90 91 CPL_PASS_OPEN_REQ6 = 0x81, 92 CPL_ACT_OPEN_REQ6 = 0x83, 93 94 CPL_TX_TLS_PDU = 0x88, 95 CPL_TX_TLS_SFO = 0x89, 96 CPL_TX_SEC_PDU = 0x8A, 97 CPL_TX_TLS_ACK = 0x8B, 98 99 CPL_RDMA_TERMINATE = 0xA2, 100 CPL_RDMA_WRITE = 0xA4, 101 CPL_SGE_EGR_UPDATE = 0xA5, 102 CPL_RX_MPS_PKT = 0xAF, 103 104 CPL_TRACE_PKT = 0xB0, 105 CPL_TLS_DATA = 0xB1, 106 CPL_ISCSI_DATA = 0xB2, 107 108 CPL_FW4_MSG = 0xC0, 109 CPL_FW4_PLD = 0xC1, 110 CPL_FW4_ACK = 0xC3, 111 CPL_SRQ_TABLE_RPL = 0xCC, 112 113 CPL_RX_PHYS_DSGL = 0xD0, 114 115 CPL_FW6_MSG = 0xE0, 116 CPL_FW6_PLD = 0xE1, 117 CPL_TX_TNL_LSO = 0xEC, 118 CPL_TX_PKT_LSO = 0xED, 119 CPL_TX_PKT_XT = 0xEE, 120 121 NUM_CPL_CMDS 122}; 123 124enum CPL_error { 125 CPL_ERR_NONE = 0, 126 CPL_ERR_TCAM_PARITY = 1, 127 CPL_ERR_TCAM_MISS = 2, 128 CPL_ERR_TCAM_FULL = 3, 129 CPL_ERR_BAD_LENGTH = 15, 130 CPL_ERR_BAD_ROUTE = 18, 131 CPL_ERR_CONN_RESET = 20, 132 CPL_ERR_CONN_EXIST_SYNRECV = 21, 133 CPL_ERR_CONN_EXIST = 22, 134 CPL_ERR_ARP_MISS = 23, 135 CPL_ERR_BAD_SYN = 24, 136 CPL_ERR_CONN_TIMEDOUT = 30, 137 CPL_ERR_XMIT_TIMEDOUT = 31, 138 CPL_ERR_PERSIST_TIMEDOUT = 32, 139 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 140 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 141 CPL_ERR_RTX_NEG_ADVICE = 35, 142 CPL_ERR_PERSIST_NEG_ADVICE = 36, 143 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 144 CPL_ERR_ABORT_FAILED = 42, 145 CPL_ERR_IWARP_FLM = 50, 146 CPL_CONTAINS_READ_RPL = 60, 147 CPL_CONTAINS_WRITE_RPL = 61, 148}; 149 150enum { 151 CPL_CONN_POLICY_AUTO = 0, 152 CPL_CONN_POLICY_ASK = 1, 153 CPL_CONN_POLICY_FILTER = 2, 154 CPL_CONN_POLICY_DENY = 3 155}; 156 157enum { 158 ULP_MODE_NONE = 0, 159 ULP_MODE_ISCSI = 2, 160 ULP_MODE_RDMA = 4, 161 ULP_MODE_TCPDDP = 5, 162 ULP_MODE_FCOE = 6, 163 ULP_MODE_TLS = 8, 164}; 165 166enum { 167 ULP_CRC_HEADER = 1 << 0, 168 ULP_CRC_DATA = 1 << 1 169}; 170 171enum { 172 CPL_ABORT_SEND_RST = 0, 173 CPL_ABORT_NO_RST, 174}; 175 176enum { /* TX_PKT_XT checksum types */ 177 TX_CSUM_TCP = 0, 178 TX_CSUM_UDP = 1, 179 TX_CSUM_CRC16 = 4, 180 TX_CSUM_CRC32 = 5, 181 TX_CSUM_CRC32C = 6, 182 TX_CSUM_FCOE = 7, 183 TX_CSUM_TCPIP = 8, 184 TX_CSUM_UDPIP = 9, 185 TX_CSUM_TCPIP6 = 10, 186 TX_CSUM_UDPIP6 = 11, 187 TX_CSUM_IP = 12, 188}; 189 190union opcode_tid { 191 __be32 opcode_tid; 192 u8 opcode; 193}; 194 195#define CPL_OPCODE_S 24 196#define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S) 197#define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF) 198#define TID_G(x) ((x) & 0xFFFFFF) 199 200/* tid is assumed to be 24-bits */ 201#define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid)) 202 203#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 204 205/* extract the TID from a CPL command */ 206#define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd)))) 207 208/* partitioning of TID fields that also carry a queue id */ 209#define TID_TID_S 0 210#define TID_TID_M 0x3fff 211#define TID_TID_V(x) ((x) << TID_TID_S) 212#define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M) 213 214#define TID_QID_S 14 215#define TID_QID_M 0x3ff 216#define TID_QID_V(x) ((x) << TID_QID_S) 217#define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M) 218 219struct rss_header { 220 u8 opcode; 221#if defined(__LITTLE_ENDIAN_BITFIELD) 222 u8 channel:2; 223 u8 filter_hit:1; 224 u8 filter_tid:1; 225 u8 hash_type:2; 226 u8 ipv6:1; 227 u8 send2fw:1; 228#else 229 u8 send2fw:1; 230 u8 ipv6:1; 231 u8 hash_type:2; 232 u8 filter_tid:1; 233 u8 filter_hit:1; 234 u8 channel:2; 235#endif 236 __be16 qid; 237 __be32 hash_val; 238}; 239 240struct work_request_hdr { 241 __be32 wr_hi; 242 __be32 wr_mid; 243 __be64 wr_lo; 244}; 245 246/* wr_hi fields */ 247#define WR_OP_S 24 248#define WR_OP_V(x) ((__u64)(x) << WR_OP_S) 249 250#define WR_HDR struct work_request_hdr wr 251 252/* option 0 fields */ 253#define TX_CHAN_S 2 254#define TX_CHAN_V(x) ((x) << TX_CHAN_S) 255 256#define ULP_MODE_S 8 257#define ULP_MODE_V(x) ((x) << ULP_MODE_S) 258 259#define RCV_BUFSIZ_S 12 260#define RCV_BUFSIZ_M 0x3FFU 261#define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S) 262 263#define SMAC_SEL_S 28 264#define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S) 265 266#define L2T_IDX_S 36 267#define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S) 268 269#define WND_SCALE_S 50 270#define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S) 271 272#define KEEP_ALIVE_S 54 273#define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S) 274#define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL) 275 276#define MSS_IDX_S 60 277#define MSS_IDX_M 0xF 278#define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S) 279#define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M) 280 281/* option 2 fields */ 282#define RSS_QUEUE_S 0 283#define RSS_QUEUE_M 0x3FF 284#define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S) 285#define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M) 286 287#define RSS_QUEUE_VALID_S 10 288#define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S) 289#define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U) 290 291#define RX_FC_DISABLE_S 20 292#define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S) 293#define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U) 294 295#define RX_FC_VALID_S 22 296#define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S) 297#define RX_FC_VALID_F RX_FC_VALID_V(1U) 298 299#define RX_CHANNEL_S 26 300#define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S) 301#define RX_CHANNEL_F RX_CHANNEL_V(1U) 302 303#define WND_SCALE_EN_S 28 304#define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S) 305#define WND_SCALE_EN_F WND_SCALE_EN_V(1U) 306 307#define T5_OPT_2_VALID_S 31 308#define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S) 309#define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U) 310 311struct cpl_pass_open_req { 312 WR_HDR; 313 union opcode_tid ot; 314 __be16 local_port; 315 __be16 peer_port; 316 __be32 local_ip; 317 __be32 peer_ip; 318 __be64 opt0; 319 __be64 opt1; 320}; 321 322/* option 0 fields */ 323#define NO_CONG_S 4 324#define NO_CONG_V(x) ((x) << NO_CONG_S) 325#define NO_CONG_F NO_CONG_V(1U) 326 327#define DELACK_S 5 328#define DELACK_V(x) ((x) << DELACK_S) 329#define DELACK_F DELACK_V(1U) 330 331#define NON_OFFLOAD_S 7 332#define NON_OFFLOAD_V(x) ((x) << NON_OFFLOAD_S) 333#define NON_OFFLOAD_F NON_OFFLOAD_V(1U) 334 335#define DSCP_S 22 336#define DSCP_M 0x3F 337#define DSCP_V(x) ((x) << DSCP_S) 338#define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M) 339 340#define TCAM_BYPASS_S 48 341#define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S) 342#define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL) 343 344#define NAGLE_S 49 345#define NAGLE_V(x) ((__u64)(x) << NAGLE_S) 346#define NAGLE_F NAGLE_V(1ULL) 347 348/* option 1 fields */ 349#define SYN_RSS_ENABLE_S 0 350#define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S) 351#define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U) 352 353#define SYN_RSS_QUEUE_S 2 354#define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S) 355 356#define CONN_POLICY_S 22 357#define CONN_POLICY_V(x) ((x) << CONN_POLICY_S) 358 359struct cpl_pass_open_req6 { 360 WR_HDR; 361 union opcode_tid ot; 362 __be16 local_port; 363 __be16 peer_port; 364 __be64 local_ip_hi; 365 __be64 local_ip_lo; 366 __be64 peer_ip_hi; 367 __be64 peer_ip_lo; 368 __be64 opt0; 369 __be64 opt1; 370}; 371 372struct cpl_pass_open_rpl { 373 union opcode_tid ot; 374 u8 rsvd[3]; 375 u8 status; 376}; 377 378struct tcp_options { 379 __be16 mss; 380 __u8 wsf; 381#if defined(__LITTLE_ENDIAN_BITFIELD) 382 __u8:4; 383 __u8 unknown:1; 384 __u8:1; 385 __u8 sack:1; 386 __u8 tstamp:1; 387#else 388 __u8 tstamp:1; 389 __u8 sack:1; 390 __u8:1; 391 __u8 unknown:1; 392 __u8:4; 393#endif 394}; 395 396struct cpl_pass_accept_req { 397 union opcode_tid ot; 398 __be16 rsvd; 399 __be16 len; 400 __be32 hdr_len; 401 __be16 vlan; 402 __be16 l2info; 403 __be32 tos_stid; 404 struct tcp_options tcpopt; 405}; 406 407/* cpl_pass_accept_req.hdr_len fields */ 408#define SYN_RX_CHAN_S 0 409#define SYN_RX_CHAN_M 0xF 410#define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S) 411#define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M) 412 413#define TCP_HDR_LEN_S 10 414#define TCP_HDR_LEN_M 0x3F 415#define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S) 416#define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 417 418#define IP_HDR_LEN_S 16 419#define IP_HDR_LEN_M 0x3FF 420#define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S) 421#define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M) 422 423#define ETH_HDR_LEN_S 26 424#define ETH_HDR_LEN_M 0x1F 425#define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S) 426#define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M) 427 428/* cpl_pass_accept_req.l2info fields */ 429#define SYN_MAC_IDX_S 0 430#define SYN_MAC_IDX_M 0x1FF 431#define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S) 432#define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M) 433 434#define SYN_XACT_MATCH_S 9 435#define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S) 436#define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U) 437 438#define SYN_INTF_S 12 439#define SYN_INTF_M 0xF 440#define SYN_INTF_V(x) ((x) << SYN_INTF_S) 441#define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M) 442 443enum { /* TCP congestion control algorithms */ 444 CONG_ALG_RENO, 445 CONG_ALG_TAHOE, 446 CONG_ALG_NEWRENO, 447 CONG_ALG_HIGHSPEED 448}; 449 450#define CONG_CNTRL_S 14 451#define CONG_CNTRL_M 0x3 452#define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S) 453#define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M) 454 455#define T5_ISS_S 18 456#define T5_ISS_V(x) ((x) << T5_ISS_S) 457#define T5_ISS_F T5_ISS_V(1U) 458 459struct cpl_pass_accept_rpl { 460 WR_HDR; 461 union opcode_tid ot; 462 __be32 opt2; 463 __be64 opt0; 464}; 465 466/* option 2 fields */ 467#define RX_COALESCE_VALID_S 11 468#define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S) 469#define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U) 470 471#define RX_COALESCE_S 12 472#define RX_COALESCE_V(x) ((x) << RX_COALESCE_S) 473 474#define PACE_S 16 475#define PACE_V(x) ((x) << PACE_S) 476 477#define TX_QUEUE_S 23 478#define TX_QUEUE_M 0x7 479#define TX_QUEUE_V(x) ((x) << TX_QUEUE_S) 480#define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M) 481 482#define CCTRL_ECN_S 27 483#define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S) 484#define CCTRL_ECN_F CCTRL_ECN_V(1U) 485 486#define TSTAMPS_EN_S 29 487#define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S) 488#define TSTAMPS_EN_F TSTAMPS_EN_V(1U) 489 490#define SACK_EN_S 30 491#define SACK_EN_V(x) ((x) << SACK_EN_S) 492#define SACK_EN_F SACK_EN_V(1U) 493 494struct cpl_t5_pass_accept_rpl { 495 WR_HDR; 496 union opcode_tid ot; 497 __be32 opt2; 498 __be64 opt0; 499 __be32 iss; 500 __be32 rsvd; 501}; 502 503struct cpl_act_open_req { 504 WR_HDR; 505 union opcode_tid ot; 506 __be16 local_port; 507 __be16 peer_port; 508 __be32 local_ip; 509 __be32 peer_ip; 510 __be64 opt0; 511 __be32 params; 512 __be32 opt2; 513}; 514 515#define FILTER_TUPLE_S 24 516#define FILTER_TUPLE_M 0xFFFFFFFFFF 517#define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S) 518#define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M) 519struct cpl_t5_act_open_req { 520 WR_HDR; 521 union opcode_tid ot; 522 __be16 local_port; 523 __be16 peer_port; 524 __be32 local_ip; 525 __be32 peer_ip; 526 __be64 opt0; 527 __be32 rsvd; 528 __be32 opt2; 529 __be64 params; 530}; 531 532struct cpl_t6_act_open_req { 533 WR_HDR; 534 union opcode_tid ot; 535 __be16 local_port; 536 __be16 peer_port; 537 __be32 local_ip; 538 __be32 peer_ip; 539 __be64 opt0; 540 __be32 rsvd; 541 __be32 opt2; 542 __be64 params; 543 __be32 rsvd2; 544 __be32 opt3; 545}; 546 547struct cpl_act_open_req6 { 548 WR_HDR; 549 union opcode_tid ot; 550 __be16 local_port; 551 __be16 peer_port; 552 __be64 local_ip_hi; 553 __be64 local_ip_lo; 554 __be64 peer_ip_hi; 555 __be64 peer_ip_lo; 556 __be64 opt0; 557 __be32 params; 558 __be32 opt2; 559}; 560 561struct cpl_t5_act_open_req6 { 562 WR_HDR; 563 union opcode_tid ot; 564 __be16 local_port; 565 __be16 peer_port; 566 __be64 local_ip_hi; 567 __be64 local_ip_lo; 568 __be64 peer_ip_hi; 569 __be64 peer_ip_lo; 570 __be64 opt0; 571 __be32 rsvd; 572 __be32 opt2; 573 __be64 params; 574}; 575 576struct cpl_t6_act_open_req6 { 577 WR_HDR; 578 union opcode_tid ot; 579 __be16 local_port; 580 __be16 peer_port; 581 __be64 local_ip_hi; 582 __be64 local_ip_lo; 583 __be64 peer_ip_hi; 584 __be64 peer_ip_lo; 585 __be64 opt0; 586 __be32 rsvd; 587 __be32 opt2; 588 __be64 params; 589 __be32 rsvd2; 590 __be32 opt3; 591}; 592 593struct cpl_act_open_rpl { 594 union opcode_tid ot; 595 __be32 atid_status; 596}; 597 598/* cpl_act_open_rpl.atid_status fields */ 599#define AOPEN_STATUS_S 0 600#define AOPEN_STATUS_M 0xFF 601#define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M) 602 603#define AOPEN_ATID_S 8 604#define AOPEN_ATID_M 0xFFFFFF 605#define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M) 606 607struct cpl_pass_establish { 608 union opcode_tid ot; 609 __be32 rsvd; 610 __be32 tos_stid; 611 __be16 mac_idx; 612 __be16 tcp_opt; 613 __be32 snd_isn; 614 __be32 rcv_isn; 615}; 616 617/* cpl_pass_establish.tos_stid fields */ 618#define PASS_OPEN_TID_S 0 619#define PASS_OPEN_TID_M 0xFFFFFF 620#define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S) 621#define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M) 622 623#define PASS_OPEN_TOS_S 24 624#define PASS_OPEN_TOS_M 0xFF 625#define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S) 626#define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M) 627 628/* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 629#define TCPOPT_WSCALE_OK_S 5 630#define TCPOPT_WSCALE_OK_M 0x1 631#define TCPOPT_WSCALE_OK_G(x) \ 632 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M) 633 634#define TCPOPT_SACK_S 6 635#define TCPOPT_SACK_M 0x1 636#define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M) 637 638#define TCPOPT_TSTAMP_S 7 639#define TCPOPT_TSTAMP_M 0x1 640#define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M) 641 642#define TCPOPT_SND_WSCALE_S 8 643#define TCPOPT_SND_WSCALE_M 0xF 644#define TCPOPT_SND_WSCALE_G(x) \ 645 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M) 646 647#define TCPOPT_MSS_S 12 648#define TCPOPT_MSS_M 0xF 649#define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M) 650 651#define T6_TCP_HDR_LEN_S 8 652#define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S) 653#define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 654 655#define T6_IP_HDR_LEN_S 14 656#define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S) 657#define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M) 658 659#define T6_ETH_HDR_LEN_S 24 660#define T6_ETH_HDR_LEN_M 0xFF 661#define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S) 662#define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M) 663 664struct cpl_act_establish { 665 union opcode_tid ot; 666 __be32 rsvd; 667 __be32 tos_atid; 668 __be16 mac_idx; 669 __be16 tcp_opt; 670 __be32 snd_isn; 671 __be32 rcv_isn; 672}; 673 674struct cpl_get_tcb { 675 WR_HDR; 676 union opcode_tid ot; 677 __be16 reply_ctrl; 678 __be16 cookie; 679}; 680 681/* cpl_get_tcb.reply_ctrl fields */ 682#define QUEUENO_S 0 683#define QUEUENO_V(x) ((x) << QUEUENO_S) 684 685#define REPLY_CHAN_S 14 686#define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S) 687#define REPLY_CHAN_F REPLY_CHAN_V(1U) 688 689#define NO_REPLY_S 15 690#define NO_REPLY_V(x) ((x) << NO_REPLY_S) 691#define NO_REPLY_F NO_REPLY_V(1U) 692 693struct cpl_get_tcb_rpl { 694 union opcode_tid ot; 695 __u8 cookie; 696 __u8 status; 697 __be16 len; 698}; 699 700struct cpl_set_tcb_field { 701 WR_HDR; 702 union opcode_tid ot; 703 __be16 reply_ctrl; 704 __be16 word_cookie; 705 __be64 mask; 706 __be64 val; 707}; 708 709struct cpl_set_tcb_field_core { 710 union opcode_tid ot; 711 __be16 reply_ctrl; 712 __be16 word_cookie; 713 __be64 mask; 714 __be64 val; 715}; 716 717/* cpl_set_tcb_field.word_cookie fields */ 718#define TCB_WORD_S 0 719#define TCB_WORD_V(x) ((x) << TCB_WORD_S) 720 721#define TCB_COOKIE_S 5 722#define TCB_COOKIE_M 0x7 723#define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S) 724#define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M) 725 726struct cpl_set_tcb_rpl { 727 union opcode_tid ot; 728 __be16 rsvd; 729 u8 cookie; 730 u8 status; 731 __be64 oldval; 732}; 733 734struct cpl_close_con_req { 735 WR_HDR; 736 union opcode_tid ot; 737 __be32 rsvd; 738}; 739 740struct cpl_close_con_rpl { 741 union opcode_tid ot; 742 u8 rsvd[3]; 743 u8 status; 744 __be32 snd_nxt; 745 __be32 rcv_nxt; 746}; 747 748struct cpl_close_listsvr_req { 749 WR_HDR; 750 union opcode_tid ot; 751 __be16 reply_ctrl; 752 __be16 rsvd; 753}; 754 755/* additional cpl_close_listsvr_req.reply_ctrl field */ 756#define LISTSVR_IPV6_S 14 757#define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S) 758#define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U) 759 760struct cpl_close_listsvr_rpl { 761 union opcode_tid ot; 762 u8 rsvd[3]; 763 u8 status; 764}; 765 766struct cpl_abort_req_rss { 767 union opcode_tid ot; 768 u8 rsvd[3]; 769 u8 status; 770}; 771 772struct cpl_abort_req_rss6 { 773 union opcode_tid ot; 774 __be32 srqidx_status; 775}; 776 777#define ABORT_RSS_STATUS_S 0 778#define ABORT_RSS_STATUS_M 0xff 779#define ABORT_RSS_STATUS_V(x) ((x) << ABORT_RSS_STATUS_S) 780#define ABORT_RSS_STATUS_G(x) (((x) >> ABORT_RSS_STATUS_S) & ABORT_RSS_STATUS_M) 781 782#define ABORT_RSS_SRQIDX_S 8 783#define ABORT_RSS_SRQIDX_M 0xffffff 784#define ABORT_RSS_SRQIDX_V(x) ((x) << ABORT_RSS_SRQIDX_S) 785#define ABORT_RSS_SRQIDX_G(x) (((x) >> ABORT_RSS_SRQIDX_S) & ABORT_RSS_SRQIDX_M) 786 787struct cpl_abort_req { 788 WR_HDR; 789 union opcode_tid ot; 790 __be32 rsvd0; 791 u8 rsvd1; 792 u8 cmd; 793 u8 rsvd2[6]; 794}; 795 796struct cpl_abort_rpl_rss { 797 union opcode_tid ot; 798 u8 rsvd[3]; 799 u8 status; 800}; 801 802struct cpl_abort_rpl_rss6 { 803 union opcode_tid ot; 804 __be32 srqidx_status; 805}; 806 807struct cpl_abort_rpl { 808 WR_HDR; 809 union opcode_tid ot; 810 __be32 rsvd0; 811 u8 rsvd1; 812 u8 cmd; 813 u8 rsvd2[6]; 814}; 815 816struct cpl_peer_close { 817 union opcode_tid ot; 818 __be32 rcv_nxt; 819}; 820 821struct cpl_tid_release { 822 WR_HDR; 823 union opcode_tid ot; 824 __be32 rsvd; 825}; 826 827struct cpl_tx_pkt_core { 828 __be32 ctrl0; 829 __be16 pack; 830 __be16 len; 831 __be64 ctrl1; 832}; 833 834struct cpl_tx_pkt { 835 WR_HDR; 836 struct cpl_tx_pkt_core c; 837}; 838 839#define cpl_tx_pkt_xt cpl_tx_pkt 840 841/* cpl_tx_pkt_core.ctrl0 fields */ 842#define TXPKT_VF_S 0 843#define TXPKT_VF_V(x) ((x) << TXPKT_VF_S) 844 845#define TXPKT_PF_S 8 846#define TXPKT_PF_V(x) ((x) << TXPKT_PF_S) 847 848#define TXPKT_VF_VLD_S 11 849#define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S) 850#define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U) 851 852#define TXPKT_OVLAN_IDX_S 12 853#define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S) 854 855#define TXPKT_T5_OVLAN_IDX_S 12 856#define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S) 857 858#define TXPKT_INTF_S 16 859#define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S) 860 861#define TXPKT_INS_OVLAN_S 21 862#define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S) 863#define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U) 864 865#define TXPKT_TSTAMP_S 23 866#define TXPKT_TSTAMP_V(x) ((x) << TXPKT_TSTAMP_S) 867#define TXPKT_TSTAMP_F TXPKT_TSTAMP_V(1ULL) 868 869#define TXPKT_OPCODE_S 24 870#define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S) 871 872/* cpl_tx_pkt_core.ctrl1 fields */ 873#define TXPKT_CSUM_END_S 12 874#define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S) 875 876#define TXPKT_CSUM_START_S 20 877#define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S) 878 879#define TXPKT_IPHDR_LEN_S 20 880#define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S) 881 882#define TXPKT_CSUM_LOC_S 30 883#define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S) 884 885#define TXPKT_ETHHDR_LEN_S 34 886#define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S) 887 888#define T6_TXPKT_ETHHDR_LEN_S 32 889#define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S) 890 891#define TXPKT_CSUM_TYPE_S 40 892#define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S) 893 894#define TXPKT_VLAN_S 44 895#define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S) 896 897#define TXPKT_VLAN_VLD_S 60 898#define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S) 899#define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL) 900 901#define TXPKT_IPCSUM_DIS_S 62 902#define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S) 903#define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL) 904 905#define TXPKT_L4CSUM_DIS_S 63 906#define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S) 907#define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL) 908 909struct cpl_tx_pkt_lso_core { 910 __be32 lso_ctrl; 911 __be16 ipid_ofst; 912 __be16 mss; 913 __be32 seqno_offset; 914 __be32 len; 915 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 916}; 917 918/* cpl_tx_pkt_lso_core.lso_ctrl fields */ 919#define LSO_TCPHDR_LEN_S 0 920#define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S) 921 922#define LSO_IPHDR_LEN_S 4 923#define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S) 924 925#define LSO_ETHHDR_LEN_S 16 926#define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S) 927 928#define LSO_IPV6_S 20 929#define LSO_IPV6_V(x) ((x) << LSO_IPV6_S) 930#define LSO_IPV6_F LSO_IPV6_V(1U) 931 932#define LSO_LAST_SLICE_S 22 933#define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S) 934#define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U) 935 936#define LSO_FIRST_SLICE_S 23 937#define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S) 938#define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U) 939 940#define LSO_OPCODE_S 24 941#define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S) 942 943#define LSO_T5_XFER_SIZE_S 0 944#define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S) 945 946struct cpl_tx_pkt_lso { 947 WR_HDR; 948 struct cpl_tx_pkt_lso_core c; 949 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 950}; 951 952struct cpl_iscsi_hdr { 953 union opcode_tid ot; 954 __be16 pdu_len_ddp; 955 __be16 len; 956 __be32 seq; 957 __be16 urg; 958 u8 rsvd; 959 u8 status; 960}; 961 962/* cpl_iscsi_hdr.pdu_len_ddp fields */ 963#define ISCSI_PDU_LEN_S 0 964#define ISCSI_PDU_LEN_M 0x7FFF 965#define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S) 966#define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M) 967 968#define ISCSI_DDP_S 15 969#define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S) 970#define ISCSI_DDP_F ISCSI_DDP_V(1U) 971 972struct cpl_rx_data_ddp { 973 union opcode_tid ot; 974 __be16 urg; 975 __be16 len; 976 __be32 seq; 977 union { 978 __be32 nxt_seq; 979 __be32 ddp_report; 980 }; 981 __be32 ulp_crc; 982 __be32 ddpvld; 983}; 984 985#define cpl_rx_iscsi_ddp cpl_rx_data_ddp 986 987struct cpl_iscsi_data { 988 union opcode_tid ot; 989 __u8 rsvd0[2]; 990 __be16 len; 991 __be32 seq; 992 __be16 urg; 993 __u8 rsvd1; 994 __u8 status; 995}; 996 997struct cpl_rx_iscsi_cmp { 998 union opcode_tid ot; 999 __be16 pdu_len_ddp; 1000 __be16 len; 1001 __be32 seq; 1002 __be16 urg; 1003 __u8 rsvd; 1004 __u8 status; 1005 __be32 ulp_crc; 1006 __be32 ddpvld; 1007}; 1008 1009struct cpl_tx_data_iso { 1010 __be32 op_to_scsi; 1011 __u8 reserved1; 1012 __u8 ahs_len; 1013 __be16 mpdu; 1014 __be32 burst_size; 1015 __be32 len; 1016 __be32 reserved2_seglen_offset; 1017 __be32 datasn_offset; 1018 __be32 buffer_offset; 1019 __be32 reserved3; 1020 1021 /* encapsulated CPL_TX_DATA follows here */ 1022}; 1023 1024/* cpl_tx_data_iso.op_to_scsi fields */ 1025#define CPL_TX_DATA_ISO_OP_S 24 1026#define CPL_TX_DATA_ISO_OP_M 0xff 1027#define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S) 1028#define CPL_TX_DATA_ISO_OP_G(x) \ 1029 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M) 1030 1031#define CPL_TX_DATA_ISO_FIRST_S 23 1032#define CPL_TX_DATA_ISO_FIRST_M 0x1 1033#define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S) 1034#define CPL_TX_DATA_ISO_FIRST_G(x) \ 1035 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M) 1036#define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U) 1037 1038#define CPL_TX_DATA_ISO_LAST_S 22 1039#define CPL_TX_DATA_ISO_LAST_M 0x1 1040#define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S) 1041#define CPL_TX_DATA_ISO_LAST_G(x) \ 1042 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M) 1043#define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U) 1044 1045#define CPL_TX_DATA_ISO_CPLHDRLEN_S 21 1046#define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1 1047#define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S) 1048#define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \ 1049 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M) 1050#define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U) 1051 1052#define CPL_TX_DATA_ISO_HDRCRC_S 20 1053#define CPL_TX_DATA_ISO_HDRCRC_M 0x1 1054#define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S) 1055#define CPL_TX_DATA_ISO_HDRCRC_G(x) \ 1056 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M) 1057#define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U) 1058 1059#define CPL_TX_DATA_ISO_PLDCRC_S 19 1060#define CPL_TX_DATA_ISO_PLDCRC_M 0x1 1061#define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S) 1062#define CPL_TX_DATA_ISO_PLDCRC_G(x) \ 1063 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M) 1064#define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U) 1065 1066#define CPL_TX_DATA_ISO_IMMEDIATE_S 18 1067#define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1 1068#define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S) 1069#define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \ 1070 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M) 1071#define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U) 1072 1073#define CPL_TX_DATA_ISO_SCSI_S 16 1074#define CPL_TX_DATA_ISO_SCSI_M 0x3 1075#define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S) 1076#define CPL_TX_DATA_ISO_SCSI_G(x) \ 1077 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M) 1078 1079/* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1080#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0 1081#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff 1082#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \ 1083 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) 1084#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \ 1085 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \ 1086 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M) 1087 1088struct cpl_rx_data { 1089 union opcode_tid ot; 1090 __be16 rsvd; 1091 __be16 len; 1092 __be32 seq; 1093 __be16 urg; 1094#if defined(__LITTLE_ENDIAN_BITFIELD) 1095 u8 dack_mode:2; 1096 u8 psh:1; 1097 u8 heartbeat:1; 1098 u8 ddp_off:1; 1099 u8 :3; 1100#else 1101 u8 :3; 1102 u8 ddp_off:1; 1103 u8 heartbeat:1; 1104 u8 psh:1; 1105 u8 dack_mode:2; 1106#endif 1107 u8 status; 1108}; 1109 1110struct cpl_rx_data_ack { 1111 WR_HDR; 1112 union opcode_tid ot; 1113 __be32 credit_dack; 1114}; 1115 1116/* cpl_rx_data_ack.ack_seq fields */ 1117#define RX_CREDITS_S 0 1118#define RX_CREDITS_V(x) ((x) << RX_CREDITS_S) 1119 1120#define RX_FORCE_ACK_S 28 1121#define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S) 1122#define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U) 1123 1124#define RX_DACK_MODE_S 29 1125#define RX_DACK_MODE_M 0x3 1126#define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S) 1127#define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M) 1128 1129#define RX_DACK_CHANGE_S 31 1130#define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S) 1131#define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U) 1132 1133struct cpl_rx_pkt { 1134 struct rss_header rsshdr; 1135 u8 opcode; 1136#if defined(__LITTLE_ENDIAN_BITFIELD) 1137 u8 iff:4; 1138 u8 csum_calc:1; 1139 u8 ipmi_pkt:1; 1140 u8 vlan_ex:1; 1141 u8 ip_frag:1; 1142#else 1143 u8 ip_frag:1; 1144 u8 vlan_ex:1; 1145 u8 ipmi_pkt:1; 1146 u8 csum_calc:1; 1147 u8 iff:4; 1148#endif 1149 __be16 csum; 1150 __be16 vlan; 1151 __be16 len; 1152 __be32 l2info; 1153 __be16 hdr_len; 1154 __be16 err_vec; 1155}; 1156 1157#define RX_T6_ETHHDR_LEN_M 0xFF 1158#define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M) 1159 1160#define RXF_PSH_S 20 1161#define RXF_PSH_V(x) ((x) << RXF_PSH_S) 1162#define RXF_PSH_F RXF_PSH_V(1U) 1163 1164#define RXF_SYN_S 21 1165#define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1166#define RXF_SYN_F RXF_SYN_V(1U) 1167 1168#define RXF_UDP_S 22 1169#define RXF_UDP_V(x) ((x) << RXF_UDP_S) 1170#define RXF_UDP_F RXF_UDP_V(1U) 1171 1172#define RXF_TCP_S 23 1173#define RXF_TCP_V(x) ((x) << RXF_TCP_S) 1174#define RXF_TCP_F RXF_TCP_V(1U) 1175 1176#define RXF_IP_S 24 1177#define RXF_IP_V(x) ((x) << RXF_IP_S) 1178#define RXF_IP_F RXF_IP_V(1U) 1179 1180#define RXF_IP6_S 25 1181#define RXF_IP6_V(x) ((x) << RXF_IP6_S) 1182#define RXF_IP6_F RXF_IP6_V(1U) 1183 1184#define RXF_SYN_COOKIE_S 26 1185#define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S) 1186#define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U) 1187 1188#define RXF_FCOE_S 26 1189#define RXF_FCOE_V(x) ((x) << RXF_FCOE_S) 1190#define RXF_FCOE_F RXF_FCOE_V(1U) 1191 1192#define RXF_LRO_S 27 1193#define RXF_LRO_V(x) ((x) << RXF_LRO_S) 1194#define RXF_LRO_F RXF_LRO_V(1U) 1195 1196/* rx_pkt.l2info fields */ 1197#define RX_ETHHDR_LEN_S 0 1198#define RX_ETHHDR_LEN_M 0x1F 1199#define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S) 1200#define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M) 1201 1202#define RX_T5_ETHHDR_LEN_S 0 1203#define RX_T5_ETHHDR_LEN_M 0x3F 1204#define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S) 1205#define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M) 1206 1207#define RX_MACIDX_S 8 1208#define RX_MACIDX_M 0x1FF 1209#define RX_MACIDX_V(x) ((x) << RX_MACIDX_S) 1210#define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M) 1211 1212#define RXF_SYN_S 21 1213#define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1214#define RXF_SYN_F RXF_SYN_V(1U) 1215 1216#define RX_CHAN_S 28 1217#define RX_CHAN_M 0xF 1218#define RX_CHAN_V(x) ((x) << RX_CHAN_S) 1219#define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M) 1220 1221/* rx_pkt.hdr_len fields */ 1222#define RX_TCPHDR_LEN_S 0 1223#define RX_TCPHDR_LEN_M 0x3F 1224#define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S) 1225#define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M) 1226 1227#define RX_IPHDR_LEN_S 6 1228#define RX_IPHDR_LEN_M 0x3FF 1229#define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S) 1230#define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M) 1231 1232/* rx_pkt.err_vec fields */ 1233#define RXERR_CSUM_S 13 1234#define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S) 1235#define RXERR_CSUM_F RXERR_CSUM_V(1U) 1236 1237#define T6_COMPR_RXERR_LEN_S 1 1238#define T6_COMPR_RXERR_LEN_V(x) ((x) << T6_COMPR_RXERR_LEN_S) 1239#define T6_COMPR_RXERR_LEN_F T6_COMPR_RXERR_LEN_V(1U) 1240 1241#define T6_COMPR_RXERR_VEC_S 0 1242#define T6_COMPR_RXERR_VEC_M 0x3F 1243#define T6_COMPR_RXERR_VEC_V(x) ((x) << T6_COMPR_RXERR_LEN_S) 1244#define T6_COMPR_RXERR_VEC_G(x) \ 1245 (((x) >> T6_COMPR_RXERR_VEC_S) & T6_COMPR_RXERR_VEC_M) 1246 1247/* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 1248#define T6_COMPR_RXERR_SUM_S 4 1249#define T6_COMPR_RXERR_SUM_V(x) ((x) << T6_COMPR_RXERR_SUM_S) 1250#define T6_COMPR_RXERR_SUM_F T6_COMPR_RXERR_SUM_V(1U) 1251 1252#define T6_RX_TNLHDR_LEN_S 8 1253#define T6_RX_TNLHDR_LEN_M 0xFF 1254#define T6_RX_TNLHDR_LEN_V(x) ((x) << T6_RX_TNLHDR_LEN_S) 1255#define T6_RX_TNLHDR_LEN_G(x) (((x) >> T6_RX_TNLHDR_LEN_S) & T6_RX_TNLHDR_LEN_M) 1256 1257struct cpl_trace_pkt { 1258 u8 opcode; 1259 u8 intf; 1260#if defined(__LITTLE_ENDIAN_BITFIELD) 1261 u8 runt:4; 1262 u8 filter_hit:4; 1263 u8 :6; 1264 u8 err:1; 1265 u8 trunc:1; 1266#else 1267 u8 filter_hit:4; 1268 u8 runt:4; 1269 u8 trunc:1; 1270 u8 err:1; 1271 u8 :6; 1272#endif 1273 __be16 rsvd; 1274 __be16 len; 1275 __be64 tstamp; 1276}; 1277 1278struct cpl_t5_trace_pkt { 1279 __u8 opcode; 1280 __u8 intf; 1281#if defined(__LITTLE_ENDIAN_BITFIELD) 1282 __u8 runt:4; 1283 __u8 filter_hit:4; 1284 __u8:6; 1285 __u8 err:1; 1286 __u8 trunc:1; 1287#else 1288 __u8 filter_hit:4; 1289 __u8 runt:4; 1290 __u8 trunc:1; 1291 __u8 err:1; 1292 __u8:6; 1293#endif 1294 __be16 rsvd; 1295 __be16 len; 1296 __be64 tstamp; 1297 __be64 rsvd1; 1298}; 1299 1300struct cpl_l2t_write_req { 1301 WR_HDR; 1302 union opcode_tid ot; 1303 __be16 params; 1304 __be16 l2t_idx; 1305 __be16 vlan; 1306 u8 dst_mac[6]; 1307}; 1308 1309/* cpl_l2t_write_req.params fields */ 1310#define L2T_W_INFO_S 2 1311#define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S) 1312 1313#define L2T_W_PORT_S 8 1314#define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S) 1315 1316#define L2T_W_NOREPLY_S 15 1317#define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S) 1318#define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U) 1319 1320#define CPL_L2T_VLAN_NONE 0xfff 1321 1322struct cpl_l2t_write_rpl { 1323 union opcode_tid ot; 1324 u8 status; 1325 u8 rsvd[3]; 1326}; 1327 1328struct cpl_smt_write_req { 1329 WR_HDR; 1330 union opcode_tid ot; 1331 __be32 params; 1332 __be16 pfvf1; 1333 u8 src_mac1[6]; 1334 __be16 pfvf0; 1335 u8 src_mac0[6]; 1336}; 1337 1338struct cpl_t6_smt_write_req { 1339 WR_HDR; 1340 union opcode_tid ot; 1341 __be32 params; 1342 __be64 tag; 1343 __be16 pfvf0; 1344 u8 src_mac0[6]; 1345 __be32 local_ip; 1346 __be32 rsvd; 1347}; 1348 1349struct cpl_smt_write_rpl { 1350 union opcode_tid ot; 1351 u8 status; 1352 u8 rsvd[3]; 1353}; 1354 1355/* cpl_smt_{read,write}_req.params fields */ 1356#define SMTW_OVLAN_IDX_S 16 1357#define SMTW_OVLAN_IDX_V(x) ((x) << SMTW_OVLAN_IDX_S) 1358 1359#define SMTW_IDX_S 20 1360#define SMTW_IDX_V(x) ((x) << SMTW_IDX_S) 1361 1362#define SMTW_NORPL_S 31 1363#define SMTW_NORPL_V(x) ((x) << SMTW_NORPL_S) 1364#define SMTW_NORPL_F SMTW_NORPL_V(1U) 1365 1366struct cpl_rdma_terminate { 1367 union opcode_tid ot; 1368 __be16 rsvd; 1369 __be16 len; 1370}; 1371 1372struct cpl_sge_egr_update { 1373 __be32 opcode_qid; 1374 __be16 cidx; 1375 __be16 pidx; 1376}; 1377 1378/* cpl_sge_egr_update.ot fields */ 1379#define EGR_QID_S 0 1380#define EGR_QID_M 0x1FFFF 1381#define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M) 1382 1383/* cpl_fw*.type values */ 1384enum { 1385 FW_TYPE_CMD_RPL = 0, 1386 FW_TYPE_WR_RPL = 1, 1387 FW_TYPE_CQE = 2, 1388 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1389 FW_TYPE_RSSCPL = 4, 1390}; 1391 1392struct cpl_fw4_pld { 1393 u8 opcode; 1394 u8 rsvd0[3]; 1395 u8 type; 1396 u8 rsvd1; 1397 __be16 len; 1398 __be64 data; 1399 __be64 rsvd2; 1400}; 1401 1402struct cpl_fw6_pld { 1403 u8 opcode; 1404 u8 rsvd[5]; 1405 __be16 len; 1406 __be64 data[4]; 1407}; 1408 1409struct cpl_fw4_msg { 1410 u8 opcode; 1411 u8 type; 1412 __be16 rsvd0; 1413 __be32 rsvd1; 1414 __be64 data[2]; 1415}; 1416 1417struct cpl_fw4_ack { 1418 union opcode_tid ot; 1419 u8 credits; 1420 u8 rsvd0[2]; 1421 u8 seq_vld; 1422 __be32 snd_nxt; 1423 __be32 snd_una; 1424 __be64 rsvd1; 1425}; 1426 1427enum { 1428 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 1429 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 1430 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 1431}; 1432 1433#define CPL_FW4_ACK_FLOWID_S 0 1434#define CPL_FW4_ACK_FLOWID_M 0xffffff 1435#define CPL_FW4_ACK_FLOWID_G(x) \ 1436 (((x) >> CPL_FW4_ACK_FLOWID_S) & CPL_FW4_ACK_FLOWID_M) 1437 1438struct cpl_fw6_msg { 1439 u8 opcode; 1440 u8 type; 1441 __be16 rsvd0; 1442 __be32 rsvd1; 1443 __be64 data[4]; 1444}; 1445 1446/* cpl_fw6_msg.type values */ 1447enum { 1448 FW6_TYPE_CMD_RPL = 0, 1449 FW6_TYPE_WR_RPL = 1, 1450 FW6_TYPE_CQE = 2, 1451 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1452 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 1453}; 1454 1455struct cpl_fw6_msg_ofld_connection_wr_rpl { 1456 __u64 cookie; 1457 __be32 tid; /* or atid in case of active failure */ 1458 __u8 t_state; 1459 __u8 retval; 1460 __u8 rsvd[2]; 1461}; 1462 1463struct cpl_tx_data { 1464 union opcode_tid ot; 1465 __be32 len; 1466 __be32 rsvd; 1467 __be32 flags; 1468}; 1469 1470/* cpl_tx_data.flags field */ 1471#define TX_FORCE_S 13 1472#define TX_FORCE_V(x) ((x) << TX_FORCE_S) 1473 1474#define TX_DATA_MSS_S 16 1475#define TX_DATA_MSS_M 0xFFFF 1476#define TX_DATA_MSS_V(x) ((x) << TX_DATA_MSS_S) 1477#define TX_DATA_MSS_G(x) (((x) >> TX_DATA_MSS_S) & TX_DATA_MSS_M) 1478 1479#define TX_LENGTH_S 0 1480#define TX_LENGTH_M 0xFFFF 1481#define TX_LENGTH_V(x) ((x) << TX_LENGTH_S) 1482#define TX_LENGTH_G(x) (((x) >> TX_LENGTH_S) & TX_LENGTH_M) 1483 1484#define T6_TX_FORCE_S 20 1485#define T6_TX_FORCE_V(x) ((x) << T6_TX_FORCE_S) 1486#define T6_TX_FORCE_F T6_TX_FORCE_V(1U) 1487 1488#define TX_URG_S 16 1489#define TX_URG_V(x) ((x) << TX_URG_S) 1490 1491#define TX_SHOVE_S 14 1492#define TX_SHOVE_V(x) ((x) << TX_SHOVE_S) 1493#define TX_SHOVE_F TX_SHOVE_V(1U) 1494 1495#define TX_BYPASS_S 21 1496#define TX_BYPASS_V(x) ((x) << TX_BYPASS_S) 1497#define TX_BYPASS_F TX_BYPASS_V(1U) 1498 1499#define TX_PUSH_S 22 1500#define TX_PUSH_V(x) ((x) << TX_PUSH_S) 1501#define TX_PUSH_F TX_PUSH_V(1U) 1502 1503#define TX_ULP_MODE_S 10 1504#define TX_ULP_MODE_M 0x7 1505#define TX_ULP_MODE_V(x) ((x) << TX_ULP_MODE_S) 1506#define TX_ULP_MODE_G(x) (((x) >> TX_ULP_MODE_S) & TX_ULP_MODE_M) 1507 1508enum { 1509 ULP_TX_MEM_READ = 2, 1510 ULP_TX_MEM_WRITE = 3, 1511 ULP_TX_PKT = 4 1512}; 1513 1514enum { 1515 ULP_TX_SC_NOOP = 0x80, 1516 ULP_TX_SC_IMM = 0x81, 1517 ULP_TX_SC_DSGL = 0x82, 1518 ULP_TX_SC_ISGL = 0x83, 1519 ULP_TX_SC_MEMRD = 0x86 1520}; 1521 1522#define ULPTX_CMD_S 24 1523#define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1524 1525#define ULPTX_LEN16_S 0 1526#define ULPTX_LEN16_M 0xFF 1527#define ULPTX_LEN16_V(x) ((x) << ULPTX_LEN16_S) 1528 1529#define ULP_TX_SC_MORE_S 23 1530#define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S) 1531#define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U) 1532 1533struct ulptx_sge_pair { 1534 __be32 len[2]; 1535 __be64 addr[2]; 1536}; 1537 1538struct ulptx_sgl { 1539 __be32 cmd_nsge; 1540 __be32 len0; 1541 __be64 addr0; 1542 struct ulptx_sge_pair sge[]; 1543}; 1544 1545struct ulptx_idata { 1546 __be32 cmd_more; 1547 __be32 len; 1548}; 1549 1550struct ulp_txpkt { 1551 __be32 cmd_dest; 1552 __be32 len; 1553}; 1554 1555#define ULPTX_CMD_S 24 1556#define ULPTX_CMD_M 0xFF 1557#define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1558 1559#define ULPTX_NSGE_S 0 1560#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1561 1562#define ULPTX_MORE_S 23 1563#define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S) 1564#define ULPTX_MORE_F ULPTX_MORE_V(1U) 1565 1566#define ULP_TXPKT_DEST_S 16 1567#define ULP_TXPKT_DEST_M 0x3 1568#define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S) 1569 1570#define ULP_TXPKT_FID_S 4 1571#define ULP_TXPKT_FID_M 0x7ff 1572#define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S) 1573 1574#define ULP_TXPKT_RO_S 3 1575#define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S) 1576#define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U) 1577 1578enum cpl_tx_tnl_lso_type { 1579 TX_TNL_TYPE_OPAQUE, 1580 TX_TNL_TYPE_NVGRE, 1581 TX_TNL_TYPE_VXLAN, 1582 TX_TNL_TYPE_GENEVE, 1583}; 1584 1585struct cpl_tx_tnl_lso { 1586 __be32 op_to_IpIdSplitOut; 1587 __be16 IpIdOffsetOut; 1588 __be16 UdpLenSetOut_to_TnlHdrLen; 1589 __be64 r1; 1590 __be32 Flow_to_TcpHdrLen; 1591 __be16 IpIdOffset; 1592 __be16 IpIdSplit_to_Mss; 1593 __be32 TCPSeqOffset; 1594 __be32 EthLenOffset_Size; 1595 /* encapsulated CPL (TX_PKT_XT) follows here */ 1596}; 1597 1598#define CPL_TX_TNL_LSO_OPCODE_S 24 1599#define CPL_TX_TNL_LSO_OPCODE_M 0xff 1600#define CPL_TX_TNL_LSO_OPCODE_V(x) ((x) << CPL_TX_TNL_LSO_OPCODE_S) 1601#define CPL_TX_TNL_LSO_OPCODE_G(x) \ 1602 (((x) >> CPL_TX_TNL_LSO_OPCODE_S) & CPL_TX_TNL_LSO_OPCODE_M) 1603 1604#define CPL_TX_TNL_LSO_FIRST_S 23 1605#define CPL_TX_TNL_LSO_FIRST_M 0x1 1606#define CPL_TX_TNL_LSO_FIRST_V(x) ((x) << CPL_TX_TNL_LSO_FIRST_S) 1607#define CPL_TX_TNL_LSO_FIRST_G(x) \ 1608 (((x) >> CPL_TX_TNL_LSO_FIRST_S) & CPL_TX_TNL_LSO_FIRST_M) 1609#define CPL_TX_TNL_LSO_FIRST_F CPL_TX_TNL_LSO_FIRST_V(1U) 1610 1611#define CPL_TX_TNL_LSO_LAST_S 22 1612#define CPL_TX_TNL_LSO_LAST_M 0x1 1613#define CPL_TX_TNL_LSO_LAST_V(x) ((x) << CPL_TX_TNL_LSO_LAST_S) 1614#define CPL_TX_TNL_LSO_LAST_G(x) \ 1615 (((x) >> CPL_TX_TNL_LSO_LAST_S) & CPL_TX_TNL_LSO_LAST_M) 1616#define CPL_TX_TNL_LSO_LAST_F CPL_TX_TNL_LSO_LAST_V(1U) 1617 1618#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_S 21 1619#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_M 0x1 1620#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_V(x) \ 1621 ((x) << CPL_TX_TNL_LSO_ETHHDRLENXOUT_S) 1622#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_G(x) \ 1623 (((x) >> CPL_TX_TNL_LSO_ETHHDRLENXOUT_S) & \ 1624 CPL_TX_TNL_LSO_ETHHDRLENXOUT_M) 1625#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_F CPL_TX_TNL_LSO_ETHHDRLENXOUT_V(1U) 1626 1627#define CPL_TX_TNL_LSO_IPV6OUT_S 20 1628#define CPL_TX_TNL_LSO_IPV6OUT_M 0x1 1629#define CPL_TX_TNL_LSO_IPV6OUT_V(x) ((x) << CPL_TX_TNL_LSO_IPV6OUT_S) 1630#define CPL_TX_TNL_LSO_IPV6OUT_G(x) \ 1631 (((x) >> CPL_TX_TNL_LSO_IPV6OUT_S) & CPL_TX_TNL_LSO_IPV6OUT_M) 1632#define CPL_TX_TNL_LSO_IPV6OUT_F CPL_TX_TNL_LSO_IPV6OUT_V(1U) 1633 1634#define CPL_TX_TNL_LSO_ETHHDRLEN_S 16 1635#define CPL_TX_TNL_LSO_ETHHDRLEN_M 0xf 1636#define CPL_TX_TNL_LSO_ETHHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_ETHHDRLEN_S) 1637#define CPL_TX_TNL_LSO_ETHHDRLEN_G(x) \ 1638 (((x) >> CPL_TX_TNL_LSO_ETHHDRLEN_S) & CPL_TX_TNL_LSO_ETHHDRLEN_M) 1639 1640#define CPL_TX_TNL_LSO_IPHDRLEN_S 4 1641#define CPL_TX_TNL_LSO_IPHDRLEN_M 0xfff 1642#define CPL_TX_TNL_LSO_IPHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRLEN_S) 1643#define CPL_TX_TNL_LSO_IPHDRLEN_G(x) \ 1644 (((x) >> CPL_TX_TNL_LSO_IPHDRLEN_S) & CPL_TX_TNL_LSO_IPHDRLEN_M) 1645 1646#define CPL_TX_TNL_LSO_TCPHDRLEN_S 0 1647#define CPL_TX_TNL_LSO_TCPHDRLEN_M 0xf 1648#define CPL_TX_TNL_LSO_TCPHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TCPHDRLEN_S) 1649#define CPL_TX_TNL_LSO_TCPHDRLEN_G(x) \ 1650 (((x) >> CPL_TX_TNL_LSO_TCPHDRLEN_S) & CPL_TX_TNL_LSO_TCPHDRLEN_M) 1651 1652#define CPL_TX_TNL_LSO_MSS_S 0 1653#define CPL_TX_TNL_LSO_MSS_M 0x3fff 1654#define CPL_TX_TNL_LSO_MSS_V(x) ((x) << CPL_TX_TNL_LSO_MSS_S) 1655#define CPL_TX_TNL_LSO_MSS_G(x) \ 1656 (((x) >> CPL_TX_TNL_LSO_MSS_S) & CPL_TX_TNL_LSO_MSS_M) 1657 1658#define CPL_TX_TNL_LSO_SIZE_S 0 1659#define CPL_TX_TNL_LSO_SIZE_M 0xfffffff 1660#define CPL_TX_TNL_LSO_SIZE_V(x) ((x) << CPL_TX_TNL_LSO_SIZE_S) 1661#define CPL_TX_TNL_LSO_SIZE_G(x) \ 1662 (((x) >> CPL_TX_TNL_LSO_SIZE_S) & CPL_TX_TNL_LSO_SIZE_M) 1663 1664#define CPL_TX_TNL_LSO_ETHHDRLENOUT_S 16 1665#define CPL_TX_TNL_LSO_ETHHDRLENOUT_M 0xf 1666#define CPL_TX_TNL_LSO_ETHHDRLENOUT_V(x) \ 1667 ((x) << CPL_TX_TNL_LSO_ETHHDRLENOUT_S) 1668#define CPL_TX_TNL_LSO_ETHHDRLENOUT_G(x) \ 1669 (((x) >> CPL_TX_TNL_LSO_ETHHDRLENOUT_S) & CPL_TX_TNL_LSO_ETHHDRLENOUT_M) 1670 1671#define CPL_TX_TNL_LSO_IPHDRLENOUT_S 4 1672#define CPL_TX_TNL_LSO_IPHDRLENOUT_M 0xfff 1673#define CPL_TX_TNL_LSO_IPHDRLENOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRLENOUT_S) 1674#define CPL_TX_TNL_LSO_IPHDRLENOUT_G(x) \ 1675 (((x) >> CPL_TX_TNL_LSO_IPHDRLENOUT_S) & CPL_TX_TNL_LSO_IPHDRLENOUT_M) 1676 1677#define CPL_TX_TNL_LSO_IPHDRCHKOUT_S 3 1678#define CPL_TX_TNL_LSO_IPHDRCHKOUT_M 0x1 1679#define CPL_TX_TNL_LSO_IPHDRCHKOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRCHKOUT_S) 1680#define CPL_TX_TNL_LSO_IPHDRCHKOUT_G(x) \ 1681 (((x) >> CPL_TX_TNL_LSO_IPHDRCHKOUT_S) & CPL_TX_TNL_LSO_IPHDRCHKOUT_M) 1682#define CPL_TX_TNL_LSO_IPHDRCHKOUT_F CPL_TX_TNL_LSO_IPHDRCHKOUT_V(1U) 1683 1684#define CPL_TX_TNL_LSO_IPLENSETOUT_S 2 1685#define CPL_TX_TNL_LSO_IPLENSETOUT_M 0x1 1686#define CPL_TX_TNL_LSO_IPLENSETOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPLENSETOUT_S) 1687#define CPL_TX_TNL_LSO_IPLENSETOUT_G(x) \ 1688 (((x) >> CPL_TX_TNL_LSO_IPLENSETOUT_S) & CPL_TX_TNL_LSO_IPLENSETOUT_M) 1689#define CPL_TX_TNL_LSO_IPLENSETOUT_F CPL_TX_TNL_LSO_IPLENSETOUT_V(1U) 1690 1691#define CPL_TX_TNL_LSO_IPIDINCOUT_S 1 1692#define CPL_TX_TNL_LSO_IPIDINCOUT_M 0x1 1693#define CPL_TX_TNL_LSO_IPIDINCOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPIDINCOUT_S) 1694#define CPL_TX_TNL_LSO_IPIDINCOUT_G(x) \ 1695 (((x) >> CPL_TX_TNL_LSO_IPIDINCOUT_S) & CPL_TX_TNL_LSO_IPIDINCOUT_M) 1696#define CPL_TX_TNL_LSO_IPIDINCOUT_F CPL_TX_TNL_LSO_IPIDINCOUT_V(1U) 1697 1698#define CPL_TX_TNL_LSO_UDPCHKCLROUT_S 14 1699#define CPL_TX_TNL_LSO_UDPCHKCLROUT_M 0x1 1700#define CPL_TX_TNL_LSO_UDPCHKCLROUT_V(x) \ 1701 ((x) << CPL_TX_TNL_LSO_UDPCHKCLROUT_S) 1702#define CPL_TX_TNL_LSO_UDPCHKCLROUT_G(x) \ 1703 (((x) >> CPL_TX_TNL_LSO_UDPCHKCLROUT_S) & \ 1704 CPL_TX_TNL_LSO_UDPCHKCLROUT_M) 1705#define CPL_TX_TNL_LSO_UDPCHKCLROUT_F CPL_TX_TNL_LSO_UDPCHKCLROUT_V(1U) 1706 1707#define CPL_TX_TNL_LSO_UDPLENSETOUT_S 15 1708#define CPL_TX_TNL_LSO_UDPLENSETOUT_M 0x1 1709#define CPL_TX_TNL_LSO_UDPLENSETOUT_V(x) \ 1710 ((x) << CPL_TX_TNL_LSO_UDPLENSETOUT_S) 1711#define CPL_TX_TNL_LSO_UDPLENSETOUT_G(x) \ 1712 (((x) >> CPL_TX_TNL_LSO_UDPLENSETOUT_S) & \ 1713 CPL_TX_TNL_LSO_UDPLENSETOUT_M) 1714#define CPL_TX_TNL_LSO_UDPLENSETOUT_F CPL_TX_TNL_LSO_UDPLENSETOUT_V(1U) 1715 1716#define CPL_TX_TNL_LSO_TNLTYPE_S 12 1717#define CPL_TX_TNL_LSO_TNLTYPE_M 0x3 1718#define CPL_TX_TNL_LSO_TNLTYPE_V(x) ((x) << CPL_TX_TNL_LSO_TNLTYPE_S) 1719#define CPL_TX_TNL_LSO_TNLTYPE_G(x) \ 1720 (((x) >> CPL_TX_TNL_LSO_TNLTYPE_S) & CPL_TX_TNL_LSO_TNLTYPE_M) 1721 1722#define S_CPL_TX_TNL_LSO_ETHHDRLEN 16 1723#define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf 1724#define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN) 1725#define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \ 1726 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN) 1727 1728#define CPL_TX_TNL_LSO_TNLHDRLEN_S 0 1729#define CPL_TX_TNL_LSO_TNLHDRLEN_M 0xfff 1730#define CPL_TX_TNL_LSO_TNLHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TNLHDRLEN_S) 1731#define CPL_TX_TNL_LSO_TNLHDRLEN_G(x) \ 1732 (((x) >> CPL_TX_TNL_LSO_TNLHDRLEN_S) & CPL_TX_TNL_LSO_TNLHDRLEN_M) 1733 1734#define CPL_TX_TNL_LSO_IPV6_S 20 1735#define CPL_TX_TNL_LSO_IPV6_M 0x1 1736#define CPL_TX_TNL_LSO_IPV6_V(x) ((x) << CPL_TX_TNL_LSO_IPV6_S) 1737#define CPL_TX_TNL_LSO_IPV6_G(x) \ 1738 (((x) >> CPL_TX_TNL_LSO_IPV6_S) & CPL_TX_TNL_LSO_IPV6_M) 1739#define CPL_TX_TNL_LSO_IPV6_F CPL_TX_TNL_LSO_IPV6_V(1U) 1740 1741#define ULP_TX_SC_MORE_S 23 1742#define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S) 1743#define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U) 1744 1745struct ulp_mem_io { 1746 WR_HDR; 1747 __be32 cmd; 1748 __be32 len16; /* command length */ 1749 __be32 dlen; /* data length in 32-byte units */ 1750 __be32 lock_addr; 1751}; 1752 1753#define ULP_MEMIO_LOCK_S 31 1754#define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S) 1755#define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U) 1756 1757/* additional ulp_mem_io.cmd fields */ 1758#define ULP_MEMIO_ORDER_S 23 1759#define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S) 1760#define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U) 1761 1762#define T5_ULP_MEMIO_IMM_S 23 1763#define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S) 1764#define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U) 1765 1766#define T5_ULP_MEMIO_ORDER_S 22 1767#define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S) 1768#define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U) 1769 1770#define T5_ULP_MEMIO_FID_S 4 1771#define T5_ULP_MEMIO_FID_M 0x7ff 1772#define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S) 1773 1774/* ulp_mem_io.lock_addr fields */ 1775#define ULP_MEMIO_ADDR_S 0 1776#define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S) 1777 1778/* ulp_mem_io.dlen fields */ 1779#define ULP_MEMIO_DATA_LEN_S 0 1780#define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S) 1781 1782#define ULPTX_NSGE_S 0 1783#define ULPTX_NSGE_M 0xFFFF 1784#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1785#define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M) 1786 1787struct ulptx_sc_memrd { 1788 __be32 cmd_to_len; 1789 __be32 addr; 1790}; 1791 1792#define ULP_TXPKT_DATAMODIFY_S 23 1793#define ULP_TXPKT_DATAMODIFY_M 0x1 1794#define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S) 1795#define ULP_TXPKT_DATAMODIFY_G(x) \ 1796 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M) 1797#define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U) 1798 1799#define ULP_TXPKT_CHANNELID_S 22 1800#define ULP_TXPKT_CHANNELID_M 0x1 1801#define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S) 1802#define ULP_TXPKT_CHANNELID_G(x) \ 1803 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M) 1804#define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U) 1805 1806#define SCMD_SEQ_NO_CTRL_S 29 1807#define SCMD_SEQ_NO_CTRL_M 0x3 1808#define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S) 1809#define SCMD_SEQ_NO_CTRL_G(x) \ 1810 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M) 1811 1812/* StsFieldPrsnt- Status field at the end of the TLS PDU */ 1813#define SCMD_STATUS_PRESENT_S 28 1814#define SCMD_STATUS_PRESENT_M 0x1 1815#define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S) 1816#define SCMD_STATUS_PRESENT_G(x) \ 1817 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M) 1818#define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U) 1819 1820/* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 1821 * 3-15: Reserved. 1822 */ 1823#define SCMD_PROTO_VERSION_S 24 1824#define SCMD_PROTO_VERSION_M 0xf 1825#define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S) 1826#define SCMD_PROTO_VERSION_G(x) \ 1827 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M) 1828 1829/* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 1830#define SCMD_ENC_DEC_CTRL_S 23 1831#define SCMD_ENC_DEC_CTRL_M 0x1 1832#define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S) 1833#define SCMD_ENC_DEC_CTRL_G(x) \ 1834 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M) 1835#define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U) 1836 1837/* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 1838#define SCMD_CIPH_AUTH_SEQ_CTRL_S 22 1839#define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1 1840#define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \ 1841 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S) 1842#define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \ 1843 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M) 1844#define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U) 1845 1846/* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 1847 * 4:Generic-AES, 5-15: Reserved. 1848 */ 1849#define SCMD_CIPH_MODE_S 18 1850#define SCMD_CIPH_MODE_M 0xf 1851#define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S) 1852#define SCMD_CIPH_MODE_G(x) \ 1853 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M) 1854 1855/* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 1856 * 4-15: Reserved 1857 */ 1858#define SCMD_AUTH_MODE_S 14 1859#define SCMD_AUTH_MODE_M 0xf 1860#define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S) 1861#define SCMD_AUTH_MODE_G(x) \ 1862 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M) 1863 1864/* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 1865 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 1866 */ 1867#define SCMD_HMAC_CTRL_S 11 1868#define SCMD_HMAC_CTRL_M 0x7 1869#define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S) 1870#define SCMD_HMAC_CTRL_G(x) \ 1871 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M) 1872 1873/* IvSize - IV size in units of 2 bytes */ 1874#define SCMD_IV_SIZE_S 7 1875#define SCMD_IV_SIZE_M 0xf 1876#define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S) 1877#define SCMD_IV_SIZE_G(x) \ 1878 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M) 1879 1880/* NumIVs - Number of IVs */ 1881#define SCMD_NUM_IVS_S 0 1882#define SCMD_NUM_IVS_M 0x7f 1883#define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S) 1884#define SCMD_NUM_IVS_G(x) \ 1885 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M) 1886 1887/* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 1888 * (below) are used as Cid (connection id for debug status), these 1889 * bits are padded to zero for forming the 64 bit 1890 * sequence number for TLS 1891 */ 1892#define SCMD_ENB_DBGID_S 31 1893#define SCMD_ENB_DBGID_M 0x1 1894#define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S) 1895#define SCMD_ENB_DBGID_G(x) \ 1896 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M) 1897 1898/* IV generation in SW. */ 1899#define SCMD_IV_GEN_CTRL_S 30 1900#define SCMD_IV_GEN_CTRL_M 0x1 1901#define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S) 1902#define SCMD_IV_GEN_CTRL_G(x) \ 1903 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M) 1904#define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U) 1905 1906/* More frags */ 1907#define SCMD_MORE_FRAGS_S 20 1908#define SCMD_MORE_FRAGS_M 0x1 1909#define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S) 1910#define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M) 1911 1912/*last frag */ 1913#define SCMD_LAST_FRAG_S 19 1914#define SCMD_LAST_FRAG_M 0x1 1915#define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S) 1916#define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M) 1917 1918/* TlsCompPdu */ 1919#define SCMD_TLS_COMPPDU_S 18 1920#define SCMD_TLS_COMPPDU_M 0x1 1921#define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S) 1922#define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M) 1923 1924/* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 1925#define SCMD_KEY_CTX_INLINE_S 17 1926#define SCMD_KEY_CTX_INLINE_M 0x1 1927#define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S) 1928#define SCMD_KEY_CTX_INLINE_G(x) \ 1929 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M) 1930#define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U) 1931 1932/* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 1933#define SCMD_TLS_FRAG_ENABLE_S 16 1934#define SCMD_TLS_FRAG_ENABLE_M 0x1 1935#define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S) 1936#define SCMD_TLS_FRAG_ENABLE_G(x) \ 1937 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M) 1938#define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U) 1939 1940/* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 1941 * modes, in this case TLS_TX will drop the PDU and only 1942 * send back the MAC bytes. 1943 */ 1944#define SCMD_MAC_ONLY_S 15 1945#define SCMD_MAC_ONLY_M 0x1 1946#define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S) 1947#define SCMD_MAC_ONLY_G(x) \ 1948 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M) 1949#define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U) 1950 1951/* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 1952 * which have complex AAD and IV formations Eg:AES-CCM 1953 */ 1954#define SCMD_AADIVDROP_S 14 1955#define SCMD_AADIVDROP_M 0x1 1956#define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S) 1957#define SCMD_AADIVDROP_G(x) \ 1958 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M) 1959#define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U) 1960 1961/* HdrLength - Length of all headers excluding TLS header 1962 * present before start of crypto PDU/payload. 1963 */ 1964#define SCMD_HDR_LEN_S 0 1965#define SCMD_HDR_LEN_M 0x3fff 1966#define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S) 1967#define SCMD_HDR_LEN_G(x) \ 1968 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M) 1969 1970struct cpl_tx_sec_pdu { 1971 __be32 op_ivinsrtofst; 1972 __be32 pldlen; 1973 __be32 aadstart_cipherstop_hi; 1974 __be32 cipherstop_lo_authinsert; 1975 __be32 seqno_numivs; 1976 __be32 ivgen_hdrlen; 1977 __be64 scmd1; 1978}; 1979 1980#define CPL_TX_SEC_PDU_OPCODE_S 24 1981#define CPL_TX_SEC_PDU_OPCODE_M 0xff 1982#define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S) 1983#define CPL_TX_SEC_PDU_OPCODE_G(x) \ 1984 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M) 1985 1986/* RX Channel Id */ 1987#define CPL_TX_SEC_PDU_RXCHID_S 22 1988#define CPL_TX_SEC_PDU_RXCHID_M 0x1 1989#define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S) 1990#define CPL_TX_SEC_PDU_RXCHID_G(x) \ 1991 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M) 1992#define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U) 1993 1994/* Ack Follows */ 1995#define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21 1996#define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1 1997#define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S) 1998#define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \ 1999 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M) 2000#define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U) 2001 2002/* Loopback bit in cpl_tx_sec_pdu */ 2003#define CPL_TX_SEC_PDU_ULPTXLPBK_S 20 2004#define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1 2005#define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S) 2006#define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \ 2007 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M) 2008#define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U) 2009 2010/* Length of cpl header encapsulated */ 2011#define CPL_TX_SEC_PDU_CPLLEN_S 16 2012#define CPL_TX_SEC_PDU_CPLLEN_M 0xf 2013#define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S) 2014#define CPL_TX_SEC_PDU_CPLLEN_G(x) \ 2015 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M) 2016 2017/* PlaceHolder */ 2018#define CPL_TX_SEC_PDU_PLACEHOLDER_S 10 2019#define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1 2020#define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S) 2021#define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \ 2022 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \ 2023 CPL_TX_SEC_PDU_PLACEHOLDER_M) 2024 2025/* IvInsrtOffset: Insertion location for IV */ 2026#define CPL_TX_SEC_PDU_IVINSRTOFST_S 0 2027#define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff 2028#define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S) 2029#define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \ 2030 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \ 2031 CPL_TX_SEC_PDU_IVINSRTOFST_M) 2032 2033/* AadStartOffset: Offset in bytes for AAD start from 2034 * the first byte following the pkt headers (0-255 bytes) 2035 */ 2036#define CPL_TX_SEC_PDU_AADSTART_S 24 2037#define CPL_TX_SEC_PDU_AADSTART_M 0xff 2038#define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S) 2039#define CPL_TX_SEC_PDU_AADSTART_G(x) \ 2040 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \ 2041 CPL_TX_SEC_PDU_AADSTART_M) 2042 2043/* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 2044 * the pkt headers (0-511 bytes) 2045 */ 2046#define CPL_TX_SEC_PDU_AADSTOP_S 15 2047#define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff 2048#define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S) 2049#define CPL_TX_SEC_PDU_AADSTOP_G(x) \ 2050 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M) 2051 2052/* CipherStartOffset: offset in bytes for encryption/decryption start from the 2053 * first byte following the pkt headers (0-1023 bytes) 2054 */ 2055#define CPL_TX_SEC_PDU_CIPHERSTART_S 5 2056#define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff 2057#define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S) 2058#define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \ 2059 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \ 2060 CPL_TX_SEC_PDU_CIPHERSTART_M) 2061 2062/* CipherStopOffset: offset in bytes for encryption/decryption end 2063 * from end of the payload of this command (0-511 bytes) 2064 */ 2065#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0 2066#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f 2067#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \ 2068 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) 2069#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \ 2070 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \ 2071 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M) 2072 2073#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28 2074#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf 2075#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \ 2076 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) 2077#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \ 2078 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \ 2079 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M) 2080 2081/* AuthStartOffset: offset in bytes for authentication start from 2082 * the first byte following the pkt headers (0-1023) 2083 */ 2084#define CPL_TX_SEC_PDU_AUTHSTART_S 18 2085#define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff 2086#define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S) 2087#define CPL_TX_SEC_PDU_AUTHSTART_G(x) \ 2088 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \ 2089 CPL_TX_SEC_PDU_AUTHSTART_M) 2090 2091/* AuthStopOffset: offset in bytes for authentication 2092 * end from end of the payload of this command (0-511 Bytes) 2093 */ 2094#define CPL_TX_SEC_PDU_AUTHSTOP_S 9 2095#define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff 2096#define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S) 2097#define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \ 2098 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \ 2099 CPL_TX_SEC_PDU_AUTHSTOP_M) 2100 2101/* AuthInsrtOffset: offset in bytes for authentication insertion 2102 * from end of the payload of this command (0-511 bytes) 2103 */ 2104#define CPL_TX_SEC_PDU_AUTHINSERT_S 0 2105#define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff 2106#define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S) 2107#define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \ 2108 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \ 2109 CPL_TX_SEC_PDU_AUTHINSERT_M) 2110 2111struct cpl_rx_phys_dsgl { 2112 __be32 op_to_tid; 2113 __be32 pcirlxorder_to_noofsgentr; 2114 struct rss_header rss_hdr_int; 2115}; 2116 2117#define CPL_RX_PHYS_DSGL_OPCODE_S 24 2118#define CPL_RX_PHYS_DSGL_OPCODE_M 0xff 2119#define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S) 2120#define CPL_RX_PHYS_DSGL_OPCODE_G(x) \ 2121 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M) 2122 2123#define CPL_RX_PHYS_DSGL_ISRDMA_S 23 2124#define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1 2125#define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S) 2126#define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \ 2127 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M) 2128#define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U) 2129 2130#define CPL_RX_PHYS_DSGL_RSVD1_S 20 2131#define CPL_RX_PHYS_DSGL_RSVD1_M 0x7 2132#define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S) 2133#define CPL_RX_PHYS_DSGL_RSVD1_G(x) \ 2134 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \ 2135 CPL_RX_PHYS_DSGL_RSVD1_M) 2136 2137#define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31 2138#define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1 2139#define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \ 2140 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S) 2141#define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \ 2142 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \ 2143 CPL_RX_PHYS_DSGL_PCIRLXORDER_M) 2144#define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U) 2145 2146#define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30 2147#define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1 2148#define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \ 2149 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S) 2150#define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \ 2151 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \ 2152 CPL_RX_PHYS_DSGL_PCINOSNOOP_M) 2153 2154#define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U) 2155 2156#define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29 2157#define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1 2158#define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \ 2159 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S) 2160#define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \ 2161 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \ 2162 CPL_RX_PHYS_DSGL_PCITPHNTENB_M) 2163#define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U) 2164 2165#define CPL_RX_PHYS_DSGL_PCITPHNT_S 27 2166#define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3 2167#define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S) 2168#define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \ 2169 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \ 2170 CPL_RX_PHYS_DSGL_PCITPHNT_M) 2171 2172#define CPL_RX_PHYS_DSGL_DCAID_S 16 2173#define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff 2174#define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S) 2175#define CPL_RX_PHYS_DSGL_DCAID_G(x) \ 2176 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \ 2177 CPL_RX_PHYS_DSGL_DCAID_M) 2178 2179#define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0 2180#define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff 2181#define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \ 2182 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S) 2183#define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \ 2184 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \ 2185 CPL_RX_PHYS_DSGL_NOOFSGENTR_M) 2186 2187struct cpl_rx_mps_pkt { 2188 __be32 op_to_r1_hi; 2189 __be32 r1_lo_length; 2190}; 2191 2192#define CPL_RX_MPS_PKT_OP_S 24 2193#define CPL_RX_MPS_PKT_OP_M 0xff 2194#define CPL_RX_MPS_PKT_OP_V(x) ((x) << CPL_RX_MPS_PKT_OP_S) 2195#define CPL_RX_MPS_PKT_OP_G(x) \ 2196 (((x) >> CPL_RX_MPS_PKT_OP_S) & CPL_RX_MPS_PKT_OP_M) 2197 2198#define CPL_RX_MPS_PKT_TYPE_S 20 2199#define CPL_RX_MPS_PKT_TYPE_M 0xf 2200#define CPL_RX_MPS_PKT_TYPE_V(x) ((x) << CPL_RX_MPS_PKT_TYPE_S) 2201#define CPL_RX_MPS_PKT_TYPE_G(x) \ 2202 (((x) >> CPL_RX_MPS_PKT_TYPE_S) & CPL_RX_MPS_PKT_TYPE_M) 2203 2204enum { 2205 X_CPL_RX_MPS_PKT_TYPE_PAUSE = 1 << 0, 2206 X_CPL_RX_MPS_PKT_TYPE_PPP = 1 << 1, 2207 X_CPL_RX_MPS_PKT_TYPE_QFC = 1 << 2, 2208 X_CPL_RX_MPS_PKT_TYPE_PTP = 1 << 3 2209}; 2210 2211struct cpl_srq_table_req { 2212 WR_HDR; 2213 union opcode_tid ot; 2214 __u8 status; 2215 __u8 rsvd[2]; 2216 __u8 idx; 2217 __be64 rsvd_pdid; 2218 __be32 qlen_qbase; 2219 __be16 cur_msn; 2220 __be16 max_msn; 2221}; 2222 2223struct cpl_srq_table_rpl { 2224 union opcode_tid ot; 2225 __u8 status; 2226 __u8 rsvd[2]; 2227 __u8 idx; 2228 __be64 rsvd_pdid; 2229 __be32 qlen_qbase; 2230 __be16 cur_msn; 2231 __be16 max_msn; 2232}; 2233 2234/* cpl_srq_table_{req,rpl}.params fields */ 2235#define SRQT_QLEN_S 28 2236#define SRQT_QLEN_M 0xF 2237#define SRQT_QLEN_V(x) ((x) << SRQT_QLEN_S) 2238#define SRQT_QLEN_G(x) (((x) >> SRQT_QLEN_S) & SRQT_QLEN_M) 2239 2240#define SRQT_QBASE_S 0 2241#define SRQT_QBASE_M 0x3FFFFFF 2242#define SRQT_QBASE_V(x) ((x) << SRQT_QBASE_S) 2243#define SRQT_QBASE_G(x) (((x) >> SRQT_QBASE_S) & SRQT_QBASE_M) 2244 2245#define SRQT_PDID_S 0 2246#define SRQT_PDID_M 0xFF 2247#define SRQT_PDID_V(x) ((x) << SRQT_PDID_S) 2248#define SRQT_PDID_G(x) (((x) >> SRQT_PDID_S) & SRQT_PDID_M) 2249 2250#define SRQT_IDX_S 0 2251#define SRQT_IDX_M 0xF 2252#define SRQT_IDX_V(x) ((x) << SRQT_IDX_S) 2253#define SRQT_IDX_G(x) (((x) >> SRQT_IDX_S) & SRQT_IDX_M) 2254 2255struct cpl_tx_tls_sfo { 2256 __be32 op_to_seg_len; 2257 __be32 pld_len; 2258 __be32 type_protover; 2259 __be32 r1_lo; 2260 __be32 seqno_numivs; 2261 __be32 ivgen_hdrlen; 2262 __be64 scmd1; 2263}; 2264 2265/* cpl_tx_tls_sfo macros */ 2266#define CPL_TX_TLS_SFO_OPCODE_S 24 2267#define CPL_TX_TLS_SFO_OPCODE_V(x) ((x) << CPL_TX_TLS_SFO_OPCODE_S) 2268 2269#define CPL_TX_TLS_SFO_DATA_TYPE_S 20 2270#define CPL_TX_TLS_SFO_DATA_TYPE_V(x) ((x) << CPL_TX_TLS_SFO_DATA_TYPE_S) 2271 2272#define CPL_TX_TLS_SFO_CPL_LEN_S 16 2273#define CPL_TX_TLS_SFO_CPL_LEN_V(x) ((x) << CPL_TX_TLS_SFO_CPL_LEN_S) 2274 2275#define CPL_TX_TLS_SFO_SEG_LEN_S 0 2276#define CPL_TX_TLS_SFO_SEG_LEN_M 0xffff 2277#define CPL_TX_TLS_SFO_SEG_LEN_V(x) ((x) << CPL_TX_TLS_SFO_SEG_LEN_S) 2278#define CPL_TX_TLS_SFO_SEG_LEN_G(x) \ 2279 (((x) >> CPL_TX_TLS_SFO_SEG_LEN_S) & CPL_TX_TLS_SFO_SEG_LEN_M) 2280 2281#define CPL_TX_TLS_SFO_TYPE_S 24 2282#define CPL_TX_TLS_SFO_TYPE_M 0xff 2283#define CPL_TX_TLS_SFO_TYPE_V(x) ((x) << CPL_TX_TLS_SFO_TYPE_S) 2284#define CPL_TX_TLS_SFO_TYPE_G(x) \ 2285 (((x) >> CPL_TX_TLS_SFO_TYPE_S) & CPL_TX_TLS_SFO_TYPE_M) 2286 2287#define CPL_TX_TLS_SFO_PROTOVER_S 8 2288#define CPL_TX_TLS_SFO_PROTOVER_M 0xffff 2289#define CPL_TX_TLS_SFO_PROTOVER_V(x) ((x) << CPL_TX_TLS_SFO_PROTOVER_S) 2290#define CPL_TX_TLS_SFO_PROTOVER_G(x) \ 2291 (((x) >> CPL_TX_TLS_SFO_PROTOVER_S) & CPL_TX_TLS_SFO_PROTOVER_M) 2292 2293struct cpl_tls_data { 2294 struct rss_header rsshdr; 2295 union opcode_tid ot; 2296 __be32 length_pkd; 2297 __be32 seq; 2298 __be32 r1; 2299}; 2300 2301#define CPL_TLS_DATA_OPCODE_S 24 2302#define CPL_TLS_DATA_OPCODE_M 0xff 2303#define CPL_TLS_DATA_OPCODE_V(x) ((x) << CPL_TLS_DATA_OPCODE_S) 2304#define CPL_TLS_DATA_OPCODE_G(x) \ 2305 (((x) >> CPL_TLS_DATA_OPCODE_S) & CPL_TLS_DATA_OPCODE_M) 2306 2307#define CPL_TLS_DATA_TID_S 0 2308#define CPL_TLS_DATA_TID_M 0xffffff 2309#define CPL_TLS_DATA_TID_V(x) ((x) << CPL_TLS_DATA_TID_S) 2310#define CPL_TLS_DATA_TID_G(x) \ 2311 (((x) >> CPL_TLS_DATA_TID_S) & CPL_TLS_DATA_TID_M) 2312 2313#define CPL_TLS_DATA_LENGTH_S 0 2314#define CPL_TLS_DATA_LENGTH_M 0xffff 2315#define CPL_TLS_DATA_LENGTH_V(x) ((x) << CPL_TLS_DATA_LENGTH_S) 2316#define CPL_TLS_DATA_LENGTH_G(x) \ 2317 (((x) >> CPL_TLS_DATA_LENGTH_S) & CPL_TLS_DATA_LENGTH_M) 2318 2319struct cpl_rx_tls_cmp { 2320 struct rss_header rsshdr; 2321 union opcode_tid ot; 2322 __be32 pdulength_length; 2323 __be32 seq; 2324 __be32 ddp_report; 2325 __be32 r; 2326 __be32 ddp_valid; 2327}; 2328 2329#define CPL_RX_TLS_CMP_OPCODE_S 24 2330#define CPL_RX_TLS_CMP_OPCODE_M 0xff 2331#define CPL_RX_TLS_CMP_OPCODE_V(x) ((x) << CPL_RX_TLS_CMP_OPCODE_S) 2332#define CPL_RX_TLS_CMP_OPCODE_G(x) \ 2333 (((x) >> CPL_RX_TLS_CMP_OPCODE_S) & CPL_RX_TLS_CMP_OPCODE_M) 2334 2335#define CPL_RX_TLS_CMP_TID_S 0 2336#define CPL_RX_TLS_CMP_TID_M 0xffffff 2337#define CPL_RX_TLS_CMP_TID_V(x) ((x) << CPL_RX_TLS_CMP_TID_S) 2338#define CPL_RX_TLS_CMP_TID_G(x) \ 2339 (((x) >> CPL_RX_TLS_CMP_TID_S) & CPL_RX_TLS_CMP_TID_M) 2340 2341#define CPL_RX_TLS_CMP_PDULENGTH_S 16 2342#define CPL_RX_TLS_CMP_PDULENGTH_M 0xffff 2343#define CPL_RX_TLS_CMP_PDULENGTH_V(x) ((x) << CPL_RX_TLS_CMP_PDULENGTH_S) 2344#define CPL_RX_TLS_CMP_PDULENGTH_G(x) \ 2345 (((x) >> CPL_RX_TLS_CMP_PDULENGTH_S) & CPL_RX_TLS_CMP_PDULENGTH_M) 2346 2347#define CPL_RX_TLS_CMP_LENGTH_S 0 2348#define CPL_RX_TLS_CMP_LENGTH_M 0xffff 2349#define CPL_RX_TLS_CMP_LENGTH_V(x) ((x) << CPL_RX_TLS_CMP_LENGTH_S) 2350#define CPL_RX_TLS_CMP_LENGTH_G(x) \ 2351 (((x) >> CPL_RX_TLS_CMP_LENGTH_S) & CPL_RX_TLS_CMP_LENGTH_M) 2352#endif /* __T4_MSG_H */ 2353