14fa9c49fSThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */
276bcb31eSAnish Bhatt/*
376bcb31eSAnish Bhatt *  Copyright (C) 2013-2014 Chelsio Communications.  All rights reserved.
476bcb31eSAnish Bhatt *
576bcb31eSAnish Bhatt *  Written by Anish Bhatt (anish@chelsio.com)
676bcb31eSAnish Bhatt */
776bcb31eSAnish Bhatt
876bcb31eSAnish Bhatt#ifndef __CXGB4_DCB_H
976bcb31eSAnish Bhatt#define __CXGB4_DCB_H
1076bcb31eSAnish Bhatt
1176bcb31eSAnish Bhatt#include <linux/netdevice.h>
1276bcb31eSAnish Bhatt#include <linux/dcbnl.h>
1376bcb31eSAnish Bhatt#include <net/dcbnl.h>
1476bcb31eSAnish Bhatt
1576bcb31eSAnish Bhatt#ifdef CONFIG_CHELSIO_T4_DCB
1676bcb31eSAnish Bhatt
1776bcb31eSAnish Bhatt#define CXGB4_DCBX_FW_SUPPORT \
1876bcb31eSAnish Bhatt	(DCB_CAP_DCBX_VER_CEE | \
1976bcb31eSAnish Bhatt	 DCB_CAP_DCBX_VER_IEEE | \
2076bcb31eSAnish Bhatt	 DCB_CAP_DCBX_LLD_MANAGED)
2176bcb31eSAnish Bhatt#define CXGB4_DCBX_HOST_SUPPORT \
2276bcb31eSAnish Bhatt	(DCB_CAP_DCBX_VER_CEE | \
2376bcb31eSAnish Bhatt	 DCB_CAP_DCBX_VER_IEEE | \
2476bcb31eSAnish Bhatt	 DCB_CAP_DCBX_HOST)
2576bcb31eSAnish Bhatt
2676bcb31eSAnish Bhatt#define CXGB4_MAX_PRIORITY      CXGB4_MAX_DCBX_APP_SUPPORTED
2776bcb31eSAnish Bhatt#define CXGB4_MAX_TCS           CXGB4_MAX_DCBX_APP_SUPPORTED
2876bcb31eSAnish Bhatt
2976bcb31eSAnish Bhatt#define INIT_PORT_DCB_CMD(__pcmd, __port, __op, __action) \
3076bcb31eSAnish Bhatt	do { \
3176bcb31eSAnish Bhatt		memset(&(__pcmd), 0, sizeof(__pcmd)); \
3276bcb31eSAnish Bhatt		(__pcmd).op_to_portid = \
33e2ac9628SHariprasad Shenai			cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | \
34e2ac9628SHariprasad Shenai				    FW_CMD_REQUEST_F | \
35e2ac9628SHariprasad Shenai				    FW_CMD_##__op##_F | \
362b5fb1f2SHariprasad Shenai				    FW_PORT_CMD_PORTID_V(__port)); \
3776bcb31eSAnish Bhatt		(__pcmd).action_to_len16 = \
382b5fb1f2SHariprasad Shenai			cpu_to_be32(FW_PORT_CMD_ACTION_V(__action) | \
3976bcb31eSAnish Bhatt				    FW_LEN16(pcmd)); \
4076bcb31eSAnish Bhatt	} while (0)
4176bcb31eSAnish Bhatt
4276bcb31eSAnish Bhatt#define INIT_PORT_DCB_READ_PEER_CMD(__pcmd, __port) \
4376bcb31eSAnish Bhatt	INIT_PORT_DCB_CMD(__pcmd, __port, READ, FW_PORT_ACTION_DCB_READ_RECV)
4476bcb31eSAnish Bhatt
4576bcb31eSAnish Bhatt#define INIT_PORT_DCB_READ_LOCAL_CMD(__pcmd, __port) \
4676bcb31eSAnish Bhatt	INIT_PORT_DCB_CMD(__pcmd, __port, READ, FW_PORT_ACTION_DCB_READ_TRANS)
4776bcb31eSAnish Bhatt
4876bcb31eSAnish Bhatt#define INIT_PORT_DCB_READ_SYNC_CMD(__pcmd, __port) \
4976bcb31eSAnish Bhatt	INIT_PORT_DCB_CMD(__pcmd, __port, READ, FW_PORT_ACTION_DCB_READ_DET)
5076bcb31eSAnish Bhatt
5176bcb31eSAnish Bhatt#define INIT_PORT_DCB_WRITE_CMD(__pcmd, __port) \
5276bcb31eSAnish Bhatt	INIT_PORT_DCB_CMD(__pcmd, __port, EXEC, FW_PORT_ACTION_L2_DCB_CFG)
5376bcb31eSAnish Bhatt
5410b00466SAnish Bhatt#define IEEE_FAUX_SYNC(__dev, __dcb) \
5510b00466SAnish Bhatt	do { \
5610b00466SAnish Bhatt		if ((__dcb)->dcb_version == FW_PORT_DCB_VER_IEEE) \
5710b00466SAnish Bhatt			cxgb4_dcb_state_fsm((__dev), \
58258b6d14SNathan Chancellor					    CXGB4_DCB_INPUT_FW_ALLSYNCED); \
5910b00466SAnish Bhatt	} while (0)
6010b00466SAnish Bhatt
6176bcb31eSAnish Bhatt/* States we can be in for a port's Data Center Bridging.
6276bcb31eSAnish Bhatt */
6376bcb31eSAnish Bhattenum cxgb4_dcb_state {
6476bcb31eSAnish Bhatt	CXGB4_DCB_STATE_START,		/* initial unknown state */
6576bcb31eSAnish Bhatt	CXGB4_DCB_STATE_HOST,		/* we're using Host DCB (if at all) */
6676bcb31eSAnish Bhatt	CXGB4_DCB_STATE_FW_INCOMPLETE,	/* using firmware DCB, incomplete */
6776bcb31eSAnish Bhatt	CXGB4_DCB_STATE_FW_ALLSYNCED,	/* using firmware DCB, all sync'ed */
6876bcb31eSAnish Bhatt};
6976bcb31eSAnish Bhatt
7076bcb31eSAnish Bhatt/* Data Center Bridging state input for the Finite State Machine.
7176bcb31eSAnish Bhatt */
7276bcb31eSAnish Bhattenum cxgb4_dcb_state_input {
7376bcb31eSAnish Bhatt	/* Input from the firmware.
7476bcb31eSAnish Bhatt	 */
7576bcb31eSAnish Bhatt	CXGB4_DCB_INPUT_FW_DISABLED,	/* firmware DCB disabled */
7676bcb31eSAnish Bhatt	CXGB4_DCB_INPUT_FW_ENABLED,	/* firmware DCB enabled */
7776bcb31eSAnish Bhatt	CXGB4_DCB_INPUT_FW_INCOMPLETE,	/* firmware reports incomplete DCB */
7876bcb31eSAnish Bhatt	CXGB4_DCB_INPUT_FW_ALLSYNCED,	/* firmware reports all sync'ed */
7976bcb31eSAnish Bhatt
8076bcb31eSAnish Bhatt};
8176bcb31eSAnish Bhatt
8276bcb31eSAnish Bhatt/* Firmware DCB messages that we've received so far ...
8376bcb31eSAnish Bhatt */
8476bcb31eSAnish Bhattenum cxgb4_dcb_fw_msgs {
8576bcb31eSAnish Bhatt	CXGB4_DCB_FW_PGID	= 0x01,
8676bcb31eSAnish Bhatt	CXGB4_DCB_FW_PGRATE	= 0x02,
8776bcb31eSAnish Bhatt	CXGB4_DCB_FW_PRIORATE	= 0x04,
8876bcb31eSAnish Bhatt	CXGB4_DCB_FW_PFC	= 0x08,
8976bcb31eSAnish Bhatt	CXGB4_DCB_FW_APP_ID	= 0x10,
9076bcb31eSAnish Bhatt};
9176bcb31eSAnish Bhatt
9276bcb31eSAnish Bhatt#define CXGB4_MAX_DCBX_APP_SUPPORTED 8
9376bcb31eSAnish Bhatt
9476bcb31eSAnish Bhatt/* Data Center Bridging support;
9576bcb31eSAnish Bhatt */
9676bcb31eSAnish Bhattstruct port_dcb_info {
9776bcb31eSAnish Bhatt	enum cxgb4_dcb_state state;	/* DCB State Machine */
9876bcb31eSAnish Bhatt	enum cxgb4_dcb_fw_msgs msgs;	/* DCB Firmware messages received */
9976bcb31eSAnish Bhatt	unsigned int supported;		/* OS DCB capabilities supported */
10076bcb31eSAnish Bhatt	bool enabled;			/* OS Enabled state */
10176bcb31eSAnish Bhatt
10276bcb31eSAnish Bhatt	/* Cached copies of DCB information sent by the firmware (in Host
10376bcb31eSAnish Bhatt	 * Native Endian format).
10476bcb31eSAnish Bhatt	 */
10576bcb31eSAnish Bhatt	u32	pgid;			/* Priority Group[0..7] */
10610b00466SAnish Bhatt	u8	dcb_version;		/* Running DCBx version */
10776bcb31eSAnish Bhatt	u8	pfcen;			/* Priority Flow Control[0..7] */
10876bcb31eSAnish Bhatt	u8	pg_num_tcs_supported;	/* max PG Traffic Classes */
10976bcb31eSAnish Bhatt	u8	pfc_num_tcs_supported;	/* max PFC Traffic Classes */
11076bcb31eSAnish Bhatt	u8	pgrate[8];		/* Priority Group Rate[0..7] */
11176bcb31eSAnish Bhatt	u8	priorate[8];		/* Priority Rate[0..7] */
11210b00466SAnish Bhatt	u8	tsa[8];			/* TSA Algorithm[0..7] */
11376bcb31eSAnish Bhatt	struct app_priority { /* Application Information */
11476bcb31eSAnish Bhatt		u8	user_prio_map;	/* Priority Map bitfield */
11576bcb31eSAnish Bhatt		u8	sel_field;	/* Protocol ID interpretation */
11676bcb31eSAnish Bhatt		u16	protocolid;	/* Protocol ID */
11776bcb31eSAnish Bhatt	} app_priority[CXGB4_MAX_DCBX_APP_SUPPORTED];
11876bcb31eSAnish Bhatt};
11976bcb31eSAnish Bhatt
12076bcb31eSAnish Bhattvoid cxgb4_dcb_state_init(struct net_device *);
12110b00466SAnish Bhattvoid cxgb4_dcb_version_init(struct net_device *);
122ba581f77SGanesh Goudarvoid cxgb4_dcb_reset(struct net_device *dev);
12376bcb31eSAnish Bhattvoid cxgb4_dcb_state_fsm(struct net_device *, enum cxgb4_dcb_state_input);
12476bcb31eSAnish Bhattvoid cxgb4_dcb_handle_fw_update(struct adapter *, const struct fw_port_cmd *);
12576bcb31eSAnish Bhattvoid cxgb4_dcb_set_caps(struct adapter *, const struct fw_port_cmd *);
12676bcb31eSAnish Bhattextern const struct dcbnl_rtnl_ops cxgb4_dcb_ops;
12776bcb31eSAnish Bhatt
128ba0c39cbSAnish Bhattstatic inline __u8 bitswap_1(unsigned char val)
129ba0c39cbSAnish Bhatt{
130ba0c39cbSAnish Bhatt	return ((val & 0x80) >> 7) |
131ba0c39cbSAnish Bhatt	       ((val & 0x40) >> 5) |
132ba0c39cbSAnish Bhatt	       ((val & 0x20) >> 3) |
133ba0c39cbSAnish Bhatt	       ((val & 0x10) >> 1) |
134ba0c39cbSAnish Bhatt	       ((val & 0x08) << 1) |
135ba0c39cbSAnish Bhatt	       ((val & 0x04) << 3) |
136ba0c39cbSAnish Bhatt	       ((val & 0x02) << 5) |
137ba0c39cbSAnish Bhatt	       ((val & 0x01) << 7);
138ba0c39cbSAnish Bhatt}
139bab3bcf3SRahul Lakkireddy
140bab3bcf3SRahul Lakkireddyextern const char * const dcb_ver_array[];
141bab3bcf3SRahul Lakkireddy
14276bcb31eSAnish Bhatt#define CXGB4_DCB_ENABLED true
14376bcb31eSAnish Bhatt
14476bcb31eSAnish Bhatt#else /* !CONFIG_CHELSIO_T4_DCB */
14576bcb31eSAnish Bhatt
14676bcb31eSAnish Bhattstatic inline void cxgb4_dcb_state_init(struct net_device *dev)
14776bcb31eSAnish Bhatt{
14876bcb31eSAnish Bhatt}
14976bcb31eSAnish Bhatt
15076bcb31eSAnish Bhatt#define CXGB4_DCB_ENABLED false
15176bcb31eSAnish Bhatt
15276bcb31eSAnish Bhatt#endif /* !CONFIG_CHELSIO_T4_DCB */
15376bcb31eSAnish Bhatt
15476bcb31eSAnish Bhatt#endif /* __CXGB4_DCB_H */
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