1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* atlx_hw.h -- common hardware definitions for Attansic network drivers 3 * 4 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. 5 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com> 6 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com> 7 * Copyright(c) 2007 Atheros Corporation. All rights reserved. 8 * 9 * Derived from Intel e1000 driver 10 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 11 */ 12 13#ifndef ATLX_H 14#define ATLX_H 15 16#include <linux/module.h> 17#include <linux/types.h> 18 19#define ATLX_ERR_PHY 2 20#define ATLX_ERR_PHY_SPEED 7 21#define ATLX_ERR_PHY_RES 8 22 23#define SPEED_0 0xffff 24#define SPEED_10 10 25#define SPEED_100 100 26#define SPEED_1000 1000 27#define HALF_DUPLEX 1 28#define FULL_DUPLEX 2 29 30#define MEDIA_TYPE_AUTO_SENSOR 0 31 32/* register definitions */ 33#define REG_PM_CTRLSTAT 0x44 34 35#define REG_PCIE_CAP_LIST 0x58 36 37#define REG_VPD_CAP 0x6C 38#define VPD_CAP_ID_MASK 0xFF 39#define VPD_CAP_ID_SHIFT 0 40#define VPD_CAP_NEXT_PTR_MASK 0xFF 41#define VPD_CAP_NEXT_PTR_SHIFT 8 42#define VPD_CAP_VPD_ADDR_MASK 0x7FFF 43#define VPD_CAP_VPD_ADDR_SHIFT 16 44#define VPD_CAP_VPD_FLAG 0x80000000 45 46#define REG_VPD_DATA 0x70 47 48#define REG_SPI_FLASH_CTRL 0x200 49#define SPI_FLASH_CTRL_STS_NON_RDY 0x1 50#define SPI_FLASH_CTRL_STS_WEN 0x2 51#define SPI_FLASH_CTRL_STS_WPEN 0x80 52#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF 53#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0 54#define SPI_FLASH_CTRL_INS_MASK 0x7 55#define SPI_FLASH_CTRL_INS_SHIFT 8 56#define SPI_FLASH_CTRL_START 0x800 57#define SPI_FLASH_CTRL_EN_VPD 0x2000 58#define SPI_FLASH_CTRL_LDSTART 0x8000 59#define SPI_FLASH_CTRL_CS_HI_MASK 0x3 60#define SPI_FLASH_CTRL_CS_HI_SHIFT 16 61#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3 62#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18 63#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3 64#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20 65#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3 66#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22 67#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3 68#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24 69#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3 70#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26 71#define SPI_FLASH_CTRL_WAIT_READY 0x10000000 72 73#define REG_SPI_ADDR 0x204 74 75#define REG_SPI_DATA 0x208 76 77#define REG_SPI_FLASH_CONFIG 0x20C 78#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF 79#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0 80#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3 81#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24 82#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000 83 84#define REG_SPI_FLASH_OP_PROGRAM 0x210 85#define REG_SPI_FLASH_OP_SC_ERASE 0x211 86#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212 87#define REG_SPI_FLASH_OP_RDID 0x213 88#define REG_SPI_FLASH_OP_WREN 0x214 89#define REG_SPI_FLASH_OP_RDSR 0x215 90#define REG_SPI_FLASH_OP_WRSR 0x216 91#define REG_SPI_FLASH_OP_READ 0x217 92 93#define REG_TWSI_CTRL 0x218 94#define TWSI_CTRL_LD_OFFSET_MASK 0xFF 95#define TWSI_CTRL_LD_OFFSET_SHIFT 0 96#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7 97#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8 98#define TWSI_CTRL_SW_LDSTART 0x800 99#define TWSI_CTRL_HW_LDSTART 0x1000 100#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F 101#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15 102#define TWSI_CTRL_LD_EXIST 0x400000 103#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3 104#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23 105#define TWSI_CTRL_FREQ_SEL_100K 0 106#define TWSI_CTRL_FREQ_SEL_200K 1 107#define TWSI_CTRL_FREQ_SEL_300K 2 108#define TWSI_CTRL_FREQ_SEL_400K 3 109#define TWSI_CTRL_SMB_SLV_ADDR /* FIXME: define or remove */ 110#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3 111#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24 112 113#define REG_PCIE_DEV_MISC_CTRL 0x21C 114#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2 115#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1 116#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4 117#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8 118#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10 119 120#define REG_PCIE_PHYMISC 0x1000 121#define PCIE_PHYMISC_FORCE_RCV_DET 0x4 122 123#define REG_PCIE_DLL_TX_CTRL1 0x1104 124#define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x400 125#define PCIE_DLL_TX_CTRL1_DEF 0x568 126 127#define REG_LTSSM_TEST_MODE 0x12FC 128#define LTSSM_TEST_MODE_DEF 0x6500 129 130/* Master Control Register */ 131#define REG_MASTER_CTRL 0x1400 132#define MASTER_CTRL_SOFT_RST 0x1 133#define MASTER_CTRL_MTIMER_EN 0x2 134#define MASTER_CTRL_ITIMER_EN 0x4 135#define MASTER_CTRL_MANUAL_INT 0x8 136#define MASTER_CTRL_REV_NUM_SHIFT 16 137#define MASTER_CTRL_REV_NUM_MASK 0xFF 138#define MASTER_CTRL_DEV_ID_SHIFT 24 139#define MASTER_CTRL_DEV_ID_MASK 0xFF 140 141/* Timer Initial Value Register */ 142#define REG_MANUAL_TIMER_INIT 0x1404 143 144/* IRQ Moderator Timer Initial Value Register */ 145#define REG_IRQ_MODU_TIMER_INIT 0x1408 146 147#define REG_PHY_ENABLE 0x140C 148 149/* IRQ Anti-Lost Timer Initial Value Register */ 150#define REG_CMBDISDMA_TIMER 0x140E 151 152/* Block IDLE Status Register */ 153#define REG_IDLE_STATUS 0x1410 154 155/* MDIO Control Register */ 156#define REG_MDIO_CTRL 0x1414 157#define MDIO_DATA_MASK 0xFFFF 158#define MDIO_DATA_SHIFT 0 159#define MDIO_REG_ADDR_MASK 0x1F 160#define MDIO_REG_ADDR_SHIFT 16 161#define MDIO_RW 0x200000 162#define MDIO_SUP_PREAMBLE 0x400000 163#define MDIO_START 0x800000 164#define MDIO_CLK_SEL_SHIFT 24 165#define MDIO_CLK_25_4 0 166#define MDIO_CLK_25_6 2 167#define MDIO_CLK_25_8 3 168#define MDIO_CLK_25_10 4 169#define MDIO_CLK_25_14 5 170#define MDIO_CLK_25_20 6 171#define MDIO_CLK_25_28 7 172#define MDIO_BUSY 0x8000000 173 174/* MII PHY Status Register */ 175#define REG_PHY_STATUS 0x1418 176 177/* BIST Control and Status Register0 (for the Packet Memory) */ 178#define REG_BIST0_CTRL 0x141C 179#define BIST0_NOW 0x1 180#define BIST0_SRAM_FAIL 0x2 181#define BIST0_FUSE_FLAG 0x4 182#define REG_BIST1_CTRL 0x1420 183#define BIST1_NOW 0x1 184#define BIST1_SRAM_FAIL 0x2 185#define BIST1_FUSE_FLAG 0x4 186 187/* SerDes Lock Detect Control and Status Register */ 188#define REG_SERDES_LOCK 0x1424 189#define SERDES_LOCK_DETECT 1 190#define SERDES_LOCK_DETECT_EN 2 191 192/* MAC Control Register */ 193#define REG_MAC_CTRL 0x1480 194#define MAC_CTRL_TX_EN 1 195#define MAC_CTRL_RX_EN 2 196#define MAC_CTRL_TX_FLOW 4 197#define MAC_CTRL_RX_FLOW 8 198#define MAC_CTRL_LOOPBACK 0x10 199#define MAC_CTRL_DUPLX 0x20 200#define MAC_CTRL_ADD_CRC 0x40 201#define MAC_CTRL_PAD 0x80 202#define MAC_CTRL_LENCHK 0x100 203#define MAC_CTRL_HUGE_EN 0x200 204#define MAC_CTRL_PRMLEN_SHIFT 10 205#define MAC_CTRL_PRMLEN_MASK 0xF 206#define MAC_CTRL_RMV_VLAN 0x4000 207#define MAC_CTRL_PROMIS_EN 0x8000 208#define MAC_CTRL_MC_ALL_EN 0x2000000 209#define MAC_CTRL_BC_EN 0x4000000 210 211/* MAC IPG/IFG Control Register */ 212#define REG_MAC_IPG_IFG 0x1484 213#define MAC_IPG_IFG_IPGT_SHIFT 0 214#define MAC_IPG_IFG_IPGT_MASK 0x7F 215#define MAC_IPG_IFG_MIFG_SHIFT 8 216#define MAC_IPG_IFG_MIFG_MASK 0xFF 217#define MAC_IPG_IFG_IPGR1_SHIFT 16 218#define MAC_IPG_IFG_IPGR1_MASK 0x7F 219#define MAC_IPG_IFG_IPGR2_SHIFT 24 220#define MAC_IPG_IFG_IPGR2_MASK 0x7F 221 222/* MAC STATION ADDRESS */ 223#define REG_MAC_STA_ADDR 0x1488 224 225/* Hash table for multicast address */ 226#define REG_RX_HASH_TABLE 0x1490 227 228/* MAC Half-Duplex Control Register */ 229#define REG_MAC_HALF_DUPLX_CTRL 0x1498 230#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 231#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3FF 232#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 233#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xF 234#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 235#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 236#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 237#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 238#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 239#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xF 240#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 241#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xF 242 243/* Maximum Frame Length Control Register */ 244#define REG_MTU 0x149C 245 246/* Wake-On-Lan control register */ 247#define REG_WOL_CTRL 0x14A0 248#define WOL_PATTERN_EN 0x1 249#define WOL_PATTERN_PME_EN 0x2 250#define WOL_MAGIC_EN 0x4 251#define WOL_MAGIC_PME_EN 0x8 252#define WOL_LINK_CHG_EN 0x10 253#define WOL_LINK_CHG_PME_EN 0x20 254#define WOL_PATTERN_ST 0x100 255#define WOL_MAGIC_ST 0x200 256#define WOL_LINKCHG_ST 0x400 257#define WOL_PT0_EN 0x10000 258#define WOL_PT1_EN 0x20000 259#define WOL_PT2_EN 0x40000 260#define WOL_PT3_EN 0x80000 261#define WOL_PT4_EN 0x100000 262#define WOL_PT0_MATCH 0x1000000 263#define WOL_PT1_MATCH 0x2000000 264#define WOL_PT2_MATCH 0x4000000 265#define WOL_PT3_MATCH 0x8000000 266#define WOL_PT4_MATCH 0x10000000 267 268/* Internal SRAM Partition Register, high 32 bits */ 269#define REG_SRAM_RFD_ADDR 0x1500 270 271/* Descriptor Control register, high 32 bits */ 272#define REG_DESC_BASE_ADDR_HI 0x1540 273 274/* Interrupt Status Register */ 275#define REG_ISR 0x1600 276#define ISR_UR_DETECTED 0x1000000 277#define ISR_FERR_DETECTED 0x2000000 278#define ISR_NFERR_DETECTED 0x4000000 279#define ISR_CERR_DETECTED 0x8000000 280#define ISR_PHY_LINKDOWN 0x10000000 281#define ISR_DIS_INT 0x80000000 282 283/* Interrupt Mask Register */ 284#define REG_IMR 0x1604 285 286#define REG_RFD_RRD_IDX 0x1800 287#define REG_TPD_IDX 0x1804 288 289/* MII definitions */ 290 291/* PHY Common Register */ 292#define MII_ATLX_CR 0x09 293#define MII_ATLX_SR 0x0A 294#define MII_ATLX_ESR 0x0F 295#define MII_ATLX_PSCR 0x10 296#define MII_ATLX_PSSR 0x11 297 298/* PHY Control Register */ 299#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 300 * 00=10 301 */ 302#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 303#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 304#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 305#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 306#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 307#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 308#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 309 * 00=10 310 */ 311#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 312#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 313#define MII_CR_SPEED_MASK 0x2040 314#define MII_CR_SPEED_1000 0x0040 315#define MII_CR_SPEED_100 0x2000 316#define MII_CR_SPEED_10 0x0000 317 318/* PHY Status Register */ 319#define MII_SR_EXTENDED_CAPS 0x0001 /* Ext register capabilities */ 320#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 321#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 322#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 323#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 324#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 325#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 326#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext stat info in Reg 0x0F */ 327#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 328#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 329#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 330#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 331#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 332#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 333#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 334 335/* Link partner ability register */ 336#define MII_LPA_SLCT 0x001f /* Same as advertise selector */ 337#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 338#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 339#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 340#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 341#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */ 342#define MII_LPA_PAUSE 0x0400 /* PAUSE */ 343#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */ 344#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */ 345#define MII_LPA_LPACK 0x4000 /* Link partner acked us */ 346#define MII_LPA_NPAGE 0x8000 /* Next page bit */ 347 348/* Autoneg Advertisement Register */ 349#define MII_AR_SELECTOR_FIELD 0x0001 /* IEEE 802.3 CSMA/CD */ 350#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 351#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 352#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 353#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 354#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 355#define MII_AR_PAUSE 0x0400 /* Pause operation desired */ 356#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Dir bit */ 357#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 358#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability support */ 359#define MII_AR_SPEED_MASK 0x01E0 360#define MII_AR_DEFAULT_CAP_MASK 0x0DE0 361 362/* 1000BASE-T Control Register */ 363#define MII_ATLX_CR_1000T_HD_CAPS 0x0100 /* Adv 1000T HD cap */ 364#define MII_ATLX_CR_1000T_FD_CAPS 0x0200 /* Adv 1000T FD cap */ 365#define MII_ATLX_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device, 366 * 0=DTE device */ 367#define MII_ATLX_CR_1000T_MS_VALUE 0x0800 /* 1=Config PHY as Master, 368 * 0=Configure PHY as Slave */ 369#define MII_ATLX_CR_1000T_MS_ENABLE 0x1000 /* 1=Man Master/Slave config, 370 * 0=Auto Master/Slave config 371 */ 372#define MII_ATLX_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 373#define MII_ATLX_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 374#define MII_ATLX_CR_1000T_TEST_MODE_2 0x4000 /* Master Xmit Jitter test */ 375#define MII_ATLX_CR_1000T_TEST_MODE_3 0x6000 /* Slave Xmit Jitter test */ 376#define MII_ATLX_CR_1000T_TEST_MODE_4 0x8000 /* Xmitter Distortion test */ 377#define MII_ATLX_CR_1000T_SPEED_MASK 0x0300 378#define MII_ATLX_CR_1000T_DEFAULT_CAP_MASK 0x0300 379 380/* 1000BASE-T Status Register */ 381#define MII_ATLX_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 382#define MII_ATLX_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 383#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 384#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 385#define MII_ATLX_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master 386 * 0=Slave 387 */ 388#define MII_ATLX_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config 389 * fault */ 390#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS_SHIFT 12 391#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS_SHIFT 13 392 393/* Extended Status Register */ 394#define MII_ATLX_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 395#define MII_ATLX_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 396#define MII_ATLX_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 397#define MII_ATLX_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 398 399/* ATLX PHY Specific Control Register */ 400#define MII_ATLX_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Func disabled */ 401#define MII_ATLX_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enbld */ 402#define MII_ATLX_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 403#define MII_ATLX_PSCR_MAC_POWERDOWN 0x0008 404#define MII_ATLX_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low 405 * 0=CLK125 toggling 406 */ 407#define MII_ATLX_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5, 408 * Manual MDI configuration 409 */ 410#define MII_ATLX_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 411#define MII_ATLX_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover 412 * 100BASE-TX/10BASE-T: MDI 413 * Mode */ 414#define MII_ATLX_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 415 * all speeds. 416 */ 417#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 418 * 10BASE-T distance 419 * (Lower 10BASE-T RX 420 * Threshold) 421 * 0=Normal 10BASE-T RX 422 * Threshold 423 */ 424#define MII_ATLX_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in 425 * 100BASE-TX 426 * 0=MII interface in 427 * 100BASE-TX 428 */ 429#define MII_ATLX_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler dsbl */ 430#define MII_ATLX_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 431#define MII_ATLX_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 432#define MII_ATLX_PSCR_POLARITY_REVERSAL_SHIFT 1 433#define MII_ATLX_PSCR_AUTO_X_MODE_SHIFT 5 434#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 435 436/* ATLX PHY Specific Status Register */ 437#define MII_ATLX_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 438#define MII_ATLX_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 439#define MII_ATLX_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 440#define MII_ATLX_PSSR_10MBS 0x0000 /* 00=10Mbs */ 441#define MII_ATLX_PSSR_100MBS 0x4000 /* 01=100Mbs */ 442#define MII_ATLX_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 443 444#define MII_DBG_ADDR 0x1D 445#define MII_DBG_DATA 0x1E 446 447/* PCI Command Register Bit Definitions */ 448#define PCI_REG_COMMAND 0x04 /* PCI Command Register */ 449#define CMD_IO_SPACE 0x0001 450#define CMD_MEMORY_SPACE 0x0002 451#define CMD_BUS_MASTER 0x0004 452 453/* Wake Up Filter Control */ 454#define ATLX_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 455#define ATLX_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 456#define ATLX_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 457#define ATLX_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ 458#define ATLX_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 459 460#define ADVERTISE_10_HALF 0x0001 461#define ADVERTISE_10_FULL 0x0002 462#define ADVERTISE_100_HALF 0x0004 463#define ADVERTISE_100_FULL 0x0008 464#define ADVERTISE_1000_HALF 0x0010 465#define ADVERTISE_1000_FULL 0x0020 466#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */ 467#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */ 468 469#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 470#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ 471 472/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA */ 473#define EEPROM_SUM 0xBABA 474 475struct atlx_spi_flash_dev { 476 const char *manu_name; /* manufacturer id */ 477 /* op-code */ 478 u8 cmd_wrsr; 479 u8 cmd_read; 480 u8 cmd_program; 481 u8 cmd_wren; 482 u8 cmd_wrdi; 483 u8 cmd_rdsr; 484 u8 cmd_rdid; 485 u8 cmd_sector_erase; 486 u8 cmd_chip_erase; 487}; 488 489#endif /* ATLX_H */ 490