1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved. 4 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com> 5 * 6 * Derived from Intel e1000 driver 7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 8 */ 9 10#include <linux/atomic.h> 11#include <linux/crc32.h> 12#include <linux/dma-mapping.h> 13#include <linux/etherdevice.h> 14#include <linux/ethtool.h> 15#include <linux/hardirq.h> 16#include <linux/if_vlan.h> 17#include <linux/in.h> 18#include <linux/interrupt.h> 19#include <linux/ip.h> 20#include <linux/irqflags.h> 21#include <linux/irqreturn.h> 22#include <linux/mii.h> 23#include <linux/net.h> 24#include <linux/netdevice.h> 25#include <linux/pci.h> 26#include <linux/pci_ids.h> 27#include <linux/pm.h> 28#include <linux/skbuff.h> 29#include <linux/slab.h> 30#include <linux/spinlock.h> 31#include <linux/string.h> 32#include <linux/tcp.h> 33#include <linux/timer.h> 34#include <linux/types.h> 35#include <linux/workqueue.h> 36 37#include "atl2.h" 38 39static const char atl2_driver_name[] = "atl2"; 40static const struct ethtool_ops atl2_ethtool_ops; 41 42MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>"); 43MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver"); 44MODULE_LICENSE("GPL"); 45 46/* 47 * atl2_pci_tbl - PCI Device ID Table 48 */ 49static const struct pci_device_id atl2_pci_tbl[] = { 50 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)}, 51 /* required last entry */ 52 {0,} 53}; 54MODULE_DEVICE_TABLE(pci, atl2_pci_tbl); 55 56static void atl2_check_options(struct atl2_adapter *adapter); 57 58/** 59 * atl2_sw_init - Initialize general software structures (struct atl2_adapter) 60 * @adapter: board private structure to initialize 61 * 62 * atl2_sw_init initializes the Adapter private data structure. 63 * Fields are initialized based on PCI device information and 64 * OS network device settings (MTU size). 65 */ 66static int atl2_sw_init(struct atl2_adapter *adapter) 67{ 68 struct atl2_hw *hw = &adapter->hw; 69 struct pci_dev *pdev = adapter->pdev; 70 71 /* PCI config space info */ 72 hw->vendor_id = pdev->vendor; 73 hw->device_id = pdev->device; 74 hw->subsystem_vendor_id = pdev->subsystem_vendor; 75 hw->subsystem_id = pdev->subsystem_device; 76 hw->revision_id = pdev->revision; 77 78 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 79 80 adapter->wol = 0; 81 adapter->ict = 50000; /* ~100ms */ 82 adapter->link_speed = SPEED_0; /* hardware init */ 83 adapter->link_duplex = FULL_DUPLEX; 84 85 hw->phy_configured = false; 86 hw->preamble_len = 7; 87 hw->ipgt = 0x60; 88 hw->min_ifg = 0x50; 89 hw->ipgr1 = 0x40; 90 hw->ipgr2 = 0x60; 91 hw->retry_buf = 2; 92 hw->max_retry = 0xf; 93 hw->lcol = 0x37; 94 hw->jam_ipg = 7; 95 hw->fc_rxd_hi = 0; 96 hw->fc_rxd_lo = 0; 97 hw->max_frame_size = adapter->netdev->mtu; 98 99 spin_lock_init(&adapter->stats_lock); 100 101 set_bit(__ATL2_DOWN, &adapter->flags); 102 103 return 0; 104} 105 106/** 107 * atl2_set_multi - Multicast and Promiscuous mode set 108 * @netdev: network interface device structure 109 * 110 * The set_multi entry point is called whenever the multicast address 111 * list or the network interface flags are updated. This routine is 112 * responsible for configuring the hardware for proper multicast, 113 * promiscuous mode, and all-multi behavior. 114 */ 115static void atl2_set_multi(struct net_device *netdev) 116{ 117 struct atl2_adapter *adapter = netdev_priv(netdev); 118 struct atl2_hw *hw = &adapter->hw; 119 struct netdev_hw_addr *ha; 120 u32 rctl; 121 u32 hash_value; 122 123 /* Check for Promiscuous and All Multicast modes */ 124 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); 125 126 if (netdev->flags & IFF_PROMISC) { 127 rctl |= MAC_CTRL_PROMIS_EN; 128 } else if (netdev->flags & IFF_ALLMULTI) { 129 rctl |= MAC_CTRL_MC_ALL_EN; 130 rctl &= ~MAC_CTRL_PROMIS_EN; 131 } else 132 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); 133 134 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); 135 136 /* clear the old settings from the multicast hash table */ 137 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 138 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 139 140 /* comoute mc addresses' hash value ,and put it into hash table */ 141 netdev_for_each_mc_addr(ha, netdev) { 142 hash_value = atl2_hash_mc_addr(hw, ha->addr); 143 atl2_hash_set(hw, hash_value); 144 } 145} 146 147static void init_ring_ptrs(struct atl2_adapter *adapter) 148{ 149 /* Read / Write Ptr Initialize: */ 150 adapter->txd_write_ptr = 0; 151 atomic_set(&adapter->txd_read_ptr, 0); 152 153 adapter->rxd_read_ptr = 0; 154 adapter->rxd_write_ptr = 0; 155 156 atomic_set(&adapter->txs_write_ptr, 0); 157 adapter->txs_next_clear = 0; 158} 159 160/** 161 * atl2_configure - Configure Transmit&Receive Unit after Reset 162 * @adapter: board private structure 163 * 164 * Configure the Tx /Rx unit of the MAC after a reset. 165 */ 166static int atl2_configure(struct atl2_adapter *adapter) 167{ 168 struct atl2_hw *hw = &adapter->hw; 169 u32 value; 170 171 /* clear interrupt status */ 172 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); 173 174 /* set MAC Address */ 175 value = (((u32)hw->mac_addr[2]) << 24) | 176 (((u32)hw->mac_addr[3]) << 16) | 177 (((u32)hw->mac_addr[4]) << 8) | 178 (((u32)hw->mac_addr[5])); 179 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); 180 value = (((u32)hw->mac_addr[0]) << 8) | 181 (((u32)hw->mac_addr[1])); 182 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); 183 184 /* HI base address */ 185 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 186 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32)); 187 188 /* LO base address */ 189 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, 190 (u32)(adapter->txd_dma & 0x00000000ffffffffULL)); 191 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, 192 (u32)(adapter->txs_dma & 0x00000000ffffffffULL)); 193 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, 194 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL)); 195 196 /* element count */ 197 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); 198 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); 199 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); 200 201 /* config Internal SRAM */ 202/* 203 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); 204 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); 205*/ 206 207 /* config IPG/IFG */ 208 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << 209 MAC_IPG_IFG_IPGT_SHIFT) | 210 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << 211 MAC_IPG_IFG_MIFG_SHIFT) | 212 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << 213 MAC_IPG_IFG_IPGR1_SHIFT)| 214 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << 215 MAC_IPG_IFG_IPGR2_SHIFT); 216 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); 217 218 /* config Half-Duplex Control */ 219 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | 220 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << 221 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | 222 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | 223 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | 224 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << 225 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); 226 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); 227 228 /* set Interrupt Moderator Timer */ 229 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); 230 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); 231 232 /* set Interrupt Clear Timer */ 233 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); 234 235 /* set MTU */ 236 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + 237 ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 238 239 /* 1590 */ 240 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); 241 242 /* flow control */ 243 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); 244 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); 245 246 /* Init mailbox */ 247 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); 248 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); 249 250 /* enable DMA read/write */ 251 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); 252 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); 253 254 value = ATL2_READ_REG(&adapter->hw, REG_ISR); 255 if ((value & ISR_PHY_LINKDOWN) != 0) 256 value = 1; /* config failed */ 257 else 258 value = 0; 259 260 /* clear all interrupt status */ 261 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); 262 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 263 return value; 264} 265 266/** 267 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources 268 * @adapter: board private structure 269 * 270 * Return 0 on success, negative on failure 271 */ 272static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter) 273{ 274 struct pci_dev *pdev = adapter->pdev; 275 int size; 276 u8 offset = 0; 277 278 /* real ring DMA buffer */ 279 adapter->ring_size = size = 280 adapter->txd_ring_size * 1 + 7 + /* dword align */ 281 adapter->txs_ring_size * 4 + 7 + /* dword align */ 282 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */ 283 284 adapter->ring_vir_addr = dma_alloc_coherent(&pdev->dev, size, 285 &adapter->ring_dma, GFP_KERNEL); 286 if (!adapter->ring_vir_addr) 287 return -ENOMEM; 288 289 /* Init TXD Ring */ 290 adapter->txd_dma = adapter->ring_dma ; 291 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0; 292 adapter->txd_dma += offset; 293 adapter->txd_ring = adapter->ring_vir_addr + offset; 294 295 /* Init TXS Ring */ 296 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size; 297 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0; 298 adapter->txs_dma += offset; 299 adapter->txs_ring = (struct tx_pkt_status *) 300 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset)); 301 302 /* Init RXD Ring */ 303 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4; 304 offset = (adapter->rxd_dma & 127) ? 305 (128 - (adapter->rxd_dma & 127)) : 0; 306 if (offset > 7) 307 offset -= 8; 308 else 309 offset += (128 - 8); 310 311 adapter->rxd_dma += offset; 312 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) + 313 (adapter->txs_ring_size * 4 + offset)); 314 315/* 316 * Read / Write Ptr Initialize: 317 * init_ring_ptrs(adapter); 318 */ 319 return 0; 320} 321 322/** 323 * atl2_irq_enable - Enable default interrupt generation settings 324 * @adapter: board private structure 325 */ 326static inline void atl2_irq_enable(struct atl2_adapter *adapter) 327{ 328 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); 329 ATL2_WRITE_FLUSH(&adapter->hw); 330} 331 332/** 333 * atl2_irq_disable - Mask off interrupt generation on the NIC 334 * @adapter: board private structure 335 */ 336static inline void atl2_irq_disable(struct atl2_adapter *adapter) 337{ 338 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); 339 ATL2_WRITE_FLUSH(&adapter->hw); 340 synchronize_irq(adapter->pdev->irq); 341} 342 343static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl) 344{ 345 if (features & NETIF_F_HW_VLAN_CTAG_RX) { 346 /* enable VLAN tag insert/strip */ 347 *ctrl |= MAC_CTRL_RMV_VLAN; 348 } else { 349 /* disable VLAN tag insert/strip */ 350 *ctrl &= ~MAC_CTRL_RMV_VLAN; 351 } 352} 353 354static void atl2_vlan_mode(struct net_device *netdev, 355 netdev_features_t features) 356{ 357 struct atl2_adapter *adapter = netdev_priv(netdev); 358 u32 ctrl; 359 360 atl2_irq_disable(adapter); 361 362 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); 363 __atl2_vlan_mode(features, &ctrl); 364 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); 365 366 atl2_irq_enable(adapter); 367} 368 369static void atl2_restore_vlan(struct atl2_adapter *adapter) 370{ 371 atl2_vlan_mode(adapter->netdev, adapter->netdev->features); 372} 373 374static netdev_features_t atl2_fix_features(struct net_device *netdev, 375 netdev_features_t features) 376{ 377 /* 378 * Since there is no support for separate rx/tx vlan accel 379 * enable/disable make sure tx flag is always in same state as rx. 380 */ 381 if (features & NETIF_F_HW_VLAN_CTAG_RX) 382 features |= NETIF_F_HW_VLAN_CTAG_TX; 383 else 384 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 385 386 return features; 387} 388 389static int atl2_set_features(struct net_device *netdev, 390 netdev_features_t features) 391{ 392 netdev_features_t changed = netdev->features ^ features; 393 394 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 395 atl2_vlan_mode(netdev, features); 396 397 return 0; 398} 399 400static void atl2_intr_rx(struct atl2_adapter *adapter) 401{ 402 struct net_device *netdev = adapter->netdev; 403 struct rx_desc *rxd; 404 struct sk_buff *skb; 405 406 do { 407 rxd = adapter->rxd_ring+adapter->rxd_write_ptr; 408 if (!rxd->status.update) 409 break; /* end of tx */ 410 411 /* clear this flag at once */ 412 rxd->status.update = 0; 413 414 if (rxd->status.ok && rxd->status.pkt_size >= 60) { 415 int rx_size = (int)(rxd->status.pkt_size - 4); 416 /* alloc new buffer */ 417 skb = netdev_alloc_skb_ip_align(netdev, rx_size); 418 if (NULL == skb) { 419 /* 420 * Check that some rx space is free. If not, 421 * free one and mark stats->rx_dropped++. 422 */ 423 netdev->stats.rx_dropped++; 424 break; 425 } 426 memcpy(skb->data, rxd->packet, rx_size); 427 skb_put(skb, rx_size); 428 skb->protocol = eth_type_trans(skb, netdev); 429 if (rxd->status.vlan) { 430 u16 vlan_tag = (rxd->status.vtag>>4) | 431 ((rxd->status.vtag&7) << 13) | 432 ((rxd->status.vtag&8) << 9); 433 434 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 435 } 436 netif_rx(skb); 437 netdev->stats.rx_bytes += rx_size; 438 netdev->stats.rx_packets++; 439 } else { 440 netdev->stats.rx_errors++; 441 442 if (rxd->status.ok && rxd->status.pkt_size <= 60) 443 netdev->stats.rx_length_errors++; 444 if (rxd->status.mcast) 445 netdev->stats.multicast++; 446 if (rxd->status.crc) 447 netdev->stats.rx_crc_errors++; 448 if (rxd->status.align) 449 netdev->stats.rx_frame_errors++; 450 } 451 452 /* advance write ptr */ 453 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size) 454 adapter->rxd_write_ptr = 0; 455 } while (1); 456 457 /* update mailbox? */ 458 adapter->rxd_read_ptr = adapter->rxd_write_ptr; 459 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); 460} 461 462static void atl2_intr_tx(struct atl2_adapter *adapter) 463{ 464 struct net_device *netdev = adapter->netdev; 465 u32 txd_read_ptr; 466 u32 txs_write_ptr; 467 struct tx_pkt_status *txs; 468 struct tx_pkt_header *txph; 469 int free_hole = 0; 470 471 do { 472 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 473 txs = adapter->txs_ring + txs_write_ptr; 474 if (!txs->update) 475 break; /* tx stop here */ 476 477 free_hole = 1; 478 txs->update = 0; 479 480 if (++txs_write_ptr == adapter->txs_ring_size) 481 txs_write_ptr = 0; 482 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr); 483 484 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr); 485 txph = (struct tx_pkt_header *) 486 (((u8 *)adapter->txd_ring) + txd_read_ptr); 487 488 if (txph->pkt_size != txs->pkt_size) { 489 struct tx_pkt_status *old_txs = txs; 490 printk(KERN_WARNING 491 "%s: txs packet size not consistent with txd" 492 " txd_:0x%08x, txs_:0x%08x!\n", 493 adapter->netdev->name, 494 *(u32 *)txph, *(u32 *)txs); 495 printk(KERN_WARNING 496 "txd read ptr: 0x%x\n", 497 txd_read_ptr); 498 txs = adapter->txs_ring + txs_write_ptr; 499 printk(KERN_WARNING 500 "txs-behind:0x%08x\n", 501 *(u32 *)txs); 502 if (txs_write_ptr < 2) { 503 txs = adapter->txs_ring + 504 (adapter->txs_ring_size + 505 txs_write_ptr - 2); 506 } else { 507 txs = adapter->txs_ring + (txs_write_ptr - 2); 508 } 509 printk(KERN_WARNING 510 "txs-before:0x%08x\n", 511 *(u32 *)txs); 512 txs = old_txs; 513 } 514 515 /* 4for TPH */ 516 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3); 517 if (txd_read_ptr >= adapter->txd_ring_size) 518 txd_read_ptr -= adapter->txd_ring_size; 519 520 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr); 521 522 /* tx statistics: */ 523 if (txs->ok) { 524 netdev->stats.tx_bytes += txs->pkt_size; 525 netdev->stats.tx_packets++; 526 } 527 else 528 netdev->stats.tx_errors++; 529 530 if (txs->defer) 531 netdev->stats.collisions++; 532 if (txs->abort_col) 533 netdev->stats.tx_aborted_errors++; 534 if (txs->late_col) 535 netdev->stats.tx_window_errors++; 536 if (txs->underrun) 537 netdev->stats.tx_fifo_errors++; 538 } while (1); 539 540 if (free_hole) { 541 if (netif_queue_stopped(adapter->netdev) && 542 netif_carrier_ok(adapter->netdev)) 543 netif_wake_queue(adapter->netdev); 544 } 545} 546 547static void atl2_check_for_link(struct atl2_adapter *adapter) 548{ 549 struct net_device *netdev = adapter->netdev; 550 u16 phy_data = 0; 551 552 spin_lock(&adapter->stats_lock); 553 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 554 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 555 spin_unlock(&adapter->stats_lock); 556 557 /* notify upper layer link down ASAP */ 558 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */ 559 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 560 printk(KERN_INFO "%s: %s NIC Link is Down\n", 561 atl2_driver_name, netdev->name); 562 adapter->link_speed = SPEED_0; 563 netif_carrier_off(netdev); 564 netif_stop_queue(netdev); 565 } 566 } 567 schedule_work(&adapter->link_chg_task); 568} 569 570static inline void atl2_clear_phy_int(struct atl2_adapter *adapter) 571{ 572 u16 phy_data; 573 spin_lock(&adapter->stats_lock); 574 atl2_read_phy_reg(&adapter->hw, 19, &phy_data); 575 spin_unlock(&adapter->stats_lock); 576} 577 578/** 579 * atl2_intr - Interrupt Handler 580 * @irq: interrupt number 581 * @data: pointer to a network interface device structure 582 */ 583static irqreturn_t atl2_intr(int irq, void *data) 584{ 585 struct atl2_adapter *adapter = netdev_priv(data); 586 struct atl2_hw *hw = &adapter->hw; 587 u32 status; 588 589 status = ATL2_READ_REG(hw, REG_ISR); 590 if (0 == status) 591 return IRQ_NONE; 592 593 /* link event */ 594 if (status & ISR_PHY) 595 atl2_clear_phy_int(adapter); 596 597 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 598 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); 599 600 /* check if PCIE PHY Link down */ 601 if (status & ISR_PHY_LINKDOWN) { 602 if (netif_running(adapter->netdev)) { /* reset MAC */ 603 ATL2_WRITE_REG(hw, REG_ISR, 0); 604 ATL2_WRITE_REG(hw, REG_IMR, 0); 605 ATL2_WRITE_FLUSH(hw); 606 schedule_work(&adapter->reset_task); 607 return IRQ_HANDLED; 608 } 609 } 610 611 /* check if DMA read/write error? */ 612 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 613 ATL2_WRITE_REG(hw, REG_ISR, 0); 614 ATL2_WRITE_REG(hw, REG_IMR, 0); 615 ATL2_WRITE_FLUSH(hw); 616 schedule_work(&adapter->reset_task); 617 return IRQ_HANDLED; 618 } 619 620 /* link event */ 621 if (status & (ISR_PHY | ISR_MANUAL)) { 622 adapter->netdev->stats.tx_carrier_errors++; 623 atl2_check_for_link(adapter); 624 } 625 626 /* transmit event */ 627 if (status & ISR_TX_EVENT) 628 atl2_intr_tx(adapter); 629 630 /* rx exception */ 631 if (status & ISR_RX_EVENT) 632 atl2_intr_rx(adapter); 633 634 /* re-enable Interrupt */ 635 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 636 return IRQ_HANDLED; 637} 638 639static int atl2_request_irq(struct atl2_adapter *adapter) 640{ 641 struct net_device *netdev = adapter->netdev; 642 int flags, err = 0; 643 644 flags = IRQF_SHARED; 645 adapter->have_msi = true; 646 err = pci_enable_msi(adapter->pdev); 647 if (err) 648 adapter->have_msi = false; 649 650 if (adapter->have_msi) 651 flags &= ~IRQF_SHARED; 652 653 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name, 654 netdev); 655} 656 657/** 658 * atl2_free_ring_resources - Free Tx / RX descriptor Resources 659 * @adapter: board private structure 660 * 661 * Free all transmit software resources 662 */ 663static void atl2_free_ring_resources(struct atl2_adapter *adapter) 664{ 665 struct pci_dev *pdev = adapter->pdev; 666 dma_free_coherent(&pdev->dev, adapter->ring_size, 667 adapter->ring_vir_addr, adapter->ring_dma); 668} 669 670/** 671 * atl2_open - Called when a network interface is made active 672 * @netdev: network interface device structure 673 * 674 * Returns 0 on success, negative value on failure 675 * 676 * The open entry point is called when a network interface is made 677 * active by the system (IFF_UP). At this point all resources needed 678 * for transmit and receive operations are allocated, the interrupt 679 * handler is registered with the OS, the watchdog timer is started, 680 * and the stack is notified that the interface is ready. 681 */ 682static int atl2_open(struct net_device *netdev) 683{ 684 struct atl2_adapter *adapter = netdev_priv(netdev); 685 int err; 686 u32 val; 687 688 /* disallow open during test */ 689 if (test_bit(__ATL2_TESTING, &adapter->flags)) 690 return -EBUSY; 691 692 /* allocate transmit descriptors */ 693 err = atl2_setup_ring_resources(adapter); 694 if (err) 695 return err; 696 697 err = atl2_init_hw(&adapter->hw); 698 if (err) { 699 err = -EIO; 700 goto err_init_hw; 701 } 702 703 /* hardware has been reset, we need to reload some things */ 704 atl2_set_multi(netdev); 705 init_ring_ptrs(adapter); 706 707 atl2_restore_vlan(adapter); 708 709 if (atl2_configure(adapter)) { 710 err = -EIO; 711 goto err_config; 712 } 713 714 err = atl2_request_irq(adapter); 715 if (err) 716 goto err_req_irq; 717 718 clear_bit(__ATL2_DOWN, &adapter->flags); 719 720 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ)); 721 722 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 723 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, 724 val | MASTER_CTRL_MANUAL_INT); 725 726 atl2_irq_enable(adapter); 727 728 return 0; 729 730err_init_hw: 731err_req_irq: 732err_config: 733 atl2_free_ring_resources(adapter); 734 atl2_reset_hw(&adapter->hw); 735 736 return err; 737} 738 739static void atl2_down(struct atl2_adapter *adapter) 740{ 741 struct net_device *netdev = adapter->netdev; 742 743 /* signal that we're down so the interrupt handler does not 744 * reschedule our watchdog timer */ 745 set_bit(__ATL2_DOWN, &adapter->flags); 746 747 netif_tx_disable(netdev); 748 749 /* reset MAC to disable all RX/TX */ 750 atl2_reset_hw(&adapter->hw); 751 msleep(1); 752 753 atl2_irq_disable(adapter); 754 755 del_timer_sync(&adapter->watchdog_timer); 756 del_timer_sync(&adapter->phy_config_timer); 757 clear_bit(0, &adapter->cfg_phy); 758 759 netif_carrier_off(netdev); 760 adapter->link_speed = SPEED_0; 761 adapter->link_duplex = -1; 762} 763 764static void atl2_free_irq(struct atl2_adapter *adapter) 765{ 766 struct net_device *netdev = adapter->netdev; 767 768 free_irq(adapter->pdev->irq, netdev); 769 770#ifdef CONFIG_PCI_MSI 771 if (adapter->have_msi) 772 pci_disable_msi(adapter->pdev); 773#endif 774} 775 776/** 777 * atl2_close - Disables a network interface 778 * @netdev: network interface device structure 779 * 780 * Returns 0, this is not allowed to fail 781 * 782 * The close entry point is called when an interface is de-activated 783 * by the OS. The hardware is still under the drivers control, but 784 * needs to be disabled. A global MAC reset is issued to stop the 785 * hardware, and all transmit and receive resources are freed. 786 */ 787static int atl2_close(struct net_device *netdev) 788{ 789 struct atl2_adapter *adapter = netdev_priv(netdev); 790 791 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 792 793 atl2_down(adapter); 794 atl2_free_irq(adapter); 795 atl2_free_ring_resources(adapter); 796 797 return 0; 798} 799 800static inline int TxsFreeUnit(struct atl2_adapter *adapter) 801{ 802 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 803 804 return (adapter->txs_next_clear >= txs_write_ptr) ? 805 (int) (adapter->txs_ring_size - adapter->txs_next_clear + 806 txs_write_ptr - 1) : 807 (int) (txs_write_ptr - adapter->txs_next_clear - 1); 808} 809 810static inline int TxdFreeBytes(struct atl2_adapter *adapter) 811{ 812 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr); 813 814 return (adapter->txd_write_ptr >= txd_read_ptr) ? 815 (int) (adapter->txd_ring_size - adapter->txd_write_ptr + 816 txd_read_ptr - 1) : 817 (int) (txd_read_ptr - adapter->txd_write_ptr - 1); 818} 819 820static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb, 821 struct net_device *netdev) 822{ 823 struct atl2_adapter *adapter = netdev_priv(netdev); 824 struct tx_pkt_header *txph; 825 u32 offset, copy_len; 826 int txs_unused; 827 int txbuf_unused; 828 829 if (test_bit(__ATL2_DOWN, &adapter->flags)) { 830 dev_kfree_skb_any(skb); 831 return NETDEV_TX_OK; 832 } 833 834 if (unlikely(skb->len <= 0)) { 835 dev_kfree_skb_any(skb); 836 return NETDEV_TX_OK; 837 } 838 839 txs_unused = TxsFreeUnit(adapter); 840 txbuf_unused = TxdFreeBytes(adapter); 841 842 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused || 843 txs_unused < 1) { 844 /* not enough resources */ 845 netif_stop_queue(netdev); 846 return NETDEV_TX_BUSY; 847 } 848 849 offset = adapter->txd_write_ptr; 850 851 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset); 852 853 *(u32 *)txph = 0; 854 txph->pkt_size = skb->len; 855 856 offset += 4; 857 if (offset >= adapter->txd_ring_size) 858 offset -= adapter->txd_ring_size; 859 copy_len = adapter->txd_ring_size - offset; 860 if (copy_len >= skb->len) { 861 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len); 862 offset += ((u32)(skb->len + 3) & ~3); 863 } else { 864 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len); 865 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len, 866 skb->len-copy_len); 867 offset = ((u32)(skb->len-copy_len + 3) & ~3); 868 } 869#ifdef NETIF_F_HW_VLAN_CTAG_TX 870 if (skb_vlan_tag_present(skb)) { 871 u16 vlan_tag = skb_vlan_tag_get(skb); 872 vlan_tag = (vlan_tag << 4) | 873 (vlan_tag >> 13) | 874 ((vlan_tag >> 9) & 0x8); 875 txph->ins_vlan = 1; 876 txph->vlan = vlan_tag; 877 } 878#endif 879 if (offset >= adapter->txd_ring_size) 880 offset -= adapter->txd_ring_size; 881 adapter->txd_write_ptr = offset; 882 883 /* clear txs before send */ 884 adapter->txs_ring[adapter->txs_next_clear].update = 0; 885 if (++adapter->txs_next_clear == adapter->txs_ring_size) 886 adapter->txs_next_clear = 0; 887 888 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, 889 (adapter->txd_write_ptr >> 2)); 890 891 dev_consume_skb_any(skb); 892 return NETDEV_TX_OK; 893} 894 895/** 896 * atl2_change_mtu - Change the Maximum Transfer Unit 897 * @netdev: network interface device structure 898 * @new_mtu: new value for maximum frame size 899 * 900 * Returns 0 on success, negative on failure 901 */ 902static int atl2_change_mtu(struct net_device *netdev, int new_mtu) 903{ 904 struct atl2_adapter *adapter = netdev_priv(netdev); 905 struct atl2_hw *hw = &adapter->hw; 906 907 /* set MTU */ 908 netdev->mtu = new_mtu; 909 hw->max_frame_size = new_mtu; 910 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ETH_HLEN + 911 VLAN_HLEN + ETH_FCS_LEN); 912 913 return 0; 914} 915 916/** 917 * atl2_set_mac - Change the Ethernet Address of the NIC 918 * @netdev: network interface device structure 919 * @p: pointer to an address structure 920 * 921 * Returns 0 on success, negative on failure 922 */ 923static int atl2_set_mac(struct net_device *netdev, void *p) 924{ 925 struct atl2_adapter *adapter = netdev_priv(netdev); 926 struct sockaddr *addr = p; 927 928 if (!is_valid_ether_addr(addr->sa_data)) 929 return -EADDRNOTAVAIL; 930 931 if (netif_running(netdev)) 932 return -EBUSY; 933 934 eth_hw_addr_set(netdev, addr->sa_data); 935 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); 936 937 atl2_set_mac_addr(&adapter->hw); 938 939 return 0; 940} 941 942static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 943{ 944 struct atl2_adapter *adapter = netdev_priv(netdev); 945 struct mii_ioctl_data *data = if_mii(ifr); 946 unsigned long flags; 947 948 switch (cmd) { 949 case SIOCGMIIPHY: 950 data->phy_id = 0; 951 break; 952 case SIOCGMIIREG: 953 spin_lock_irqsave(&adapter->stats_lock, flags); 954 if (atl2_read_phy_reg(&adapter->hw, 955 data->reg_num & 0x1F, &data->val_out)) { 956 spin_unlock_irqrestore(&adapter->stats_lock, flags); 957 return -EIO; 958 } 959 spin_unlock_irqrestore(&adapter->stats_lock, flags); 960 break; 961 case SIOCSMIIREG: 962 if (data->reg_num & ~(0x1F)) 963 return -EFAULT; 964 spin_lock_irqsave(&adapter->stats_lock, flags); 965 if (atl2_write_phy_reg(&adapter->hw, data->reg_num, 966 data->val_in)) { 967 spin_unlock_irqrestore(&adapter->stats_lock, flags); 968 return -EIO; 969 } 970 spin_unlock_irqrestore(&adapter->stats_lock, flags); 971 break; 972 default: 973 return -EOPNOTSUPP; 974 } 975 return 0; 976} 977 978static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 979{ 980 switch (cmd) { 981 case SIOCGMIIPHY: 982 case SIOCGMIIREG: 983 case SIOCSMIIREG: 984 return atl2_mii_ioctl(netdev, ifr, cmd); 985#ifdef ETHTOOL_OPS_COMPAT 986 case SIOCETHTOOL: 987 return ethtool_ioctl(ifr); 988#endif 989 default: 990 return -EOPNOTSUPP; 991 } 992} 993 994/** 995 * atl2_tx_timeout - Respond to a Tx Hang 996 * @netdev: network interface device structure 997 * @txqueue: index of the hanging transmit queue 998 */ 999static void atl2_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1000{ 1001 struct atl2_adapter *adapter = netdev_priv(netdev); 1002 1003 /* Do the reset outside of interrupt context */ 1004 schedule_work(&adapter->reset_task); 1005} 1006 1007/** 1008 * atl2_watchdog - Timer Call-back 1009 * @t: timer list containing a pointer to netdev cast into an unsigned long 1010 */ 1011static void atl2_watchdog(struct timer_list *t) 1012{ 1013 struct atl2_adapter *adapter = from_timer(adapter, t, watchdog_timer); 1014 1015 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1016 u32 drop_rxd, drop_rxs; 1017 unsigned long flags; 1018 1019 spin_lock_irqsave(&adapter->stats_lock, flags); 1020 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); 1021 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); 1022 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1023 1024 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs; 1025 1026 /* Reset the timer */ 1027 mod_timer(&adapter->watchdog_timer, 1028 round_jiffies(jiffies + 4 * HZ)); 1029 } 1030} 1031 1032/** 1033 * atl2_phy_config - Timer Call-back 1034 * @t: timer list containing a pointer to netdev cast into an unsigned long 1035 */ 1036static void atl2_phy_config(struct timer_list *t) 1037{ 1038 struct atl2_adapter *adapter = from_timer(adapter, t, 1039 phy_config_timer); 1040 struct atl2_hw *hw = &adapter->hw; 1041 unsigned long flags; 1042 1043 spin_lock_irqsave(&adapter->stats_lock, flags); 1044 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 1045 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN | 1046 MII_CR_RESTART_AUTO_NEG); 1047 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1048 clear_bit(0, &adapter->cfg_phy); 1049} 1050 1051static int atl2_up(struct atl2_adapter *adapter) 1052{ 1053 struct net_device *netdev = adapter->netdev; 1054 int err = 0; 1055 u32 val; 1056 1057 /* hardware has been reset, we need to reload some things */ 1058 1059 err = atl2_init_hw(&adapter->hw); 1060 if (err) { 1061 err = -EIO; 1062 return err; 1063 } 1064 1065 atl2_set_multi(netdev); 1066 init_ring_ptrs(adapter); 1067 1068 atl2_restore_vlan(adapter); 1069 1070 if (atl2_configure(adapter)) { 1071 err = -EIO; 1072 goto err_up; 1073 } 1074 1075 clear_bit(__ATL2_DOWN, &adapter->flags); 1076 1077 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 1078 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | 1079 MASTER_CTRL_MANUAL_INT); 1080 1081 atl2_irq_enable(adapter); 1082 1083err_up: 1084 return err; 1085} 1086 1087static void atl2_reinit_locked(struct atl2_adapter *adapter) 1088{ 1089 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1090 msleep(1); 1091 atl2_down(adapter); 1092 atl2_up(adapter); 1093 clear_bit(__ATL2_RESETTING, &adapter->flags); 1094} 1095 1096static void atl2_reset_task(struct work_struct *work) 1097{ 1098 struct atl2_adapter *adapter; 1099 adapter = container_of(work, struct atl2_adapter, reset_task); 1100 1101 atl2_reinit_locked(adapter); 1102} 1103 1104static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter) 1105{ 1106 u32 value; 1107 struct atl2_hw *hw = &adapter->hw; 1108 struct net_device *netdev = adapter->netdev; 1109 1110 /* Config MAC CTRL Register */ 1111 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1112 1113 /* duplex */ 1114 if (FULL_DUPLEX == adapter->link_duplex) 1115 value |= MAC_CTRL_DUPLX; 1116 1117 /* flow control */ 1118 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 1119 1120 /* PAD & CRC */ 1121 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1122 1123 /* preamble length */ 1124 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << 1125 MAC_CTRL_PRMLEN_SHIFT); 1126 1127 /* vlan */ 1128 __atl2_vlan_mode(netdev->features, &value); 1129 1130 /* filter mode */ 1131 value |= MAC_CTRL_BC_EN; 1132 if (netdev->flags & IFF_PROMISC) 1133 value |= MAC_CTRL_PROMIS_EN; 1134 else if (netdev->flags & IFF_ALLMULTI) 1135 value |= MAC_CTRL_MC_ALL_EN; 1136 1137 /* half retry buffer */ 1138 value |= (((u32)(adapter->hw.retry_buf & 1139 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1140 1141 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1142} 1143 1144static int atl2_check_link(struct atl2_adapter *adapter) 1145{ 1146 struct atl2_hw *hw = &adapter->hw; 1147 struct net_device *netdev = adapter->netdev; 1148 int ret_val; 1149 u16 speed, duplex, phy_data; 1150 int reconfig = 0; 1151 1152 /* MII_BMSR must read twise */ 1153 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1154 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1155 if (!(phy_data&BMSR_LSTATUS)) { /* link down */ 1156 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 1157 u32 value; 1158 /* disable rx */ 1159 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1160 value &= ~MAC_CTRL_RX_EN; 1161 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1162 adapter->link_speed = SPEED_0; 1163 netif_carrier_off(netdev); 1164 netif_stop_queue(netdev); 1165 } 1166 return 0; 1167 } 1168 1169 /* Link Up */ 1170 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1171 if (ret_val) 1172 return ret_val; 1173 switch (hw->MediaType) { 1174 case MEDIA_TYPE_100M_FULL: 1175 if (speed != SPEED_100 || duplex != FULL_DUPLEX) 1176 reconfig = 1; 1177 break; 1178 case MEDIA_TYPE_100M_HALF: 1179 if (speed != SPEED_100 || duplex != HALF_DUPLEX) 1180 reconfig = 1; 1181 break; 1182 case MEDIA_TYPE_10M_FULL: 1183 if (speed != SPEED_10 || duplex != FULL_DUPLEX) 1184 reconfig = 1; 1185 break; 1186 case MEDIA_TYPE_10M_HALF: 1187 if (speed != SPEED_10 || duplex != HALF_DUPLEX) 1188 reconfig = 1; 1189 break; 1190 } 1191 /* link result is our setting */ 1192 if (reconfig == 0) { 1193 if (adapter->link_speed != speed || 1194 adapter->link_duplex != duplex) { 1195 adapter->link_speed = speed; 1196 adapter->link_duplex = duplex; 1197 atl2_setup_mac_ctrl(adapter); 1198 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n", 1199 atl2_driver_name, netdev->name, 1200 adapter->link_speed, 1201 adapter->link_duplex == FULL_DUPLEX ? 1202 "Full Duplex" : "Half Duplex"); 1203 } 1204 1205 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */ 1206 netif_carrier_on(netdev); 1207 netif_wake_queue(netdev); 1208 } 1209 return 0; 1210 } 1211 1212 /* change original link status */ 1213 if (netif_carrier_ok(netdev)) { 1214 u32 value; 1215 /* disable rx */ 1216 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1217 value &= ~MAC_CTRL_RX_EN; 1218 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1219 1220 adapter->link_speed = SPEED_0; 1221 netif_carrier_off(netdev); 1222 netif_stop_queue(netdev); 1223 } 1224 1225 /* auto-neg, insert timer to re-config phy 1226 * (if interval smaller than 5 seconds, something strange) */ 1227 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1228 if (!test_and_set_bit(0, &adapter->cfg_phy)) 1229 mod_timer(&adapter->phy_config_timer, 1230 round_jiffies(jiffies + 5 * HZ)); 1231 } 1232 1233 return 0; 1234} 1235 1236/** 1237 * atl2_link_chg_task - deal with link change event Out of interrupt context 1238 * @work: pointer to work struct with private info 1239 */ 1240static void atl2_link_chg_task(struct work_struct *work) 1241{ 1242 struct atl2_adapter *adapter; 1243 unsigned long flags; 1244 1245 adapter = container_of(work, struct atl2_adapter, link_chg_task); 1246 1247 spin_lock_irqsave(&adapter->stats_lock, flags); 1248 atl2_check_link(adapter); 1249 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1250} 1251 1252static void atl2_setup_pcicmd(struct pci_dev *pdev) 1253{ 1254 u16 cmd; 1255 1256 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1257 1258 if (cmd & PCI_COMMAND_INTX_DISABLE) 1259 cmd &= ~PCI_COMMAND_INTX_DISABLE; 1260 if (cmd & PCI_COMMAND_IO) 1261 cmd &= ~PCI_COMMAND_IO; 1262 if (0 == (cmd & PCI_COMMAND_MEMORY)) 1263 cmd |= PCI_COMMAND_MEMORY; 1264 if (0 == (cmd & PCI_COMMAND_MASTER)) 1265 cmd |= PCI_COMMAND_MASTER; 1266 pci_write_config_word(pdev, PCI_COMMAND, cmd); 1267 1268 /* 1269 * some motherboards BIOS(PXE/EFI) driver may set PME 1270 * while they transfer control to OS (Windows/Linux) 1271 * so we should clear this bit before NIC work normally 1272 */ 1273 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); 1274} 1275 1276#ifdef CONFIG_NET_POLL_CONTROLLER 1277static void atl2_poll_controller(struct net_device *netdev) 1278{ 1279 disable_irq(netdev->irq); 1280 atl2_intr(netdev->irq, netdev); 1281 enable_irq(netdev->irq); 1282} 1283#endif 1284 1285 1286static const struct net_device_ops atl2_netdev_ops = { 1287 .ndo_open = atl2_open, 1288 .ndo_stop = atl2_close, 1289 .ndo_start_xmit = atl2_xmit_frame, 1290 .ndo_set_rx_mode = atl2_set_multi, 1291 .ndo_validate_addr = eth_validate_addr, 1292 .ndo_set_mac_address = atl2_set_mac, 1293 .ndo_change_mtu = atl2_change_mtu, 1294 .ndo_fix_features = atl2_fix_features, 1295 .ndo_set_features = atl2_set_features, 1296 .ndo_eth_ioctl = atl2_ioctl, 1297 .ndo_tx_timeout = atl2_tx_timeout, 1298#ifdef CONFIG_NET_POLL_CONTROLLER 1299 .ndo_poll_controller = atl2_poll_controller, 1300#endif 1301}; 1302 1303/** 1304 * atl2_probe - Device Initialization Routine 1305 * @pdev: PCI device information struct 1306 * @ent: entry in atl2_pci_tbl 1307 * 1308 * Returns 0 on success, negative on failure 1309 * 1310 * atl2_probe initializes an adapter identified by a pci_dev structure. 1311 * The OS initialization, configuring of the adapter private structure, 1312 * and a hardware reset occur. 1313 */ 1314static int atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1315{ 1316 struct net_device *netdev; 1317 struct atl2_adapter *adapter; 1318 static int cards_found = 0; 1319 unsigned long mmio_start; 1320 int mmio_len; 1321 int err; 1322 1323 err = pci_enable_device(pdev); 1324 if (err) 1325 return err; 1326 1327 /* 1328 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA 1329 * until the kernel has the proper infrastructure to support 64-bit DMA 1330 * on these devices. 1331 */ 1332 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) && 1333 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 1334 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n"); 1335 err = -EIO; 1336 goto err_dma; 1337 } 1338 1339 /* Mark all PCI regions associated with PCI device 1340 * pdev as being reserved by owner atl2_driver_name */ 1341 err = pci_request_regions(pdev, atl2_driver_name); 1342 if (err) 1343 goto err_pci_reg; 1344 1345 /* Enables bus-mastering on the device and calls 1346 * pcibios_set_master to do the needed arch specific settings */ 1347 pci_set_master(pdev); 1348 1349 netdev = alloc_etherdev(sizeof(struct atl2_adapter)); 1350 if (!netdev) { 1351 err = -ENOMEM; 1352 goto err_alloc_etherdev; 1353 } 1354 1355 SET_NETDEV_DEV(netdev, &pdev->dev); 1356 1357 pci_set_drvdata(pdev, netdev); 1358 adapter = netdev_priv(netdev); 1359 adapter->netdev = netdev; 1360 adapter->pdev = pdev; 1361 adapter->hw.back = adapter; 1362 1363 mmio_start = pci_resource_start(pdev, 0x0); 1364 mmio_len = pci_resource_len(pdev, 0x0); 1365 1366 adapter->hw.mem_rang = (u32)mmio_len; 1367 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 1368 if (!adapter->hw.hw_addr) { 1369 err = -EIO; 1370 goto err_ioremap; 1371 } 1372 1373 atl2_setup_pcicmd(pdev); 1374 1375 netdev->netdev_ops = &atl2_netdev_ops; 1376 netdev->ethtool_ops = &atl2_ethtool_ops; 1377 netdev->watchdog_timeo = 5 * HZ; 1378 netdev->min_mtu = 40; 1379 netdev->max_mtu = ETH_DATA_LEN + VLAN_HLEN; 1380 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 1381 1382 netdev->mem_start = mmio_start; 1383 netdev->mem_end = mmio_start + mmio_len; 1384 adapter->bd_number = cards_found; 1385 adapter->pci_using_64 = false; 1386 1387 /* setup the private structure */ 1388 err = atl2_sw_init(adapter); 1389 if (err) 1390 goto err_sw_init; 1391 1392 netdev->hw_features = NETIF_F_HW_VLAN_CTAG_RX; 1393 netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 1394 1395 /* Init PHY as early as possible due to power saving issue */ 1396 atl2_phy_init(&adapter->hw); 1397 1398 /* reset the controller to 1399 * put the device in a known good starting state */ 1400 1401 if (atl2_reset_hw(&adapter->hw)) { 1402 err = -EIO; 1403 goto err_reset; 1404 } 1405 1406 /* copy the MAC address out of the EEPROM */ 1407 atl2_read_mac_addr(&adapter->hw); 1408 eth_hw_addr_set(netdev, adapter->hw.mac_addr); 1409 if (!is_valid_ether_addr(netdev->dev_addr)) { 1410 err = -EIO; 1411 goto err_eeprom; 1412 } 1413 1414 atl2_check_options(adapter); 1415 1416 timer_setup(&adapter->watchdog_timer, atl2_watchdog, 0); 1417 1418 timer_setup(&adapter->phy_config_timer, atl2_phy_config, 0); 1419 1420 INIT_WORK(&adapter->reset_task, atl2_reset_task); 1421 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task); 1422 1423 strcpy(netdev->name, "eth%d"); /* ?? */ 1424 err = register_netdev(netdev); 1425 if (err) 1426 goto err_register; 1427 1428 /* assume we have no link for now */ 1429 netif_carrier_off(netdev); 1430 netif_stop_queue(netdev); 1431 1432 cards_found++; 1433 1434 return 0; 1435 1436err_reset: 1437err_register: 1438err_sw_init: 1439err_eeprom: 1440 iounmap(adapter->hw.hw_addr); 1441err_ioremap: 1442 free_netdev(netdev); 1443err_alloc_etherdev: 1444 pci_release_regions(pdev); 1445err_pci_reg: 1446err_dma: 1447 pci_disable_device(pdev); 1448 return err; 1449} 1450 1451/** 1452 * atl2_remove - Device Removal Routine 1453 * @pdev: PCI device information struct 1454 * 1455 * atl2_remove is called by the PCI subsystem to alert the driver 1456 * that it should release a PCI device. The could be caused by a 1457 * Hot-Plug event, or because the driver is going to be removed from 1458 * memory. 1459 */ 1460/* FIXME: write the original MAC address back in case it was changed from a 1461 * BIOS-set value, as in atl1 -- CHS */ 1462static void atl2_remove(struct pci_dev *pdev) 1463{ 1464 struct net_device *netdev = pci_get_drvdata(pdev); 1465 struct atl2_adapter *adapter = netdev_priv(netdev); 1466 1467 /* flush_scheduled work may reschedule our watchdog task, so 1468 * explicitly disable watchdog tasks from being rescheduled */ 1469 set_bit(__ATL2_DOWN, &adapter->flags); 1470 1471 del_timer_sync(&adapter->watchdog_timer); 1472 del_timer_sync(&adapter->phy_config_timer); 1473 cancel_work_sync(&adapter->reset_task); 1474 cancel_work_sync(&adapter->link_chg_task); 1475 1476 unregister_netdev(netdev); 1477 1478 atl2_force_ps(&adapter->hw); 1479 1480 iounmap(adapter->hw.hw_addr); 1481 pci_release_regions(pdev); 1482 1483 free_netdev(netdev); 1484 1485 pci_disable_device(pdev); 1486} 1487 1488static int atl2_suspend(struct pci_dev *pdev, pm_message_t state) 1489{ 1490 struct net_device *netdev = pci_get_drvdata(pdev); 1491 struct atl2_adapter *adapter = netdev_priv(netdev); 1492 struct atl2_hw *hw = &adapter->hw; 1493 u16 speed, duplex; 1494 u32 ctrl = 0; 1495 u32 wufc = adapter->wol; 1496 1497#ifdef CONFIG_PM 1498 int retval = 0; 1499#endif 1500 1501 netif_device_detach(netdev); 1502 1503 if (netif_running(netdev)) { 1504 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 1505 atl2_down(adapter); 1506 } 1507 1508#ifdef CONFIG_PM 1509 retval = pci_save_state(pdev); 1510 if (retval) 1511 return retval; 1512#endif 1513 1514 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1515 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1516 if (ctrl & BMSR_LSTATUS) 1517 wufc &= ~ATLX_WUFC_LNKC; 1518 1519 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) { 1520 u32 ret_val; 1521 /* get current link speed & duplex */ 1522 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1523 if (ret_val) { 1524 printk(KERN_DEBUG 1525 "%s: get speed&duplex error while suspend\n", 1526 atl2_driver_name); 1527 goto wol_dis; 1528 } 1529 1530 ctrl = 0; 1531 1532 /* turn on magic packet wol */ 1533 if (wufc & ATLX_WUFC_MAG) 1534 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); 1535 1536 /* ignore Link Chg event when Link is up */ 1537 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1538 1539 /* Config MAC CTRL Register */ 1540 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1541 if (FULL_DUPLEX == adapter->link_duplex) 1542 ctrl |= MAC_CTRL_DUPLX; 1543 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1544 ctrl |= (((u32)adapter->hw.preamble_len & 1545 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 1546 ctrl |= (((u32)(adapter->hw.retry_buf & 1547 MAC_CTRL_HALF_LEFT_BUF_MASK)) << 1548 MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1549 if (wufc & ATLX_WUFC_MAG) { 1550 /* magic packet maybe Broadcast&multicast&Unicast */ 1551 ctrl |= MAC_CTRL_BC_EN; 1552 } 1553 1554 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); 1555 1556 /* pcie patch */ 1557 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1558 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1559 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1560 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1561 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1562 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1563 1564 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1565 goto suspend_exit; 1566 } 1567 1568 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) { 1569 /* link is down, so only LINK CHG WOL event enable */ 1570 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 1571 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1572 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); 1573 1574 /* pcie patch */ 1575 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1576 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1577 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1578 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1579 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1580 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1581 1582 hw->phy_configured = false; /* re-init PHY when resume */ 1583 1584 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1585 1586 goto suspend_exit; 1587 } 1588 1589wol_dis: 1590 /* WOL disabled */ 1591 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); 1592 1593 /* pcie patch */ 1594 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1595 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1596 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1597 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1598 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1599 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1600 1601 atl2_force_ps(hw); 1602 hw->phy_configured = false; /* re-init PHY when resume */ 1603 1604 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1605 1606suspend_exit: 1607 if (netif_running(netdev)) 1608 atl2_free_irq(adapter); 1609 1610 pci_disable_device(pdev); 1611 1612 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1613 1614 return 0; 1615} 1616 1617#ifdef CONFIG_PM 1618static int atl2_resume(struct pci_dev *pdev) 1619{ 1620 struct net_device *netdev = pci_get_drvdata(pdev); 1621 struct atl2_adapter *adapter = netdev_priv(netdev); 1622 u32 err; 1623 1624 pci_set_power_state(pdev, PCI_D0); 1625 pci_restore_state(pdev); 1626 1627 err = pci_enable_device(pdev); 1628 if (err) { 1629 printk(KERN_ERR 1630 "atl2: Cannot enable PCI device from suspend\n"); 1631 return err; 1632 } 1633 1634 pci_set_master(pdev); 1635 1636 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ 1637 1638 pci_enable_wake(pdev, PCI_D3hot, 0); 1639 pci_enable_wake(pdev, PCI_D3cold, 0); 1640 1641 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); 1642 1643 if (netif_running(netdev)) { 1644 err = atl2_request_irq(adapter); 1645 if (err) 1646 return err; 1647 } 1648 1649 atl2_reset_hw(&adapter->hw); 1650 1651 if (netif_running(netdev)) 1652 atl2_up(adapter); 1653 1654 netif_device_attach(netdev); 1655 1656 return 0; 1657} 1658#endif 1659 1660static void atl2_shutdown(struct pci_dev *pdev) 1661{ 1662 atl2_suspend(pdev, PMSG_SUSPEND); 1663} 1664 1665static struct pci_driver atl2_driver = { 1666 .name = atl2_driver_name, 1667 .id_table = atl2_pci_tbl, 1668 .probe = atl2_probe, 1669 .remove = atl2_remove, 1670 /* Power Management Hooks */ 1671 .suspend = atl2_suspend, 1672#ifdef CONFIG_PM 1673 .resume = atl2_resume, 1674#endif 1675 .shutdown = atl2_shutdown, 1676}; 1677 1678module_pci_driver(atl2_driver); 1679 1680static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1681{ 1682 struct atl2_adapter *adapter = hw->back; 1683 pci_read_config_word(adapter->pdev, reg, value); 1684} 1685 1686static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1687{ 1688 struct atl2_adapter *adapter = hw->back; 1689 pci_write_config_word(adapter->pdev, reg, *value); 1690} 1691 1692static int atl2_get_link_ksettings(struct net_device *netdev, 1693 struct ethtool_link_ksettings *cmd) 1694{ 1695 struct atl2_adapter *adapter = netdev_priv(netdev); 1696 struct atl2_hw *hw = &adapter->hw; 1697 u32 supported, advertising; 1698 1699 supported = (SUPPORTED_10baseT_Half | 1700 SUPPORTED_10baseT_Full | 1701 SUPPORTED_100baseT_Half | 1702 SUPPORTED_100baseT_Full | 1703 SUPPORTED_Autoneg | 1704 SUPPORTED_TP); 1705 advertising = ADVERTISED_TP; 1706 1707 advertising |= ADVERTISED_Autoneg; 1708 advertising |= hw->autoneg_advertised; 1709 1710 cmd->base.port = PORT_TP; 1711 cmd->base.phy_address = 0; 1712 1713 if (adapter->link_speed != SPEED_0) { 1714 cmd->base.speed = adapter->link_speed; 1715 if (adapter->link_duplex == FULL_DUPLEX) 1716 cmd->base.duplex = DUPLEX_FULL; 1717 else 1718 cmd->base.duplex = DUPLEX_HALF; 1719 } else { 1720 cmd->base.speed = SPEED_UNKNOWN; 1721 cmd->base.duplex = DUPLEX_UNKNOWN; 1722 } 1723 1724 cmd->base.autoneg = AUTONEG_ENABLE; 1725 1726 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 1727 supported); 1728 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 1729 advertising); 1730 1731 return 0; 1732} 1733 1734static int atl2_set_link_ksettings(struct net_device *netdev, 1735 const struct ethtool_link_ksettings *cmd) 1736{ 1737 struct atl2_adapter *adapter = netdev_priv(netdev); 1738 struct atl2_hw *hw = &adapter->hw; 1739 u32 advertising; 1740 1741 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1742 cmd->link_modes.advertising); 1743 1744 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1745 msleep(1); 1746 1747 if (cmd->base.autoneg == AUTONEG_ENABLE) { 1748#define MY_ADV_MASK (ADVERTISE_10_HALF | \ 1749 ADVERTISE_10_FULL | \ 1750 ADVERTISE_100_HALF| \ 1751 ADVERTISE_100_FULL) 1752 1753 if ((advertising & MY_ADV_MASK) == MY_ADV_MASK) { 1754 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; 1755 hw->autoneg_advertised = MY_ADV_MASK; 1756 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_100_FULL) { 1757 hw->MediaType = MEDIA_TYPE_100M_FULL; 1758 hw->autoneg_advertised = ADVERTISE_100_FULL; 1759 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_100_HALF) { 1760 hw->MediaType = MEDIA_TYPE_100M_HALF; 1761 hw->autoneg_advertised = ADVERTISE_100_HALF; 1762 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_10_FULL) { 1763 hw->MediaType = MEDIA_TYPE_10M_FULL; 1764 hw->autoneg_advertised = ADVERTISE_10_FULL; 1765 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_10_HALF) { 1766 hw->MediaType = MEDIA_TYPE_10M_HALF; 1767 hw->autoneg_advertised = ADVERTISE_10_HALF; 1768 } else { 1769 clear_bit(__ATL2_RESETTING, &adapter->flags); 1770 return -EINVAL; 1771 } 1772 advertising = hw->autoneg_advertised | 1773 ADVERTISED_TP | ADVERTISED_Autoneg; 1774 } else { 1775 clear_bit(__ATL2_RESETTING, &adapter->flags); 1776 return -EINVAL; 1777 } 1778 1779 /* reset the link */ 1780 if (netif_running(adapter->netdev)) { 1781 atl2_down(adapter); 1782 atl2_up(adapter); 1783 } else 1784 atl2_reset_hw(&adapter->hw); 1785 1786 clear_bit(__ATL2_RESETTING, &adapter->flags); 1787 return 0; 1788} 1789 1790static u32 atl2_get_msglevel(struct net_device *netdev) 1791{ 1792 return 0; 1793} 1794 1795/* 1796 * It's sane for this to be empty, but we might want to take advantage of this. 1797 */ 1798static void atl2_set_msglevel(struct net_device *netdev, u32 data) 1799{ 1800} 1801 1802static int atl2_get_regs_len(struct net_device *netdev) 1803{ 1804#define ATL2_REGS_LEN 42 1805 return sizeof(u32) * ATL2_REGS_LEN; 1806} 1807 1808static void atl2_get_regs(struct net_device *netdev, 1809 struct ethtool_regs *regs, void *p) 1810{ 1811 struct atl2_adapter *adapter = netdev_priv(netdev); 1812 struct atl2_hw *hw = &adapter->hw; 1813 u32 *regs_buff = p; 1814 u16 phy_data; 1815 1816 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN); 1817 1818 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 1819 1820 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); 1821 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 1822 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); 1823 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); 1824 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); 1825 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); 1826 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); 1827 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); 1828 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); 1829 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); 1830 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); 1831 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); 1832 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); 1833 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); 1834 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); 1835 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 1836 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); 1837 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); 1838 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); 1839 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); 1840 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); 1841 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); 1842 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); 1843 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); 1844 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); 1845 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); 1846 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); 1847 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); 1848 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); 1849 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); 1850 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); 1851 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); 1852 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); 1853 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); 1854 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); 1855 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); 1856 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); 1857 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); 1858 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); 1859 1860 atl2_read_phy_reg(hw, MII_BMCR, &phy_data); 1861 regs_buff[40] = (u32)phy_data; 1862 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1863 regs_buff[41] = (u32)phy_data; 1864} 1865 1866static int atl2_get_eeprom_len(struct net_device *netdev) 1867{ 1868 struct atl2_adapter *adapter = netdev_priv(netdev); 1869 1870 if (!atl2_check_eeprom_exist(&adapter->hw)) 1871 return 512; 1872 else 1873 return 0; 1874} 1875 1876static int atl2_get_eeprom(struct net_device *netdev, 1877 struct ethtool_eeprom *eeprom, u8 *bytes) 1878{ 1879 struct atl2_adapter *adapter = netdev_priv(netdev); 1880 struct atl2_hw *hw = &adapter->hw; 1881 u32 *eeprom_buff; 1882 int first_dword, last_dword; 1883 int ret_val = 0; 1884 int i; 1885 1886 if (eeprom->len == 0) 1887 return -EINVAL; 1888 1889 if (atl2_check_eeprom_exist(hw)) 1890 return -EINVAL; 1891 1892 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 1893 1894 first_dword = eeprom->offset >> 2; 1895 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1896 1897 eeprom_buff = kmalloc_array(last_dword - first_dword + 1, sizeof(u32), 1898 GFP_KERNEL); 1899 if (!eeprom_buff) 1900 return -ENOMEM; 1901 1902 for (i = first_dword; i < last_dword; i++) { 1903 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) { 1904 ret_val = -EIO; 1905 goto free; 1906 } 1907 } 1908 1909 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), 1910 eeprom->len); 1911free: 1912 kfree(eeprom_buff); 1913 1914 return ret_val; 1915} 1916 1917static int atl2_set_eeprom(struct net_device *netdev, 1918 struct ethtool_eeprom *eeprom, u8 *bytes) 1919{ 1920 struct atl2_adapter *adapter = netdev_priv(netdev); 1921 struct atl2_hw *hw = &adapter->hw; 1922 u32 *eeprom_buff; 1923 u32 *ptr; 1924 int max_len, first_dword, last_dword, ret_val = 0; 1925 int i; 1926 1927 if (eeprom->len == 0) 1928 return -EOPNOTSUPP; 1929 1930 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 1931 return -EFAULT; 1932 1933 max_len = 512; 1934 1935 first_dword = eeprom->offset >> 2; 1936 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1937 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 1938 if (!eeprom_buff) 1939 return -ENOMEM; 1940 1941 ptr = eeprom_buff; 1942 1943 if (eeprom->offset & 3) { 1944 /* need read/modify/write of first changed EEPROM word */ 1945 /* only the second byte of the word is being modified */ 1946 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) { 1947 ret_val = -EIO; 1948 goto out; 1949 } 1950 ptr++; 1951 } 1952 if (((eeprom->offset + eeprom->len) & 3)) { 1953 /* 1954 * need read/modify/write of last changed EEPROM word 1955 * only the first byte of the word is being modified 1956 */ 1957 if (!atl2_read_eeprom(hw, last_dword * 4, 1958 &(eeprom_buff[last_dword - first_dword]))) { 1959 ret_val = -EIO; 1960 goto out; 1961 } 1962 } 1963 1964 /* Device's eeprom is always little-endian, word addressable */ 1965 memcpy(ptr, bytes, eeprom->len); 1966 1967 for (i = 0; i < last_dword - first_dword + 1; i++) { 1968 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) { 1969 ret_val = -EIO; 1970 goto out; 1971 } 1972 } 1973 out: 1974 kfree(eeprom_buff); 1975 return ret_val; 1976} 1977 1978static void atl2_get_drvinfo(struct net_device *netdev, 1979 struct ethtool_drvinfo *drvinfo) 1980{ 1981 struct atl2_adapter *adapter = netdev_priv(netdev); 1982 1983 strscpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver)); 1984 strscpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version)); 1985 strscpy(drvinfo->bus_info, pci_name(adapter->pdev), 1986 sizeof(drvinfo->bus_info)); 1987} 1988 1989static void atl2_get_wol(struct net_device *netdev, 1990 struct ethtool_wolinfo *wol) 1991{ 1992 struct atl2_adapter *adapter = netdev_priv(netdev); 1993 1994 wol->supported = WAKE_MAGIC; 1995 wol->wolopts = 0; 1996 1997 if (adapter->wol & ATLX_WUFC_EX) 1998 wol->wolopts |= WAKE_UCAST; 1999 if (adapter->wol & ATLX_WUFC_MC) 2000 wol->wolopts |= WAKE_MCAST; 2001 if (adapter->wol & ATLX_WUFC_BC) 2002 wol->wolopts |= WAKE_BCAST; 2003 if (adapter->wol & ATLX_WUFC_MAG) 2004 wol->wolopts |= WAKE_MAGIC; 2005 if (adapter->wol & ATLX_WUFC_LNKC) 2006 wol->wolopts |= WAKE_PHY; 2007} 2008 2009static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2010{ 2011 struct atl2_adapter *adapter = netdev_priv(netdev); 2012 2013 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2014 return -EOPNOTSUPP; 2015 2016 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)) 2017 return -EOPNOTSUPP; 2018 2019 /* these settings will always override what we currently have */ 2020 adapter->wol = 0; 2021 2022 if (wol->wolopts & WAKE_MAGIC) 2023 adapter->wol |= ATLX_WUFC_MAG; 2024 if (wol->wolopts & WAKE_PHY) 2025 adapter->wol |= ATLX_WUFC_LNKC; 2026 2027 return 0; 2028} 2029 2030static int atl2_nway_reset(struct net_device *netdev) 2031{ 2032 struct atl2_adapter *adapter = netdev_priv(netdev); 2033 if (netif_running(netdev)) 2034 atl2_reinit_locked(adapter); 2035 return 0; 2036} 2037 2038static const struct ethtool_ops atl2_ethtool_ops = { 2039 .get_drvinfo = atl2_get_drvinfo, 2040 .get_regs_len = atl2_get_regs_len, 2041 .get_regs = atl2_get_regs, 2042 .get_wol = atl2_get_wol, 2043 .set_wol = atl2_set_wol, 2044 .get_msglevel = atl2_get_msglevel, 2045 .set_msglevel = atl2_set_msglevel, 2046 .nway_reset = atl2_nway_reset, 2047 .get_link = ethtool_op_get_link, 2048 .get_eeprom_len = atl2_get_eeprom_len, 2049 .get_eeprom = atl2_get_eeprom, 2050 .set_eeprom = atl2_set_eeprom, 2051 .get_link_ksettings = atl2_get_link_ksettings, 2052 .set_link_ksettings = atl2_set_link_ksettings, 2053}; 2054 2055#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \ 2056 (((a) & 0xff00ff00) >> 8)) 2057#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16)) 2058#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8)) 2059 2060/* 2061 * Reset the transmit and receive units; mask and clear all interrupts. 2062 * 2063 * hw - Struct containing variables accessed by shared code 2064 * return : 0 or idle status (if error) 2065 */ 2066static s32 atl2_reset_hw(struct atl2_hw *hw) 2067{ 2068 u32 icr; 2069 u16 pci_cfg_cmd_word; 2070 int i; 2071 2072 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ 2073 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2074 if ((pci_cfg_cmd_word & 2075 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) != 2076 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) { 2077 pci_cfg_cmd_word |= 2078 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER); 2079 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2080 } 2081 2082 /* Clear Interrupt mask to stop board from generating 2083 * interrupts & Clear any pending interrupt events 2084 */ 2085 /* FIXME */ 2086 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */ 2087 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */ 2088 2089 /* Issue Soft Reset to the MAC. This will reset the chip's 2090 * transmit, receive, DMA. It will not effect 2091 * the current PCI configuration. The global reset bit is self- 2092 * clearing, and should clear within a microsecond. 2093 */ 2094 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); 2095 wmb(); 2096 msleep(1); /* delay about 1ms */ 2097 2098 /* Wait at least 10ms for All module to be Idle */ 2099 for (i = 0; i < 10; i++) { 2100 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); 2101 if (!icr) 2102 break; 2103 msleep(1); /* delay 1 ms */ 2104 cpu_relax(); 2105 } 2106 2107 if (icr) 2108 return icr; 2109 2110 return 0; 2111} 2112 2113#define CUSTOM_SPI_CS_SETUP 2 2114#define CUSTOM_SPI_CLK_HI 2 2115#define CUSTOM_SPI_CLK_LO 2 2116#define CUSTOM_SPI_CS_HOLD 2 2117#define CUSTOM_SPI_CS_HI 3 2118 2119static struct atl2_spi_flash_dev flash_table[] = 2120{ 2121/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */ 2122{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 }, 2123{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 }, 2124{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 }, 2125}; 2126 2127static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf) 2128{ 2129 int i; 2130 u32 value; 2131 2132 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); 2133 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); 2134 2135 value = SPI_FLASH_CTRL_WAIT_READY | 2136 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << 2137 SPI_FLASH_CTRL_CS_SETUP_SHIFT | 2138 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << 2139 SPI_FLASH_CTRL_CLK_HI_SHIFT | 2140 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << 2141 SPI_FLASH_CTRL_CLK_LO_SHIFT | 2142 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << 2143 SPI_FLASH_CTRL_CS_HOLD_SHIFT | 2144 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << 2145 SPI_FLASH_CTRL_CS_HI_SHIFT | 2146 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT; 2147 2148 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2149 2150 value |= SPI_FLASH_CTRL_START; 2151 2152 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2153 2154 for (i = 0; i < 10; i++) { 2155 msleep(1); 2156 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2157 if (!(value & SPI_FLASH_CTRL_START)) 2158 break; 2159 } 2160 2161 if (value & SPI_FLASH_CTRL_START) 2162 return false; 2163 2164 *buf = ATL2_READ_REG(hw, REG_SPI_DATA); 2165 2166 return true; 2167} 2168 2169/* 2170 * get_permanent_address 2171 * return 0 if get valid mac address, 2172 */ 2173static int get_permanent_address(struct atl2_hw *hw) 2174{ 2175 u32 Addr[2]; 2176 u32 i, Control; 2177 u16 Register; 2178 u8 EthAddr[ETH_ALEN]; 2179 bool KeyValid; 2180 2181 if (is_valid_ether_addr(hw->perm_mac_addr)) 2182 return 0; 2183 2184 Addr[0] = 0; 2185 Addr[1] = 0; 2186 2187 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ 2188 Register = 0; 2189 KeyValid = false; 2190 2191 /* Read out all EEPROM content */ 2192 i = 0; 2193 while (1) { 2194 if (atl2_read_eeprom(hw, i + 0x100, &Control)) { 2195 if (KeyValid) { 2196 if (Register == REG_MAC_STA_ADDR) 2197 Addr[0] = Control; 2198 else if (Register == 2199 (REG_MAC_STA_ADDR + 4)) 2200 Addr[1] = Control; 2201 KeyValid = false; 2202 } else if ((Control & 0xff) == 0x5A) { 2203 KeyValid = true; 2204 Register = (u16) (Control >> 16); 2205 } else { 2206 /* assume data end while encount an invalid KEYWORD */ 2207 break; 2208 } 2209 } else { 2210 break; /* read error */ 2211 } 2212 i += 4; 2213 } 2214 2215 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2216 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2217 2218 if (is_valid_ether_addr(EthAddr)) { 2219 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2220 return 0; 2221 } 2222 return 1; 2223 } 2224 2225 /* see if SPI flash exists? */ 2226 Addr[0] = 0; 2227 Addr[1] = 0; 2228 Register = 0; 2229 KeyValid = false; 2230 i = 0; 2231 while (1) { 2232 if (atl2_spi_read(hw, i + 0x1f000, &Control)) { 2233 if (KeyValid) { 2234 if (Register == REG_MAC_STA_ADDR) 2235 Addr[0] = Control; 2236 else if (Register == (REG_MAC_STA_ADDR + 4)) 2237 Addr[1] = Control; 2238 KeyValid = false; 2239 } else if ((Control & 0xff) == 0x5A) { 2240 KeyValid = true; 2241 Register = (u16) (Control >> 16); 2242 } else { 2243 break; /* data end */ 2244 } 2245 } else { 2246 break; /* read error */ 2247 } 2248 i += 4; 2249 } 2250 2251 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2252 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]); 2253 if (is_valid_ether_addr(EthAddr)) { 2254 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2255 return 0; 2256 } 2257 /* maybe MAC-address is from BIOS */ 2258 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 2259 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4); 2260 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2261 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2262 2263 if (is_valid_ether_addr(EthAddr)) { 2264 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2265 return 0; 2266 } 2267 2268 return 1; 2269} 2270 2271/* 2272 * Reads the adapter's MAC address from the EEPROM 2273 * 2274 * hw - Struct containing variables accessed by shared code 2275 */ 2276static s32 atl2_read_mac_addr(struct atl2_hw *hw) 2277{ 2278 if (get_permanent_address(hw)) { 2279 /* for test */ 2280 /* FIXME: shouldn't we use eth_random_addr() here? */ 2281 hw->perm_mac_addr[0] = 0x00; 2282 hw->perm_mac_addr[1] = 0x13; 2283 hw->perm_mac_addr[2] = 0x74; 2284 hw->perm_mac_addr[3] = 0x00; 2285 hw->perm_mac_addr[4] = 0x5c; 2286 hw->perm_mac_addr[5] = 0x38; 2287 } 2288 2289 memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN); 2290 2291 return 0; 2292} 2293 2294/* 2295 * Hashes an address to determine its location in the multicast table 2296 * 2297 * hw - Struct containing variables accessed by shared code 2298 * mc_addr - the multicast address to hash 2299 * 2300 * atl2_hash_mc_addr 2301 * purpose 2302 * set hash value for a multicast address 2303 * hash calcu processing : 2304 * 1. calcu 32bit CRC for multicast address 2305 * 2. reverse crc with MSB to LSB 2306 */ 2307static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) 2308{ 2309 u32 crc32, value; 2310 int i; 2311 2312 value = 0; 2313 crc32 = ether_crc_le(6, mc_addr); 2314 2315 for (i = 0; i < 32; i++) 2316 value |= (((crc32 >> i) & 1) << (31 - i)); 2317 2318 return value; 2319} 2320 2321/* 2322 * Sets the bit in the multicast table corresponding to the hash value. 2323 * 2324 * hw - Struct containing variables accessed by shared code 2325 * hash_value - Multicast address hash value 2326 */ 2327static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value) 2328{ 2329 u32 hash_bit, hash_reg; 2330 u32 mta; 2331 2332 /* The HASH Table is a register array of 2 32-bit registers. 2333 * It is treated like an array of 64 bits. We want to set 2334 * bit BitArray[hash_value]. So we figure out what register 2335 * the bit is in, read it, OR in the new bit, then write 2336 * back the new value. The register is determined by the 2337 * upper 7 bits of the hash value and the bit within that 2338 * register are determined by the lower 5 bits of the value. 2339 */ 2340 hash_reg = (hash_value >> 31) & 0x1; 2341 hash_bit = (hash_value >> 26) & 0x1F; 2342 2343 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); 2344 2345 mta |= (1 << hash_bit); 2346 2347 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); 2348} 2349 2350/* 2351 * atl2_init_pcie - init PCIE module 2352 */ 2353static void atl2_init_pcie(struct atl2_hw *hw) 2354{ 2355 u32 value; 2356 value = LTSSM_TEST_MODE_DEF; 2357 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); 2358 2359 value = PCIE_DLL_TX_CTRL1_DEF; 2360 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); 2361} 2362 2363static void atl2_init_flash_opcode(struct atl2_hw *hw) 2364{ 2365 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) 2366 hw->flash_vendor = 0; /* ATMEL */ 2367 2368 /* Init OP table */ 2369 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, 2370 flash_table[hw->flash_vendor].cmdPROGRAM); 2371 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, 2372 flash_table[hw->flash_vendor].cmdSECTOR_ERASE); 2373 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, 2374 flash_table[hw->flash_vendor].cmdCHIP_ERASE); 2375 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, 2376 flash_table[hw->flash_vendor].cmdRDID); 2377 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, 2378 flash_table[hw->flash_vendor].cmdWREN); 2379 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, 2380 flash_table[hw->flash_vendor].cmdRDSR); 2381 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, 2382 flash_table[hw->flash_vendor].cmdWRSR); 2383 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, 2384 flash_table[hw->flash_vendor].cmdREAD); 2385} 2386 2387/******************************************************************** 2388* Performs basic configuration of the adapter. 2389* 2390* hw - Struct containing variables accessed by shared code 2391* Assumes that the controller has previously been reset and is in a 2392* post-reset uninitialized state. Initializes multicast table, 2393* and Calls routines to setup link 2394* Leaves the transmit and receive units disabled and uninitialized. 2395********************************************************************/ 2396static s32 atl2_init_hw(struct atl2_hw *hw) 2397{ 2398 u32 ret_val = 0; 2399 2400 atl2_init_pcie(hw); 2401 2402 /* Zero out the Multicast HASH table */ 2403 /* clear the old settings from the multicast hash table */ 2404 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 2405 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 2406 2407 atl2_init_flash_opcode(hw); 2408 2409 ret_val = atl2_phy_init(hw); 2410 2411 return ret_val; 2412} 2413 2414/* 2415 * Detects the current speed and duplex settings of the hardware. 2416 * 2417 * hw - Struct containing variables accessed by shared code 2418 * speed - Speed of the connection 2419 * duplex - Duplex setting of the connection 2420 */ 2421static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, 2422 u16 *duplex) 2423{ 2424 s32 ret_val; 2425 u16 phy_data; 2426 2427 /* Read PHY Specific Status Register (17) */ 2428 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); 2429 if (ret_val) 2430 return ret_val; 2431 2432 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) 2433 return ATLX_ERR_PHY_RES; 2434 2435 switch (phy_data & MII_ATLX_PSSR_SPEED) { 2436 case MII_ATLX_PSSR_100MBS: 2437 *speed = SPEED_100; 2438 break; 2439 case MII_ATLX_PSSR_10MBS: 2440 *speed = SPEED_10; 2441 break; 2442 default: 2443 return ATLX_ERR_PHY_SPEED; 2444 } 2445 2446 if (phy_data & MII_ATLX_PSSR_DPLX) 2447 *duplex = FULL_DUPLEX; 2448 else 2449 *duplex = HALF_DUPLEX; 2450 2451 return 0; 2452} 2453 2454/* 2455 * Reads the value from a PHY register 2456 * hw - Struct containing variables accessed by shared code 2457 * reg_addr - address of the PHY register to read 2458 */ 2459static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) 2460{ 2461 u32 val; 2462 int i; 2463 2464 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 2465 MDIO_START | 2466 MDIO_SUP_PREAMBLE | 2467 MDIO_RW | 2468 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2469 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2470 2471 wmb(); 2472 2473 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2474 udelay(2); 2475 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2476 if (!(val & (MDIO_START | MDIO_BUSY))) 2477 break; 2478 wmb(); 2479 } 2480 if (!(val & (MDIO_START | MDIO_BUSY))) { 2481 *phy_data = (u16)val; 2482 return 0; 2483 } 2484 2485 return ATLX_ERR_PHY; 2486} 2487 2488/* 2489 * Writes a value to a PHY register 2490 * hw - Struct containing variables accessed by shared code 2491 * reg_addr - address of the PHY register to write 2492 * data - data to write to the PHY 2493 */ 2494static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) 2495{ 2496 int i; 2497 u32 val; 2498 2499 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 2500 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 2501 MDIO_SUP_PREAMBLE | 2502 MDIO_START | 2503 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2504 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2505 2506 wmb(); 2507 2508 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2509 udelay(2); 2510 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2511 if (!(val & (MDIO_START | MDIO_BUSY))) 2512 break; 2513 2514 wmb(); 2515 } 2516 2517 if (!(val & (MDIO_START | MDIO_BUSY))) 2518 return 0; 2519 2520 return ATLX_ERR_PHY; 2521} 2522 2523/* 2524 * Configures PHY autoneg and flow control advertisement settings 2525 * 2526 * hw - Struct containing variables accessed by shared code 2527 */ 2528static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) 2529{ 2530 s16 mii_autoneg_adv_reg; 2531 2532 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2533 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 2534 2535 /* Need to parse autoneg_advertised and set up 2536 * the appropriate PHY registers. First we will parse for 2537 * autoneg_advertised software override. Since we can advertise 2538 * a plethora of combinations, we need to check each bit 2539 * individually. 2540 */ 2541 2542 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 2543 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2544 * the 1000Base-T Control Register (Address 9). */ 2545 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 2546 2547 /* Need to parse MediaType and setup the 2548 * appropriate PHY registers. */ 2549 switch (hw->MediaType) { 2550 case MEDIA_TYPE_AUTO_SENSOR: 2551 mii_autoneg_adv_reg |= 2552 (MII_AR_10T_HD_CAPS | 2553 MII_AR_10T_FD_CAPS | 2554 MII_AR_100TX_HD_CAPS| 2555 MII_AR_100TX_FD_CAPS); 2556 hw->autoneg_advertised = 2557 ADVERTISE_10_HALF | 2558 ADVERTISE_10_FULL | 2559 ADVERTISE_100_HALF| 2560 ADVERTISE_100_FULL; 2561 break; 2562 case MEDIA_TYPE_100M_FULL: 2563 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 2564 hw->autoneg_advertised = ADVERTISE_100_FULL; 2565 break; 2566 case MEDIA_TYPE_100M_HALF: 2567 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 2568 hw->autoneg_advertised = ADVERTISE_100_HALF; 2569 break; 2570 case MEDIA_TYPE_10M_FULL: 2571 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 2572 hw->autoneg_advertised = ADVERTISE_10_FULL; 2573 break; 2574 default: 2575 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 2576 hw->autoneg_advertised = ADVERTISE_10_HALF; 2577 break; 2578 } 2579 2580 /* flow control fixed to enable all */ 2581 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 2582 2583 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 2584 2585 return atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 2586} 2587 2588/* 2589 * Resets the PHY and make all config validate 2590 * 2591 * hw - Struct containing variables accessed by shared code 2592 * 2593 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) 2594 */ 2595static s32 atl2_phy_commit(struct atl2_hw *hw) 2596{ 2597 s32 ret_val; 2598 u16 phy_data; 2599 2600 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2601 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); 2602 if (ret_val) { 2603 u32 val; 2604 int i; 2605 /* pcie serdes link may be down ! */ 2606 for (i = 0; i < 25; i++) { 2607 msleep(1); 2608 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2609 if (!(val & (MDIO_START | MDIO_BUSY))) 2610 break; 2611 } 2612 2613 if (0 != (val & (MDIO_START | MDIO_BUSY))) { 2614 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n"); 2615 return ret_val; 2616 } 2617 } 2618 return 0; 2619} 2620 2621static s32 atl2_phy_init(struct atl2_hw *hw) 2622{ 2623 s32 ret_val; 2624 u16 phy_val; 2625 2626 if (hw->phy_configured) 2627 return 0; 2628 2629 /* Enable PHY */ 2630 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); 2631 ATL2_WRITE_FLUSH(hw); 2632 msleep(1); 2633 2634 /* check if the PHY is in powersaving mode */ 2635 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2636 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2637 2638 /* 024E / 124E 0r 0274 / 1274 ? */ 2639 if (phy_val & 0x1000) { 2640 phy_val &= ~0x1000; 2641 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); 2642 } 2643 2644 msleep(1); 2645 2646 /*Enable PHY LinkChange Interrupt */ 2647 ret_val = atl2_write_phy_reg(hw, 18, 0xC00); 2648 if (ret_val) 2649 return ret_val; 2650 2651 /* setup AutoNeg parameters */ 2652 ret_val = atl2_phy_setup_autoneg_adv(hw); 2653 if (ret_val) 2654 return ret_val; 2655 2656 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */ 2657 ret_val = atl2_phy_commit(hw); 2658 if (ret_val) 2659 return ret_val; 2660 2661 hw->phy_configured = true; 2662 2663 return ret_val; 2664} 2665 2666static void atl2_set_mac_addr(struct atl2_hw *hw) 2667{ 2668 u32 value; 2669 /* 00-0B-6A-F6-00-DC 2670 * 0: 6AF600DC 1: 000B 2671 * low dword */ 2672 value = (((u32)hw->mac_addr[2]) << 24) | 2673 (((u32)hw->mac_addr[3]) << 16) | 2674 (((u32)hw->mac_addr[4]) << 8) | 2675 (((u32)hw->mac_addr[5])); 2676 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); 2677 /* hight dword */ 2678 value = (((u32)hw->mac_addr[0]) << 8) | 2679 (((u32)hw->mac_addr[1])); 2680 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); 2681} 2682 2683/* 2684 * check_eeprom_exist 2685 * return 0 if eeprom exist 2686 */ 2687static int atl2_check_eeprom_exist(struct atl2_hw *hw) 2688{ 2689 u32 value; 2690 2691 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2692 if (value & SPI_FLASH_CTRL_EN_VPD) { 2693 value &= ~SPI_FLASH_CTRL_EN_VPD; 2694 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2695 } 2696 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); 2697 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 2698} 2699 2700/* FIXME: This doesn't look right. -- CHS */ 2701static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) 2702{ 2703 return true; 2704} 2705 2706static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) 2707{ 2708 int i; 2709 u32 Control; 2710 2711 if (Offset & 0x3) 2712 return false; /* address do not align */ 2713 2714 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); 2715 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 2716 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); 2717 2718 for (i = 0; i < 10; i++) { 2719 msleep(2); 2720 Control = ATL2_READ_REG(hw, REG_VPD_CAP); 2721 if (Control & VPD_CAP_VPD_FLAG) 2722 break; 2723 } 2724 2725 if (Control & VPD_CAP_VPD_FLAG) { 2726 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); 2727 return true; 2728 } 2729 return false; /* timeout */ 2730} 2731 2732static void atl2_force_ps(struct atl2_hw *hw) 2733{ 2734 u16 phy_val; 2735 2736 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2737 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2738 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); 2739 2740 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); 2741 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); 2742 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); 2743 atl2_write_phy_reg(hw, MII_DBG_DATA, 0); 2744} 2745 2746/* This is the only thing that needs to be changed to adjust the 2747 * maximum number of ports that the driver can manage. 2748 */ 2749#define ATL2_MAX_NIC 4 2750 2751#define OPTION_UNSET -1 2752#define OPTION_DISABLED 0 2753#define OPTION_ENABLED 1 2754 2755/* All parameters are treated the same, as an integer array of values. 2756 * This macro just reduces the need to repeat the same declaration code 2757 * over and over (plus this helps to avoid typo bugs). 2758 */ 2759#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET} 2760#ifndef module_param_array 2761/* Module Parameters are always initialized to -1, so that the driver 2762 * can tell the difference between no user specified value or the 2763 * user asking for the default value. 2764 * The true default values are loaded in when atl2_check_options is called. 2765 * 2766 * This is a GCC extension to ANSI C. 2767 * See the item "Labeled Elements in Initializers" in the section 2768 * "Extensions to the C Language Family" of the GCC documentation. 2769 */ 2770 2771#define ATL2_PARAM(X, desc) \ 2772 static const int X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \ 2773 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \ 2774 MODULE_PARM_DESC(X, desc); 2775#else 2776#define ATL2_PARAM(X, desc) \ 2777 static int X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \ 2778 static unsigned int num_##X; \ 2779 module_param_array_named(X, X, int, &num_##X, 0); \ 2780 MODULE_PARM_DESC(X, desc); 2781#endif 2782 2783/* 2784 * Transmit Memory Size 2785 * Valid Range: 64-2048 2786 * Default Value: 128 2787 */ 2788#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */ 2789#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */ 2790#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */ 2791ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory"); 2792 2793/* 2794 * Receive Memory Block Count 2795 * Valid Range: 16-512 2796 * Default Value: 128 2797 */ 2798#define ATL2_MIN_RXD_COUNT 16 2799#define ATL2_MAX_RXD_COUNT 512 2800#define ATL2_DEFAULT_RXD_COUNT 64 2801ATL2_PARAM(RxMemBlock, "Number of receive memory block"); 2802 2803/* 2804 * User Specified MediaType Override 2805 * 2806 * Valid Range: 0-5 2807 * - 0 - auto-negotiate at all supported speeds 2808 * - 1 - only link at 1000Mbps Full Duplex 2809 * - 2 - only link at 100Mbps Full Duplex 2810 * - 3 - only link at 100Mbps Half Duplex 2811 * - 4 - only link at 10Mbps Full Duplex 2812 * - 5 - only link at 10Mbps Half Duplex 2813 * Default Value: 0 2814 */ 2815ATL2_PARAM(MediaType, "MediaType Select"); 2816 2817/* 2818 * Interrupt Moderate Timer in units of 2048 ns (~2 us) 2819 * Valid Range: 10-65535 2820 * Default Value: 45000(90ms) 2821 */ 2822#define INT_MOD_DEFAULT_CNT 100 /* 200us */ 2823#define INT_MOD_MAX_CNT 65000 2824#define INT_MOD_MIN_CNT 50 2825ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer"); 2826 2827/* 2828 * FlashVendor 2829 * Valid Range: 0-2 2830 * 0 - Atmel 2831 * 1 - SST 2832 * 2 - ST 2833 */ 2834ATL2_PARAM(FlashVendor, "SPI Flash Vendor"); 2835 2836#define AUTONEG_ADV_DEFAULT 0x2F 2837#define AUTONEG_ADV_MASK 0x2F 2838#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL 2839 2840#define FLASH_VENDOR_DEFAULT 0 2841#define FLASH_VENDOR_MIN 0 2842#define FLASH_VENDOR_MAX 2 2843 2844struct atl2_option { 2845 enum { enable_option, range_option, list_option } type; 2846 char *name; 2847 char *err; 2848 int def; 2849 union { 2850 struct { /* range_option info */ 2851 int min; 2852 int max; 2853 } r; 2854 struct { /* list_option info */ 2855 int nr; 2856 struct atl2_opt_list { int i; char *str; } *p; 2857 } l; 2858 } arg; 2859}; 2860 2861static int atl2_validate_option(int *value, struct atl2_option *opt) 2862{ 2863 int i; 2864 struct atl2_opt_list *ent; 2865 2866 if (*value == OPTION_UNSET) { 2867 *value = opt->def; 2868 return 0; 2869 } 2870 2871 switch (opt->type) { 2872 case enable_option: 2873 switch (*value) { 2874 case OPTION_ENABLED: 2875 printk(KERN_INFO "%s Enabled\n", opt->name); 2876 return 0; 2877 case OPTION_DISABLED: 2878 printk(KERN_INFO "%s Disabled\n", opt->name); 2879 return 0; 2880 } 2881 break; 2882 case range_option: 2883 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 2884 printk(KERN_INFO "%s set to %i\n", opt->name, *value); 2885 return 0; 2886 } 2887 break; 2888 case list_option: 2889 for (i = 0; i < opt->arg.l.nr; i++) { 2890 ent = &opt->arg.l.p[i]; 2891 if (*value == ent->i) { 2892 if (ent->str[0] != '\0') 2893 printk(KERN_INFO "%s\n", ent->str); 2894 return 0; 2895 } 2896 } 2897 break; 2898 default: 2899 BUG(); 2900 } 2901 2902 printk(KERN_INFO "Invalid %s specified (%i) %s\n", 2903 opt->name, *value, opt->err); 2904 *value = opt->def; 2905 return -1; 2906} 2907 2908/** 2909 * atl2_check_options - Range Checking for Command Line Parameters 2910 * @adapter: board private structure 2911 * 2912 * This routine checks all command line parameters for valid user 2913 * input. If an invalid value is given, or if no user specified 2914 * value exists, a default value is used. The final value is stored 2915 * in a variable in the adapter structure. 2916 */ 2917static void atl2_check_options(struct atl2_adapter *adapter) 2918{ 2919 int val; 2920 struct atl2_option opt; 2921 int bd = adapter->bd_number; 2922 if (bd >= ATL2_MAX_NIC) { 2923 printk(KERN_NOTICE "Warning: no configuration for board #%i\n", 2924 bd); 2925 printk(KERN_NOTICE "Using defaults for all values\n"); 2926#ifndef module_param_array 2927 bd = ATL2_MAX_NIC; 2928#endif 2929 } 2930 2931 /* Bytes of Transmit Memory */ 2932 opt.type = range_option; 2933 opt.name = "Bytes of Transmit Memory"; 2934 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE); 2935 opt.def = ATL2_DEFAULT_TX_MEMSIZE; 2936 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE; 2937 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE; 2938#ifdef module_param_array 2939 if (num_TxMemSize > bd) { 2940#endif 2941 val = TxMemSize[bd]; 2942 atl2_validate_option(&val, &opt); 2943 adapter->txd_ring_size = ((u32) val) * 1024; 2944#ifdef module_param_array 2945 } else 2946 adapter->txd_ring_size = ((u32)opt.def) * 1024; 2947#endif 2948 /* txs ring size: */ 2949 adapter->txs_ring_size = adapter->txd_ring_size / 128; 2950 if (adapter->txs_ring_size > 160) 2951 adapter->txs_ring_size = 160; 2952 2953 /* Receive Memory Block Count */ 2954 opt.type = range_option; 2955 opt.name = "Number of receive memory block"; 2956 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT); 2957 opt.def = ATL2_DEFAULT_RXD_COUNT; 2958 opt.arg.r.min = ATL2_MIN_RXD_COUNT; 2959 opt.arg.r.max = ATL2_MAX_RXD_COUNT; 2960#ifdef module_param_array 2961 if (num_RxMemBlock > bd) { 2962#endif 2963 val = RxMemBlock[bd]; 2964 atl2_validate_option(&val, &opt); 2965 adapter->rxd_ring_size = (u32)val; 2966 /* FIXME */ 2967 /* ((u16)val)&~1; */ /* even number */ 2968#ifdef module_param_array 2969 } else 2970 adapter->rxd_ring_size = (u32)opt.def; 2971#endif 2972 /* init RXD Flow control value */ 2973 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7; 2974 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) > 2975 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) : 2976 (adapter->rxd_ring_size / 12); 2977 2978 /* Interrupt Moderate Timer */ 2979 opt.type = range_option; 2980 opt.name = "Interrupt Moderate Timer"; 2981 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT); 2982 opt.def = INT_MOD_DEFAULT_CNT; 2983 opt.arg.r.min = INT_MOD_MIN_CNT; 2984 opt.arg.r.max = INT_MOD_MAX_CNT; 2985#ifdef module_param_array 2986 if (num_IntModTimer > bd) { 2987#endif 2988 val = IntModTimer[bd]; 2989 atl2_validate_option(&val, &opt); 2990 adapter->imt = (u16) val; 2991#ifdef module_param_array 2992 } else 2993 adapter->imt = (u16)(opt.def); 2994#endif 2995 /* Flash Vendor */ 2996 opt.type = range_option; 2997 opt.name = "SPI Flash Vendor"; 2998 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT); 2999 opt.def = FLASH_VENDOR_DEFAULT; 3000 opt.arg.r.min = FLASH_VENDOR_MIN; 3001 opt.arg.r.max = FLASH_VENDOR_MAX; 3002#ifdef module_param_array 3003 if (num_FlashVendor > bd) { 3004#endif 3005 val = FlashVendor[bd]; 3006 atl2_validate_option(&val, &opt); 3007 adapter->hw.flash_vendor = (u8) val; 3008#ifdef module_param_array 3009 } else 3010 adapter->hw.flash_vendor = (u8)(opt.def); 3011#endif 3012 /* MediaType */ 3013 opt.type = range_option; 3014 opt.name = "Speed/Duplex Selection"; 3015 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR); 3016 opt.def = MEDIA_TYPE_AUTO_SENSOR; 3017 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR; 3018 opt.arg.r.max = MEDIA_TYPE_10M_HALF; 3019#ifdef module_param_array 3020 if (num_MediaType > bd) { 3021#endif 3022 val = MediaType[bd]; 3023 atl2_validate_option(&val, &opt); 3024 adapter->hw.MediaType = (u16) val; 3025#ifdef module_param_array 3026 } else 3027 adapter->hw.MediaType = (u16)(opt.def); 3028#endif 3029} 3030