1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Atlantic Network Driver 3 * 4 * Copyright (C) 2014-2019 aQuantia Corporation 5 * Copyright (C) 2019-2020 Marvell International Ltd. 6 */ 7 8/* File hw_atl_llh_internal.h: Preprocessor definitions 9 * for Atlantic registers. 10 */ 11 12#ifndef HW_ATL_LLH_INTERNAL_H 13#define HW_ATL_LLH_INTERNAL_H 14 15/* COM Temperature Sense Reset Bitfield Definitions */ 16#define HW_ATL_TS_RESET_ADR 0x00003100 17#define HW_ATL_TS_RESET_MSK 0x00000004 18#define HW_ATL_TS_RESET_SHIFT 2 19#define HW_ATL_TS_RESET_WIDTH 1 20 21/* COM Temperature Sense Power Down Bitfield Definitions */ 22#define HW_ATL_TS_POWER_DOWN_ADR 0x00003100 23#define HW_ATL_TS_POWER_DOWN_MSK 0x00000001 24#define HW_ATL_TS_POWER_DOWN_SHIFT 0 25#define HW_ATL_TS_POWER_DOWN_WIDTH 1 26 27/* COM Temperature Sense Ready Bitfield Definitions */ 28#define HW_ATL_TS_READY_ADR 0x00003120 29#define HW_ATL_TS_READY_MSK 0x80000000 30#define HW_ATL_TS_READY_SHIFT 31 31#define HW_ATL_TS_READY_WIDTH 1 32 33/* COM Temperature Sense Ready Latch High Bitfield Definitions */ 34#define HW_ATL_TS_READY_LATCH_HIGH_ADR 0x00003120 35#define HW_ATL_TS_READY_LATCH_HIGH_MSK 0x40000000 36#define HW_ATL_TS_READY_LATCH_HIGH_SHIFT 30 37#define HW_ATL_TS_READY_LATCH_HIGH_WIDTH 1 38 39/* COM Temperature Sense Data Out [B:0] Bitfield Definitions */ 40#define HW_ATL_TS_DATA_OUT_ADR 0x00003120 41#define HW_ATL_TS_DATA_OUT_MSK 0x00000FFF 42#define HW_ATL_TS_DATA_OUT_SHIFT 0 43#define HW_ATL_TS_DATA_OUT_WIDTH 12 44 45/* global microprocessor semaphore definitions 46 * base address: 0x000003a0 47 * parameter: semaphore {s} | stride size 0x4 | range [0, 15] 48 */ 49#define HW_ATL_GLB_CPU_SEM_ADR(semaphore) (0x000003a0u + (semaphore) * 0x4) 50/* register address for bitfield rx dma good octet counter lsw [1f:0] */ 51#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808 52/* register address for bitfield rx dma good packet counter lsw [1f:0] */ 53#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800 54/* register address for bitfield tx dma good octet counter lsw [1f:0] */ 55#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808 56/* register address for bitfield tx dma good packet counter lsw [1f:0] */ 57#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800 58 59/* register address for bitfield rx dma good octet counter msw [3f:20] */ 60#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c 61/* register address for bitfield rx dma good packet counter msw [3f:20] */ 62#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804 63/* register address for bitfield tx dma good octet counter msw [3f:20] */ 64#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c 65/* register address for bitfield tx dma good packet counter msw [3f:20] */ 66#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804 67 68/* preprocessor definitions for msm rx errors counter register */ 69#define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u 70 71/* preprocessor definitions for msm rx unicast frames counter register */ 72#define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR 0x000000e0u 73 74/* preprocessor definitions for msm rx multicast frames counter register */ 75#define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR 0x000000e8u 76 77/* preprocessor definitions for msm rx broadcast frames counter register */ 78#define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR 0x000000f0u 79 80/* preprocessor definitions for msm rx broadcast octets counter register 1 */ 81#define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR 0x000001b0u 82 83/* preprocessor definitions for msm rx broadcast octets counter register 2 */ 84#define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR 0x000001b4u 85 86/* preprocessor definitions for msm rx unicast octets counter register 0 */ 87#define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u 88 89/* preprocessor definitions for msm tx unicast frames counter register */ 90#define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u 91 92/* preprocessor definitions for msm tx multicast frames counter register */ 93#define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR 0x00000110u 94 95/* preprocessor definitions for global mif identification */ 96#define HW_ATL_GLB_MIF_ID_ADR 0x0000001cu 97 98/* register address for bitfield iamr_lsw[1f:0] */ 99#define HW_ATL_ITR_IAMRLSW_ADR 0x00002090 100/* register address for bitfield rx dma drop packet counter [1f:0] */ 101#define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR 0x00006818 102 103/* register address for bitfield imcr_lsw[1f:0] */ 104#define HW_ATL_ITR_IMCRLSW_ADR 0x00002070 105/* register address for bitfield imsr_lsw[1f:0] */ 106#define HW_ATL_ITR_IMSRLSW_ADR 0x00002060 107/* register address for bitfield itr_reg_res_dsbl */ 108#define HW_ATL_ITR_REG_RES_DSBL_ADR 0x00002300 109/* bitmask for bitfield itr_reg_res_dsbl */ 110#define HW_ATL_ITR_REG_RES_DSBL_MSK 0x20000000 111/* lower bit position of bitfield itr_reg_res_dsbl */ 112#define HW_ATL_ITR_REG_RES_DSBL_SHIFT 29 113/* register address for bitfield iscr_lsw[1f:0] */ 114#define HW_ATL_ITR_ISCRLSW_ADR 0x00002050 115/* register address for bitfield isr_lsw[1f:0] */ 116#define HW_ATL_ITR_ISRLSW_ADR 0x00002000 117/* register address for bitfield itr_reset */ 118#define HW_ATL_ITR_RES_ADR 0x00002300 119/* bitmask for bitfield itr_reset */ 120#define HW_ATL_ITR_RES_MSK 0x80000000 121/* lower bit position of bitfield itr_reset */ 122#define HW_ATL_ITR_RES_SHIFT 31 123 124/* register address for bitfield rsc_en */ 125#define HW_ATL_ITR_RSC_EN_ADR 0x00002200 126 127/* register address for bitfield rsc_delay */ 128#define HW_ATL_ITR_RSC_DELAY_ADR 0x00002204 129/* bitmask for bitfield rsc_delay */ 130#define HW_ATL_ITR_RSC_DELAY_MSK 0x0000000f 131/* width of bitfield rsc_delay */ 132#define HW_ATL_ITR_RSC_DELAY_WIDTH 4 133/* lower bit position of bitfield rsc_delay */ 134#define HW_ATL_ITR_RSC_DELAY_SHIFT 0 135 136/* register address for bitfield dca{d}_cpuid[7:0] */ 137#define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4) 138/* bitmask for bitfield dca{d}_cpuid[7:0] */ 139#define HW_ATL_RDM_DCADCPUID_MSK 0x000000ff 140/* lower bit position of bitfield dca{d}_cpuid[7:0] */ 141#define HW_ATL_RDM_DCADCPUID_SHIFT 0 142/* register address for bitfield dca_en */ 143#define HW_ATL_RDM_DCA_EN_ADR 0x00006180 144 145/* rx dca_en bitfield definitions 146 * preprocessor definitions for the bitfield "dca_en". 147 * port="pif_rdm_dca_en_i" 148 */ 149 150/* register address for bitfield dca_en */ 151#define HW_ATL_RDM_DCA_EN_ADR 0x00006180 152/* bitmask for bitfield dca_en */ 153#define HW_ATL_RDM_DCA_EN_MSK 0x80000000 154/* inverted bitmask for bitfield dca_en */ 155#define HW_ATL_RDM_DCA_EN_MSKN 0x7fffffff 156/* lower bit position of bitfield dca_en */ 157#define HW_ATL_RDM_DCA_EN_SHIFT 31 158/* width of bitfield dca_en */ 159#define HW_ATL_RDM_DCA_EN_WIDTH 1 160/* default value of bitfield dca_en */ 161#define HW_ATL_RDM_DCA_EN_DEFAULT 0x1 162 163/* rx dca_mode[3:0] bitfield definitions 164 * preprocessor definitions for the bitfield "dca_mode[3:0]". 165 * port="pif_rdm_dca_mode_i[3:0]" 166 */ 167 168/* register address for bitfield dca_mode[3:0] */ 169#define HW_ATL_RDM_DCA_MODE_ADR 0x00006180 170/* bitmask for bitfield dca_mode[3:0] */ 171#define HW_ATL_RDM_DCA_MODE_MSK 0x0000000f 172/* inverted bitmask for bitfield dca_mode[3:0] */ 173#define HW_ATL_RDM_DCA_MODE_MSKN 0xfffffff0 174/* lower bit position of bitfield dca_mode[3:0] */ 175#define HW_ATL_RDM_DCA_MODE_SHIFT 0 176/* width of bitfield dca_mode[3:0] */ 177#define HW_ATL_RDM_DCA_MODE_WIDTH 4 178/* default value of bitfield dca_mode[3:0] */ 179#define HW_ATL_RDM_DCA_MODE_DEFAULT 0x0 180 181/* rx desc{d}_data_size[4:0] bitfield definitions 182 * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]". 183 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 184 * port="pif_rdm_desc0_data_size_i[4:0]" 185 */ 186 187/* register address for bitfield desc{d}_data_size[4:0] */ 188#define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) \ 189 (0x00005b18 + (descriptor) * 0x20) 190/* bitmask for bitfield desc{d}_data_size[4:0] */ 191#define HW_ATL_RDM_DESCDDATA_SIZE_MSK 0x0000001f 192/* inverted bitmask for bitfield desc{d}_data_size[4:0] */ 193#define HW_ATL_RDM_DESCDDATA_SIZE_MSKN 0xffffffe0 194/* lower bit position of bitfield desc{d}_data_size[4:0] */ 195#define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT 0 196/* width of bitfield desc{d}_data_size[4:0] */ 197#define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH 5 198/* default value of bitfield desc{d}_data_size[4:0] */ 199#define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT 0x0 200 201/* rx dca{d}_desc_en bitfield definitions 202 * preprocessor definitions for the bitfield "dca{d}_desc_en". 203 * parameter: dca {d} | stride size 0x4 | range [0, 31] 204 * port="pif_rdm_dca_desc_en_i[0]" 205 */ 206 207/* register address for bitfield dca{d}_desc_en */ 208#define HW_ATL_RDM_DCADDESC_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 209/* bitmask for bitfield dca{d}_desc_en */ 210#define HW_ATL_RDM_DCADDESC_EN_MSK 0x80000000 211/* inverted bitmask for bitfield dca{d}_desc_en */ 212#define HW_ATL_RDM_DCADDESC_EN_MSKN 0x7fffffff 213/* lower bit position of bitfield dca{d}_desc_en */ 214#define HW_ATL_RDM_DCADDESC_EN_SHIFT 31 215/* width of bitfield dca{d}_desc_en */ 216#define HW_ATL_RDM_DCADDESC_EN_WIDTH 1 217/* default value of bitfield dca{d}_desc_en */ 218#define HW_ATL_RDM_DCADDESC_EN_DEFAULT 0x0 219 220/* rx desc{d}_en bitfield definitions 221 * preprocessor definitions for the bitfield "desc{d}_en". 222 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 223 * port="pif_rdm_desc_en_i[0]" 224 */ 225 226/* register address for bitfield desc{d}_en */ 227#define HW_ATL_RDM_DESCDEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 228/* bitmask for bitfield desc{d}_en */ 229#define HW_ATL_RDM_DESCDEN_MSK 0x80000000 230/* inverted bitmask for bitfield desc{d}_en */ 231#define HW_ATL_RDM_DESCDEN_MSKN 0x7fffffff 232/* lower bit position of bitfield desc{d}_en */ 233#define HW_ATL_RDM_DESCDEN_SHIFT 31 234/* width of bitfield desc{d}_en */ 235#define HW_ATL_RDM_DESCDEN_WIDTH 1 236/* default value of bitfield desc{d}_en */ 237#define HW_ATL_RDM_DESCDEN_DEFAULT 0x0 238 239/* rx desc{d}_hdr_size[4:0] bitfield definitions 240 * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]". 241 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 242 * port="pif_rdm_desc0_hdr_size_i[4:0]" 243 */ 244 245/* register address for bitfield desc{d}_hdr_size[4:0] */ 246#define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) \ 247 (0x00005b18 + (descriptor) * 0x20) 248/* bitmask for bitfield desc{d}_hdr_size[4:0] */ 249#define HW_ATL_RDM_DESCDHDR_SIZE_MSK 0x00001f00 250/* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */ 251#define HW_ATL_RDM_DESCDHDR_SIZE_MSKN 0xffffe0ff 252/* lower bit position of bitfield desc{d}_hdr_size[4:0] */ 253#define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT 8 254/* width of bitfield desc{d}_hdr_size[4:0] */ 255#define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH 5 256/* default value of bitfield desc{d}_hdr_size[4:0] */ 257#define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT 0x0 258 259/* rx desc{d}_hdr_split bitfield definitions 260 * preprocessor definitions for the bitfield "desc{d}_hdr_split". 261 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 262 * port="pif_rdm_desc_hdr_split_i[0]" 263 */ 264 265/* register address for bitfield desc{d}_hdr_split */ 266#define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) \ 267 (0x00005b08 + (descriptor) * 0x20) 268/* bitmask for bitfield desc{d}_hdr_split */ 269#define HW_ATL_RDM_DESCDHDR_SPLIT_MSK 0x10000000 270/* inverted bitmask for bitfield desc{d}_hdr_split */ 271#define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN 0xefffffff 272/* lower bit position of bitfield desc{d}_hdr_split */ 273#define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT 28 274/* width of bitfield desc{d}_hdr_split */ 275#define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH 1 276/* default value of bitfield desc{d}_hdr_split */ 277#define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT 0x0 278 279/* rx desc{d}_hd[c:0] bitfield definitions 280 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 281 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 282 * port="rdm_pif_desc0_hd_o[12:0]" 283 */ 284 285/* register address for bitfield desc{d}_hd[c:0] */ 286#define HW_ATL_RDM_DESCDHD_ADR(descriptor) (0x00005b0c + (descriptor) * 0x20) 287/* bitmask for bitfield desc{d}_hd[c:0] */ 288#define HW_ATL_RDM_DESCDHD_MSK 0x00001fff 289/* inverted bitmask for bitfield desc{d}_hd[c:0] */ 290#define HW_ATL_RDM_DESCDHD_MSKN 0xffffe000 291/* lower bit position of bitfield desc{d}_hd[c:0] */ 292#define HW_ATL_RDM_DESCDHD_SHIFT 0 293/* width of bitfield desc{d}_hd[c:0] */ 294#define HW_ATL_RDM_DESCDHD_WIDTH 13 295 296/* rx desc{d}_len[9:0] bitfield definitions 297 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 298 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 299 * port="pif_rdm_desc0_len_i[9:0]" 300 */ 301 302/* register address for bitfield desc{d}_len[9:0] */ 303#define HW_ATL_RDM_DESCDLEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 304/* bitmask for bitfield desc{d}_len[9:0] */ 305#define HW_ATL_RDM_DESCDLEN_MSK 0x00001ff8 306/* inverted bitmask for bitfield desc{d}_len[9:0] */ 307#define HW_ATL_RDM_DESCDLEN_MSKN 0xffffe007 308/* lower bit position of bitfield desc{d}_len[9:0] */ 309#define HW_ATL_RDM_DESCDLEN_SHIFT 3 310/* width of bitfield desc{d}_len[9:0] */ 311#define HW_ATL_RDM_DESCDLEN_WIDTH 10 312/* default value of bitfield desc{d}_len[9:0] */ 313#define HW_ATL_RDM_DESCDLEN_DEFAULT 0x0 314 315/* rx desc{d}_reset bitfield definitions 316 * preprocessor definitions for the bitfield "desc{d}_reset". 317 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 318 * port="pif_rdm_q_pf_res_i[0]" 319 */ 320 321/* register address for bitfield desc{d}_reset */ 322#define HW_ATL_RDM_DESCDRESET_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 323/* bitmask for bitfield desc{d}_reset */ 324#define HW_ATL_RDM_DESCDRESET_MSK 0x02000000 325/* inverted bitmask for bitfield desc{d}_reset */ 326#define HW_ATL_RDM_DESCDRESET_MSKN 0xfdffffff 327/* lower bit position of bitfield desc{d}_reset */ 328#define HW_ATL_RDM_DESCDRESET_SHIFT 25 329/* width of bitfield desc{d}_reset */ 330#define HW_ATL_RDM_DESCDRESET_WIDTH 1 331/* default value of bitfield desc{d}_reset */ 332#define HW_ATL_RDM_DESCDRESET_DEFAULT 0x0 333 334/* rdm_desc_init_i bitfield definitions 335 * preprocessor definitions for the bitfield rdm_desc_init_i. 336 * port="pif_rdm_desc_init_i" 337 */ 338 339/* register address for bitfield rdm_desc_init_i */ 340#define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR 0x00005a00 341/* bitmask for bitfield rdm_desc_init_i */ 342#define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK 0xffffffff 343/* inverted bitmask for bitfield rdm_desc_init_i */ 344#define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSKN 0x00000000 345/* lower bit position of bitfield rdm_desc_init_i */ 346#define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT 0 347/* width of bitfield rdm_desc_init_i */ 348#define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_WIDTH 32 349/* default value of bitfield rdm_desc_init_i */ 350#define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_DEFAULT 0x0 351 352/* rdm_desc_init_done_i bitfield definitions 353 * preprocessor definitions for the bitfield rdm_desc_init_done_i. 354 * port="pif_rdm_desc_init_done_i" 355 */ 356 357/* register address for bitfield rdm_desc_init_done_i */ 358#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR 0x00005a10 359/* bitmask for bitfield rdm_desc_init_done_i */ 360#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK 0x00000001U 361/* inverted bitmask for bitfield rdm_desc_init_done_i */ 362#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSKN 0xfffffffe 363/* lower bit position of bitfield rdm_desc_init_done_i */ 364#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT 0U 365/* width of bitfield rdm_desc_init_done_i */ 366#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_WIDTH 1 367/* default value of bitfield rdm_desc_init_done_i */ 368#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_DEFAULT 0x0 369 370 371/* rx int_desc_wrb_en bitfield definitions 372 * preprocessor definitions for the bitfield "int_desc_wrb_en". 373 * port="pif_rdm_int_desc_wrb_en_i" 374 */ 375 376/* register address for bitfield int_desc_wrb_en */ 377#define HW_ATL_RDM_INT_DESC_WRB_EN_ADR 0x00005a30 378/* bitmask for bitfield int_desc_wrb_en */ 379#define HW_ATL_RDM_INT_DESC_WRB_EN_MSK 0x00000004 380/* inverted bitmask for bitfield int_desc_wrb_en */ 381#define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN 0xfffffffb 382/* lower bit position of bitfield int_desc_wrb_en */ 383#define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT 2 384/* width of bitfield int_desc_wrb_en */ 385#define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH 1 386/* default value of bitfield int_desc_wrb_en */ 387#define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT 0x0 388 389/* rx dca{d}_hdr_en bitfield definitions 390 * preprocessor definitions for the bitfield "dca{d}_hdr_en". 391 * parameter: dca {d} | stride size 0x4 | range [0, 31] 392 * port="pif_rdm_dca_hdr_en_i[0]" 393 */ 394 395/* register address for bitfield dca{d}_hdr_en */ 396#define HW_ATL_RDM_DCADHDR_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 397/* bitmask for bitfield dca{d}_hdr_en */ 398#define HW_ATL_RDM_DCADHDR_EN_MSK 0x40000000 399/* inverted bitmask for bitfield dca{d}_hdr_en */ 400#define HW_ATL_RDM_DCADHDR_EN_MSKN 0xbfffffff 401/* lower bit position of bitfield dca{d}_hdr_en */ 402#define HW_ATL_RDM_DCADHDR_EN_SHIFT 30 403/* width of bitfield dca{d}_hdr_en */ 404#define HW_ATL_RDM_DCADHDR_EN_WIDTH 1 405/* default value of bitfield dca{d}_hdr_en */ 406#define HW_ATL_RDM_DCADHDR_EN_DEFAULT 0x0 407 408/* rx dca{d}_pay_en bitfield definitions 409 * preprocessor definitions for the bitfield "dca{d}_pay_en". 410 * parameter: dca {d} | stride size 0x4 | range [0, 31] 411 * port="pif_rdm_dca_pay_en_i[0]" 412 */ 413 414/* register address for bitfield dca{d}_pay_en */ 415#define HW_ATL_RDM_DCADPAY_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 416/* bitmask for bitfield dca{d}_pay_en */ 417#define HW_ATL_RDM_DCADPAY_EN_MSK 0x20000000 418/* inverted bitmask for bitfield dca{d}_pay_en */ 419#define HW_ATL_RDM_DCADPAY_EN_MSKN 0xdfffffff 420/* lower bit position of bitfield dca{d}_pay_en */ 421#define HW_ATL_RDM_DCADPAY_EN_SHIFT 29 422/* width of bitfield dca{d}_pay_en */ 423#define HW_ATL_RDM_DCADPAY_EN_WIDTH 1 424/* default value of bitfield dca{d}_pay_en */ 425#define HW_ATL_RDM_DCADPAY_EN_DEFAULT 0x0 426 427/* RX rdm_int_rim_en Bitfield Definitions 428 * Preprocessor definitions for the bitfield "rdm_int_rim_en". 429 * PORT="pif_rdm_int_rim_en_i" 430 */ 431 432/* Register address for bitfield rdm_int_rim_en */ 433#define HW_ATL_RDM_INT_RIM_EN_ADR 0x00005A30 434/* Bitmask for bitfield rdm_int_rim_en */ 435#define HW_ATL_RDM_INT_RIM_EN_MSK 0x00000008 436/* Inverted bitmask for bitfield rdm_int_rim_en */ 437#define HW_ATL_RDM_INT_RIM_EN_MSKN 0xFFFFFFF7 438/* Lower bit position of bitfield rdm_int_rim_en */ 439#define HW_ATL_RDM_INT_RIM_EN_SHIFT 3 440/* Width of bitfield rdm_int_rim_en */ 441#define HW_ATL_RDM_INT_RIM_EN_WIDTH 1 442/* Default value of bitfield rdm_int_rim_en */ 443#define HW_ATL_RDM_INT_RIM_EN_DEFAULT 0x0 444 445/* general interrupt mapping register definitions 446 * preprocessor definitions for general interrupt mapping register 447 * base address: 0x00002180 448 * parameter: regidx {f} | stride size 0x4 | range [0, 3] 449 */ 450#define HW_ATL_GEN_INTR_MAP_ADR(regidx) (0x00002180u + (regidx) * 0x4) 451 452/* general interrupt status register definitions 453 * preprocessor definitions for general interrupt status register 454 * address: 0x000021A0 455 */ 456 457#define HW_ATL_GEN_INTR_STAT_ADR 0x000021A4U 458 459/* interrupt global control register definitions 460 * preprocessor definitions for interrupt global control register 461 * address: 0x00002300 462 */ 463#define HW_ATL_INTR_GLB_CTL_ADR 0x00002300u 464 465/* interrupt throttle register definitions 466 * preprocessor definitions for interrupt throttle register 467 * base address: 0x00002800 468 * parameter: throttle {t} | stride size 0x4 | range [0, 31] 469 */ 470#define HW_ATL_INTR_THR_ADR(throttle) (0x00002800u + (throttle) * 0x4) 471 472/* rx dma descriptor base address lsw definitions 473 * preprocessor definitions for rx dma descriptor base address lsw 474 * base address: 0x00005b00 475 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 476 */ 477#define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ 478(0x00005b00u + (descriptor) * 0x20) 479 480/* rx dma descriptor base address msw definitions 481 * preprocessor definitions for rx dma descriptor base address msw 482 * base address: 0x00005b04 483 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 484 */ 485#define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ 486(0x00005b04u + (descriptor) * 0x20) 487 488/* rx dma descriptor status register definitions 489 * preprocessor definitions for rx dma descriptor status register 490 * base address: 0x00005b14 491 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 492 */ 493#define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) \ 494 (0x00005b14u + (descriptor) * 0x20) 495 496/* rx dma descriptor tail pointer register definitions 497 * preprocessor definitions for rx dma descriptor tail pointer register 498 * base address: 0x00005b10 499 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 500 */ 501#define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ 502 (0x00005b10u + (descriptor) * 0x20) 503 504/* rx interrupt moderation control register definitions 505 * Preprocessor definitions for RX Interrupt Moderation Control Register 506 * Base Address: 0x00005A40 507 * Parameter: RIM {R} | stride size 0x4 | range [0, 31] 508 */ 509#define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) (0x00005A40u + (rim) * 0x4) 510 511/* rx filter multicast filter mask register definitions 512 * preprocessor definitions for rx filter multicast filter mask register 513 * address: 0x00005270 514 */ 515#define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR 0x00005270u 516 517/* rx filter multicast filter register definitions 518 * preprocessor definitions for rx filter multicast filter register 519 * base address: 0x00005250 520 * parameter: filter {f} | stride size 0x4 | range [0, 7] 521 */ 522#define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) (0x00005250u + (filter) * 0x4) 523 524/* RX Filter RSS Control Register 1 Definitions 525 * Preprocessor definitions for RX Filter RSS Control Register 1 526 * Address: 0x000054C0 527 */ 528#define HW_ATL_RX_FLR_RSS_CONTROL1_ADR 0x000054C0u 529 530/* RX Filter Control Register 2 Definitions 531 * Preprocessor definitions for RX Filter Control Register 2 532 * Address: 0x00005104 533 */ 534#define HW_ATL_RX_FLR_CONTROL2_ADR 0x00005104u 535 536/* tx tx dma debug control [1f:0] bitfield definitions 537 * preprocessor definitions for the bitfield "tx dma debug control [1f:0]". 538 * port="pif_tdm_debug_cntl_i[31:0]" 539 */ 540 541/* register address for bitfield tx dma debug control [1f:0] */ 542#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR 0x00008920 543/* bitmask for bitfield tx dma debug control [1f:0] */ 544#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK 0xffffffff 545/* inverted bitmask for bitfield tx dma debug control [1f:0] */ 546#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN 0x00000000 547/* lower bit position of bitfield tx dma debug control [1f:0] */ 548#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT 0 549/* width of bitfield tx dma debug control [1f:0] */ 550#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH 32 551/* default value of bitfield tx dma debug control [1f:0] */ 552#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT 0x0 553 554/* tx dma descriptor base address lsw definitions 555 * preprocessor definitions for tx dma descriptor base address lsw 556 * base address: 0x00007c00 557 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 558 */ 559#define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ 560 (0x00007c00u + (descriptor) * 0x40) 561 562/* tx dma descriptor tail pointer register definitions 563 * preprocessor definitions for tx dma descriptor tail pointer register 564 * base address: 0x00007c10 565 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 566 */ 567#define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ 568 (0x00007c10u + (descriptor) * 0x40) 569 570/* rx dma_sys_loopback bitfield definitions 571 * preprocessor definitions for the bitfield "dma_sys_loopback". 572 * port="pif_rpb_dma_sys_lbk_i" 573 */ 574 575/* register address for bitfield dma_sys_loopback */ 576#define HW_ATL_RPB_DMA_SYS_LBK_ADR 0x00005000 577/* bitmask for bitfield dma_sys_loopback */ 578#define HW_ATL_RPB_DMA_SYS_LBK_MSK 0x00000040 579/* inverted bitmask for bitfield dma_sys_loopback */ 580#define HW_ATL_RPB_DMA_SYS_LBK_MSKN 0xffffffbf 581/* lower bit position of bitfield dma_sys_loopback */ 582#define HW_ATL_RPB_DMA_SYS_LBK_SHIFT 6 583/* width of bitfield dma_sys_loopback */ 584#define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1 585/* default value of bitfield dma_sys_loopback */ 586#define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0 587 588/* rx dma_net_loopback bitfield definitions 589 * preprocessor definitions for the bitfield "dma_net_loopback". 590 * port="pif_rpb_dma_net_lbk_i" 591 */ 592 593/* register address for bitfield dma_net_loopback */ 594#define HW_ATL_RPB_DMA_NET_LBK_ADR 0x00005000 595/* bitmask for bitfield dma_net_loopback */ 596#define HW_ATL_RPB_DMA_NET_LBK_MSK 0x00000010 597/* inverted bitmask for bitfield dma_net_loopback */ 598#define HW_ATL_RPB_DMA_NET_LBK_MSKN 0xffffffef 599/* lower bit position of bitfield dma_net_loopback */ 600#define HW_ATL_RPB_DMA_NET_LBK_SHIFT 4 601/* width of bitfield dma_net_loopback */ 602#define HW_ATL_RPB_DMA_NET_LBK_WIDTH 1 603/* default value of bitfield dma_net_loopback */ 604#define HW_ATL_RPB_DMA_NET_LBK_DEFAULT 0x0 605 606/* rx rx_tc_mode bitfield definitions 607 * preprocessor definitions for the bitfield "rx_tc_mode". 608 * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i" 609 */ 610 611/* register address for bitfield rx_tc_mode */ 612#define HW_ATL_RPB_RPF_RX_TC_MODE_ADR 0x00005700 613/* bitmask for bitfield rx_tc_mode */ 614#define HW_ATL_RPB_RPF_RX_TC_MODE_MSK 0x00000100 615/* inverted bitmask for bitfield rx_tc_mode */ 616#define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN 0xfffffeff 617/* lower bit position of bitfield rx_tc_mode */ 618#define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT 8 619/* width of bitfield rx_tc_mode */ 620#define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH 1 621/* default value of bitfield rx_tc_mode */ 622#define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT 0x0 623 624/* rx rx_buf_en bitfield definitions 625 * preprocessor definitions for the bitfield "rx_buf_en". 626 * port="pif_rpb_rx_buf_en_i" 627 */ 628 629/* register address for bitfield rx_buf_en */ 630#define HW_ATL_RPB_RX_BUF_EN_ADR 0x00005700 631/* bitmask for bitfield rx_buf_en */ 632#define HW_ATL_RPB_RX_BUF_EN_MSK 0x00000001 633/* inverted bitmask for bitfield rx_buf_en */ 634#define HW_ATL_RPB_RX_BUF_EN_MSKN 0xfffffffe 635/* lower bit position of bitfield rx_buf_en */ 636#define HW_ATL_RPB_RX_BUF_EN_SHIFT 0 637/* width of bitfield rx_buf_en */ 638#define HW_ATL_RPB_RX_BUF_EN_WIDTH 1 639/* default value of bitfield rx_buf_en */ 640#define HW_ATL_RPB_RX_BUF_EN_DEFAULT 0x0 641 642/* rx rx{b}_hi_thresh[d:0] bitfield definitions 643 * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]". 644 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 645 * port="pif_rpb_rx0_hi_thresh_i[13:0]" 646 */ 647 648/* register address for bitfield rx{b}_hi_thresh[d:0] */ 649#define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) 650/* bitmask for bitfield rx{b}_hi_thresh[d:0] */ 651#define HW_ATL_RPB_RXBHI_THRESH_MSK 0x3fff0000 652/* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */ 653#define HW_ATL_RPB_RXBHI_THRESH_MSKN 0xc000ffff 654/* lower bit position of bitfield rx{b}_hi_thresh[d:0] */ 655#define HW_ATL_RPB_RXBHI_THRESH_SHIFT 16 656/* width of bitfield rx{b}_hi_thresh[d:0] */ 657#define HW_ATL_RPB_RXBHI_THRESH_WIDTH 14 658/* default value of bitfield rx{b}_hi_thresh[d:0] */ 659#define HW_ATL_RPB_RXBHI_THRESH_DEFAULT 0x0 660 661/* rx rx{b}_lo_thresh[d:0] bitfield definitions 662 * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]". 663 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 664 * port="pif_rpb_rx0_lo_thresh_i[13:0]" 665 */ 666 667/* register address for bitfield rx{b}_lo_thresh[d:0] */ 668#define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) 669/* bitmask for bitfield rx{b}_lo_thresh[d:0] */ 670#define HW_ATL_RPB_RXBLO_THRESH_MSK 0x00003fff 671/* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */ 672#define HW_ATL_RPB_RXBLO_THRESH_MSKN 0xffffc000 673/* lower bit position of bitfield rx{b}_lo_thresh[d:0] */ 674#define HW_ATL_RPB_RXBLO_THRESH_SHIFT 0 675/* width of bitfield rx{b}_lo_thresh[d:0] */ 676#define HW_ATL_RPB_RXBLO_THRESH_WIDTH 14 677/* default value of bitfield rx{b}_lo_thresh[d:0] */ 678#define HW_ATL_RPB_RXBLO_THRESH_DEFAULT 0x0 679 680/* rx rx_fc_mode[1:0] bitfield definitions 681 * preprocessor definitions for the bitfield "rx_fc_mode[1:0]". 682 * port="pif_rpb_rx_fc_mode_i[1:0]" 683 */ 684 685/* register address for bitfield rx_fc_mode[1:0] */ 686#define HW_ATL_RPB_RX_FC_MODE_ADR 0x00005700 687/* bitmask for bitfield rx_fc_mode[1:0] */ 688#define HW_ATL_RPB_RX_FC_MODE_MSK 0x00000030 689/* inverted bitmask for bitfield rx_fc_mode[1:0] */ 690#define HW_ATL_RPB_RX_FC_MODE_MSKN 0xffffffcf 691/* lower bit position of bitfield rx_fc_mode[1:0] */ 692#define HW_ATL_RPB_RX_FC_MODE_SHIFT 4 693/* width of bitfield rx_fc_mode[1:0] */ 694#define HW_ATL_RPB_RX_FC_MODE_WIDTH 2 695/* default value of bitfield rx_fc_mode[1:0] */ 696#define HW_ATL_RPB_RX_FC_MODE_DEFAULT 0x0 697 698/* rx rx{b}_buf_size[8:0] bitfield definitions 699 * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]". 700 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 701 * port="pif_rpb_rx0_buf_size_i[8:0]" 702 */ 703 704/* register address for bitfield rx{b}_buf_size[8:0] */ 705#define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) (0x00005710 + (buffer) * 0x10) 706/* bitmask for bitfield rx{b}_buf_size[8:0] */ 707#define HW_ATL_RPB_RXBBUF_SIZE_MSK 0x000001ff 708/* inverted bitmask for bitfield rx{b}_buf_size[8:0] */ 709#define HW_ATL_RPB_RXBBUF_SIZE_MSKN 0xfffffe00 710/* lower bit position of bitfield rx{b}_buf_size[8:0] */ 711#define HW_ATL_RPB_RXBBUF_SIZE_SHIFT 0 712/* width of bitfield rx{b}_buf_size[8:0] */ 713#define HW_ATL_RPB_RXBBUF_SIZE_WIDTH 9 714/* default value of bitfield rx{b}_buf_size[8:0] */ 715#define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT 0x0 716 717/* rx rx{b}_xoff_en bitfield definitions 718 * preprocessor definitions for the bitfield "rx{b}_xoff_en". 719 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 720 * port="pif_rpb_rx_xoff_en_i[0]" 721 */ 722 723/* register address for bitfield rx{b}_xoff_en */ 724#define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) (0x00005714 + (buffer) * 0x10) 725/* bitmask for bitfield rx{b}_xoff_en */ 726#define HW_ATL_RPB_RXBXOFF_EN_MSK 0x80000000 727/* inverted bitmask for bitfield rx{b}_xoff_en */ 728#define HW_ATL_RPB_RXBXOFF_EN_MSKN 0x7fffffff 729/* lower bit position of bitfield rx{b}_xoff_en */ 730#define HW_ATL_RPB_RXBXOFF_EN_SHIFT 31 731/* width of bitfield rx{b}_xoff_en */ 732#define HW_ATL_RPB_RXBXOFF_EN_WIDTH 1 733/* default value of bitfield rx{b}_xoff_en */ 734#define HW_ATL_RPB_RXBXOFF_EN_DEFAULT 0x0 735 736/* rx l2_bc_thresh[f:0] bitfield definitions 737 * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]". 738 * port="pif_rpf_l2_bc_thresh_i[15:0]" 739 */ 740 741/* register address for bitfield l2_bc_thresh[f:0] */ 742#define HW_ATL_RPFL2BC_THRESH_ADR 0x00005100 743/* bitmask for bitfield l2_bc_thresh[f:0] */ 744#define HW_ATL_RPFL2BC_THRESH_MSK 0xffff0000 745/* inverted bitmask for bitfield l2_bc_thresh[f:0] */ 746#define HW_ATL_RPFL2BC_THRESH_MSKN 0x0000ffff 747/* lower bit position of bitfield l2_bc_thresh[f:0] */ 748#define HW_ATL_RPFL2BC_THRESH_SHIFT 16 749/* width of bitfield l2_bc_thresh[f:0] */ 750#define HW_ATL_RPFL2BC_THRESH_WIDTH 16 751/* default value of bitfield l2_bc_thresh[f:0] */ 752#define HW_ATL_RPFL2BC_THRESH_DEFAULT 0x0 753 754/* rx l2_bc_en bitfield definitions 755 * preprocessor definitions for the bitfield "l2_bc_en". 756 * port="pif_rpf_l2_bc_en_i" 757 */ 758 759/* register address for bitfield l2_bc_en */ 760#define HW_ATL_RPFL2BC_EN_ADR 0x00005100 761/* bitmask for bitfield l2_bc_en */ 762#define HW_ATL_RPFL2BC_EN_MSK 0x00000001 763/* inverted bitmask for bitfield l2_bc_en */ 764#define HW_ATL_RPFL2BC_EN_MSKN 0xfffffffe 765/* lower bit position of bitfield l2_bc_en */ 766#define HW_ATL_RPFL2BC_EN_SHIFT 0 767/* width of bitfield l2_bc_en */ 768#define HW_ATL_RPFL2BC_EN_WIDTH 1 769/* default value of bitfield l2_bc_en */ 770#define HW_ATL_RPFL2BC_EN_DEFAULT 0x0 771 772/* rx l2_bc_act[2:0] bitfield definitions 773 * preprocessor definitions for the bitfield "l2_bc_act[2:0]". 774 * port="pif_rpf_l2_bc_act_i[2:0]" 775 */ 776 777/* register address for bitfield l2_bc_act[2:0] */ 778#define HW_ATL_RPFL2BC_ACT_ADR 0x00005100 779/* bitmask for bitfield l2_bc_act[2:0] */ 780#define HW_ATL_RPFL2BC_ACT_MSK 0x00007000 781/* inverted bitmask for bitfield l2_bc_act[2:0] */ 782#define HW_ATL_RPFL2BC_ACT_MSKN 0xffff8fff 783/* lower bit position of bitfield l2_bc_act[2:0] */ 784#define HW_ATL_RPFL2BC_ACT_SHIFT 12 785/* width of bitfield l2_bc_act[2:0] */ 786#define HW_ATL_RPFL2BC_ACT_WIDTH 3 787/* default value of bitfield l2_bc_act[2:0] */ 788#define HW_ATL_RPFL2BC_ACT_DEFAULT 0x0 789 790/* rx l2_mc_en{f} bitfield definitions 791 * preprocessor definitions for the bitfield "l2_mc_en{f}". 792 * parameter: filter {f} | stride size 0x4 | range [0, 7] 793 * port="pif_rpf_l2_mc_en_i[0]" 794 */ 795 796/* register address for bitfield l2_mc_en{f} */ 797#define HW_ATL_RPFL2MC_ENF_ADR(filter) (0x00005250 + (filter) * 0x4) 798/* bitmask for bitfield l2_mc_en{f} */ 799#define HW_ATL_RPFL2MC_ENF_MSK 0x80000000 800/* inverted bitmask for bitfield l2_mc_en{f} */ 801#define HW_ATL_RPFL2MC_ENF_MSKN 0x7fffffff 802/* lower bit position of bitfield l2_mc_en{f} */ 803#define HW_ATL_RPFL2MC_ENF_SHIFT 31 804/* width of bitfield l2_mc_en{f} */ 805#define HW_ATL_RPFL2MC_ENF_WIDTH 1 806/* default value of bitfield l2_mc_en{f} */ 807#define HW_ATL_RPFL2MC_ENF_DEFAULT 0x0 808 809/* rx l2_promis_mode bitfield definitions 810 * preprocessor definitions for the bitfield "l2_promis_mode". 811 * port="pif_rpf_l2_promis_mode_i" 812 */ 813 814/* register address for bitfield l2_promis_mode */ 815#define HW_ATL_RPFL2PROMIS_MODE_ADR 0x00005100 816/* bitmask for bitfield l2_promis_mode */ 817#define HW_ATL_RPFL2PROMIS_MODE_MSK 0x00000008 818/* inverted bitmask for bitfield l2_promis_mode */ 819#define HW_ATL_RPFL2PROMIS_MODE_MSKN 0xfffffff7 820/* lower bit position of bitfield l2_promis_mode */ 821#define HW_ATL_RPFL2PROMIS_MODE_SHIFT 3 822/* width of bitfield l2_promis_mode */ 823#define HW_ATL_RPFL2PROMIS_MODE_WIDTH 1 824/* default value of bitfield l2_promis_mode */ 825#define HW_ATL_RPFL2PROMIS_MODE_DEFAULT 0x0 826 827/* rx l2_uc_act{f}[2:0] bitfield definitions 828 * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]". 829 * parameter: filter {f} | stride size 0x8 | range [0, 37] 830 * port="pif_rpf_l2_uc_act0_i[2:0]" 831 */ 832 833/* register address for bitfield l2_uc_act{f}[2:0] */ 834#define HW_ATL_RPFL2UC_ACTF_ADR(filter) (0x00005114 + (filter) * 0x8) 835/* bitmask for bitfield l2_uc_act{f}[2:0] */ 836#define HW_ATL_RPFL2UC_ACTF_MSK 0x00070000 837/* inverted bitmask for bitfield l2_uc_act{f}[2:0] */ 838#define HW_ATL_RPFL2UC_ACTF_MSKN 0xfff8ffff 839/* lower bit position of bitfield l2_uc_act{f}[2:0] */ 840#define HW_ATL_RPFL2UC_ACTF_SHIFT 16 841/* width of bitfield l2_uc_act{f}[2:0] */ 842#define HW_ATL_RPFL2UC_ACTF_WIDTH 3 843/* default value of bitfield l2_uc_act{f}[2:0] */ 844#define HW_ATL_RPFL2UC_ACTF_DEFAULT 0x0 845 846/* rx l2_uc_en{f} bitfield definitions 847 * preprocessor definitions for the bitfield "l2_uc_en{f}". 848 * parameter: filter {f} | stride size 0x8 | range [0, 37] 849 * port="pif_rpf_l2_uc_en_i[0]" 850 */ 851 852/* register address for bitfield l2_uc_en{f} */ 853#define HW_ATL_RPFL2UC_ENF_ADR(filter) (0x00005114 + (filter) * 0x8) 854/* bitmask for bitfield l2_uc_en{f} */ 855#define HW_ATL_RPFL2UC_ENF_MSK 0x80000000 856/* inverted bitmask for bitfield l2_uc_en{f} */ 857#define HW_ATL_RPFL2UC_ENF_MSKN 0x7fffffff 858/* lower bit position of bitfield l2_uc_en{f} */ 859#define HW_ATL_RPFL2UC_ENF_SHIFT 31 860/* width of bitfield l2_uc_en{f} */ 861#define HW_ATL_RPFL2UC_ENF_WIDTH 1 862/* default value of bitfield l2_uc_en{f} */ 863#define HW_ATL_RPFL2UC_ENF_DEFAULT 0x0 864 865/* register address for bitfield l2_uc_da{f}_lsw[1f:0] */ 866#define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) (0x00005110 + (filter) * 0x8) 867/* register address for bitfield l2_uc_da{f}_msw[f:0] */ 868#define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) (0x00005114 + (filter) * 0x8) 869/* bitmask for bitfield l2_uc_da{f}_msw[f:0] */ 870#define HW_ATL_RPFL2UC_DAFMSW_MSK 0x0000ffff 871/* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */ 872#define HW_ATL_RPFL2UC_DAFMSW_SHIFT 0 873 874/* rx l2_mc_accept_all bitfield definitions 875 * Preprocessor definitions for the bitfield "l2_mc_accept_all". 876 * PORT="pif_rpf_l2_mc_all_accept_i" 877 */ 878 879/* Register address for bitfield l2_mc_accept_all */ 880#define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR 0x00005270 881/* Bitmask for bitfield l2_mc_accept_all */ 882#define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK 0x00004000 883/* Inverted bitmask for bitfield l2_mc_accept_all */ 884#define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN 0xFFFFBFFF 885/* Lower bit position of bitfield l2_mc_accept_all */ 886#define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT 14 887/* Width of bitfield l2_mc_accept_all */ 888#define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH 1 889/* Default value of bitfield l2_mc_accept_all */ 890#define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT 0x0 891 892/* width of bitfield rx_tc_up{t}[2:0] */ 893#define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH 3 894/* default value of bitfield rx_tc_up{t}[2:0] */ 895#define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT 0x0 896 897/* rx rss_key_addr[4:0] bitfield definitions 898 * preprocessor definitions for the bitfield "rss_key_addr[4:0]". 899 * port="pif_rpf_rss_key_addr_i[4:0]" 900 */ 901 902/* register address for bitfield rss_key_addr[4:0] */ 903#define HW_ATL_RPF_RSS_KEY_ADDR_ADR 0x000054d0 904/* bitmask for bitfield rss_key_addr[4:0] */ 905#define HW_ATL_RPF_RSS_KEY_ADDR_MSK 0x0000001f 906/* inverted bitmask for bitfield rss_key_addr[4:0] */ 907#define HW_ATL_RPF_RSS_KEY_ADDR_MSKN 0xffffffe0 908/* lower bit position of bitfield rss_key_addr[4:0] */ 909#define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT 0 910/* width of bitfield rss_key_addr[4:0] */ 911#define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH 5 912/* default value of bitfield rss_key_addr[4:0] */ 913#define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT 0x0 914 915/* rx rss_key_wr_data[1f:0] bitfield definitions 916 * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]". 917 * port="pif_rpf_rss_key_wr_data_i[31:0]" 918 */ 919 920/* register address for bitfield rss_key_wr_data[1f:0] */ 921#define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR 0x000054d4 922/* bitmask for bitfield rss_key_wr_data[1f:0] */ 923#define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK 0xffffffff 924/* inverted bitmask for bitfield rss_key_wr_data[1f:0] */ 925#define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN 0x00000000 926/* lower bit position of bitfield rss_key_wr_data[1f:0] */ 927#define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT 0 928/* width of bitfield rss_key_wr_data[1f:0] */ 929#define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH 32 930/* default value of bitfield rss_key_wr_data[1f:0] */ 931#define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT 0x0 932 933/* rx rss_key_wr_en_i bitfield definitions 934 * preprocessor definitions for the bitfield "rss_key_wr_en_i". 935 * port="pif_rpf_rss_key_wr_en_i" 936 */ 937 938/* register address for bitfield rss_key_wr_en_i */ 939#define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR 0x000054d0 940/* bitmask for bitfield rss_key_wr_en_i */ 941#define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK 0x00000020 942/* inverted bitmask for bitfield rss_key_wr_en_i */ 943#define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN 0xffffffdf 944/* lower bit position of bitfield rss_key_wr_en_i */ 945#define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT 5 946/* width of bitfield rss_key_wr_en_i */ 947#define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH 1 948/* default value of bitfield rss_key_wr_en_i */ 949#define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT 0x0 950 951/* rx rss_redir_addr[3:0] bitfield definitions 952 * preprocessor definitions for the bitfield "rss_redir_addr[3:0]". 953 * port="pif_rpf_rss_redir_addr_i[3:0]" 954 */ 955 956/* register address for bitfield rss_redir_addr[3:0] */ 957#define HW_ATL_RPF_RSS_REDIR_ADDR_ADR 0x000054e0 958/* bitmask for bitfield rss_redir_addr[3:0] */ 959#define HW_ATL_RPF_RSS_REDIR_ADDR_MSK 0x0000000f 960/* inverted bitmask for bitfield rss_redir_addr[3:0] */ 961#define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN 0xfffffff0 962/* lower bit position of bitfield rss_redir_addr[3:0] */ 963#define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT 0 964/* width of bitfield rss_redir_addr[3:0] */ 965#define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH 4 966/* default value of bitfield rss_redir_addr[3:0] */ 967#define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT 0x0 968 969/* rx rss_redir_wr_data[f:0] bitfield definitions 970 * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]". 971 * port="pif_rpf_rss_redir_wr_data_i[15:0]" 972 */ 973 974/* register address for bitfield rss_redir_wr_data[f:0] */ 975#define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR 0x000054e4 976/* bitmask for bitfield rss_redir_wr_data[f:0] */ 977#define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK 0x0000ffff 978/* inverted bitmask for bitfield rss_redir_wr_data[f:0] */ 979#define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN 0xffff0000 980/* lower bit position of bitfield rss_redir_wr_data[f:0] */ 981#define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT 0 982/* width of bitfield rss_redir_wr_data[f:0] */ 983#define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH 16 984/* default value of bitfield rss_redir_wr_data[f:0] */ 985#define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT 0x0 986 987/* rx rss_redir_wr_en_i bitfield definitions 988 * preprocessor definitions for the bitfield "rss_redir_wr_en_i". 989 * port="pif_rpf_rss_redir_wr_en_i" 990 */ 991 992/* register address for bitfield rss_redir_wr_en_i */ 993#define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR 0x000054e0 994/* bitmask for bitfield rss_redir_wr_en_i */ 995#define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK 0x00000010 996/* inverted bitmask for bitfield rss_redir_wr_en_i */ 997#define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN 0xffffffef 998/* lower bit position of bitfield rss_redir_wr_en_i */ 999#define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT 4 1000/* width of bitfield rss_redir_wr_en_i */ 1001#define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH 1 1002/* default value of bitfield rss_redir_wr_en_i */ 1003#define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT 0x0 1004 1005/* rx tpo_rpf_sys_loopback bitfield definitions 1006 * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback". 1007 * port="pif_rpf_tpo_pkt_sys_lbk_i" 1008 */ 1009 1010/* register address for bitfield tpo_rpf_sys_loopback */ 1011#define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR 0x00005000 1012/* bitmask for bitfield tpo_rpf_sys_loopback */ 1013#define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK 0x00000100 1014/* inverted bitmask for bitfield tpo_rpf_sys_loopback */ 1015#define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN 0xfffffeff 1016/* lower bit position of bitfield tpo_rpf_sys_loopback */ 1017#define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT 8 1018/* width of bitfield tpo_rpf_sys_loopback */ 1019#define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH 1 1020/* default value of bitfield tpo_rpf_sys_loopback */ 1021#define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT 0x0 1022 1023/* rx vl_inner_tpid[f:0] bitfield definitions 1024 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]". 1025 * port="pif_rpf_vl_inner_tpid_i[15:0]" 1026 */ 1027 1028/* register address for bitfield vl_inner_tpid[f:0] */ 1029#define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284 1030/* bitmask for bitfield vl_inner_tpid[f:0] */ 1031#define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff 1032/* inverted bitmask for bitfield vl_inner_tpid[f:0] */ 1033#define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000 1034/* lower bit position of bitfield vl_inner_tpid[f:0] */ 1035#define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0 1036/* width of bitfield vl_inner_tpid[f:0] */ 1037#define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16 1038/* default value of bitfield vl_inner_tpid[f:0] */ 1039#define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100 1040 1041/* rx vl_outer_tpid[f:0] bitfield definitions 1042 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]". 1043 * port="pif_rpf_vl_outer_tpid_i[15:0]" 1044 */ 1045 1046/* register address for bitfield vl_outer_tpid[f:0] */ 1047#define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284 1048/* bitmask for bitfield vl_outer_tpid[f:0] */ 1049#define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000 1050/* inverted bitmask for bitfield vl_outer_tpid[f:0] */ 1051#define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff 1052/* lower bit position of bitfield vl_outer_tpid[f:0] */ 1053#define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16 1054/* width of bitfield vl_outer_tpid[f:0] */ 1055#define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16 1056/* default value of bitfield vl_outer_tpid[f:0] */ 1057#define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8 1058 1059/* rx vl_promis_mode bitfield definitions 1060 * preprocessor definitions for the bitfield "vl_promis_mode". 1061 * port="pif_rpf_vl_promis_mode_i" 1062 */ 1063 1064/* register address for bitfield vl_promis_mode */ 1065#define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280 1066/* bitmask for bitfield vl_promis_mode */ 1067#define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002 1068/* inverted bitmask for bitfield vl_promis_mode */ 1069#define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd 1070/* lower bit position of bitfield vl_promis_mode */ 1071#define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1 1072/* width of bitfield vl_promis_mode */ 1073#define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1 1074/* default value of bitfield vl_promis_mode */ 1075#define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0 1076 1077/* RX vl_accept_untagged_mode Bitfield Definitions 1078 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode". 1079 * PORT="pif_rpf_vl_accept_untagged_i" 1080 */ 1081 1082/* Register address for bitfield vl_accept_untagged_mode */ 1083#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280 1084/* Bitmask for bitfield vl_accept_untagged_mode */ 1085#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004 1086/* Inverted bitmask for bitfield vl_accept_untagged_mode */ 1087#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB 1088/* Lower bit position of bitfield vl_accept_untagged_mode */ 1089#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2 1090/* Width of bitfield vl_accept_untagged_mode */ 1091#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1 1092/* Default value of bitfield vl_accept_untagged_mode */ 1093#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0 1094 1095/* rX vl_untagged_act[2:0] Bitfield Definitions 1096 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]". 1097 * PORT="pif_rpf_vl_untagged_act_i[2:0]" 1098 */ 1099 1100/* Register address for bitfield vl_untagged_act[2:0] */ 1101#define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280 1102/* Bitmask for bitfield vl_untagged_act[2:0] */ 1103#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038 1104/* Inverted bitmask for bitfield vl_untagged_act[2:0] */ 1105#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7 1106/* Lower bit position of bitfield vl_untagged_act[2:0] */ 1107#define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3 1108/* Width of bitfield vl_untagged_act[2:0] */ 1109#define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3 1110/* Default value of bitfield vl_untagged_act[2:0] */ 1111#define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0 1112 1113/* RX vl_en{F} Bitfield Definitions 1114 * Preprocessor definitions for the bitfield "vl_en{F}". 1115 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1116 * PORT="pif_rpf_vl_en_i[0]" 1117 */ 1118 1119/* Register address for bitfield vl_en{F} */ 1120#define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1121/* Bitmask for bitfield vl_en{F} */ 1122#define HW_ATL_RPF_VL_EN_F_MSK 0x80000000 1123/* Inverted bitmask for bitfield vl_en{F} */ 1124#define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF 1125/* Lower bit position of bitfield vl_en{F} */ 1126#define HW_ATL_RPF_VL_EN_F_SHIFT 31 1127/* Width of bitfield vl_en{F} */ 1128#define HW_ATL_RPF_VL_EN_F_WIDTH 1 1129/* Default value of bitfield vl_en{F} */ 1130#define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0 1131 1132/* RX vl_act{F}[2:0] Bitfield Definitions 1133 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]". 1134 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1135 * PORT="pif_rpf_vl_act0_i[2:0]" 1136 */ 1137 1138/* Register address for bitfield vl_act{F}[2:0] */ 1139#define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1140/* Bitmask for bitfield vl_act{F}[2:0] */ 1141#define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000 1142/* Inverted bitmask for bitfield vl_act{F}[2:0] */ 1143#define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF 1144/* Lower bit position of bitfield vl_act{F}[2:0] */ 1145#define HW_ATL_RPF_VL_ACT_F_SHIFT 16 1146/* Width of bitfield vl_act{F}[2:0] */ 1147#define HW_ATL_RPF_VL_ACT_F_WIDTH 3 1148/* Default value of bitfield vl_act{F}[2:0] */ 1149#define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0 1150 1151/* RX vl_id{F}[B:0] Bitfield Definitions 1152 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]". 1153 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1154 * PORT="pif_rpf_vl_id0_i[11:0]" 1155 */ 1156 1157/* Register address for bitfield vl_id{F}[B:0] */ 1158#define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1159/* Bitmask for bitfield vl_id{F}[B:0] */ 1160#define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF 1161/* Inverted bitmask for bitfield vl_id{F}[B:0] */ 1162#define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000 1163/* Lower bit position of bitfield vl_id{F}[B:0] */ 1164#define HW_ATL_RPF_VL_ID_F_SHIFT 0 1165/* Width of bitfield vl_id{F}[B:0] */ 1166#define HW_ATL_RPF_VL_ID_F_WIDTH 12 1167/* Default value of bitfield vl_id{F}[B:0] */ 1168#define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0 1169 1170/* RX vl_rxq_en{F} Bitfield Definitions 1171 * Preprocessor definitions for the bitfield "vl_rxq{F}". 1172 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1173 * PORT="pif_rpf_vl_rxq_en_i" 1174 */ 1175 1176/* Register address for bitfield vl_rxq_en{F} */ 1177#define HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1178/* Bitmask for bitfield vl_rxq_en{F} */ 1179#define HW_ATL_RPF_VL_RXQ_EN_F_MSK 0x10000000 1180/* Inverted bitmask for bitfield vl_rxq_en{F}[ */ 1181#define HW_ATL_RPF_VL_RXQ_EN_F_MSKN 0xEFFFFFFF 1182/* Lower bit position of bitfield vl_rxq_en{F} */ 1183#define HW_ATL_RPF_VL_RXQ_EN_F_SHIFT 28 1184/* Width of bitfield vl_rxq_en{F} */ 1185#define HW_ATL_RPF_VL_RXQ_EN_F_WIDTH 1 1186/* Default value of bitfield vl_rxq_en{F} */ 1187#define HW_ATL_RPF_VL_RXQ_EN_F_DEFAULT 0x0 1188 1189/* RX vl_rxq{F}[4:0] Bitfield Definitions 1190 * Preprocessor definitions for the bitfield "vl_rxq{F}[4:0]". 1191 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1192 * PORT="pif_rpf_vl_rxq0_i[4:0]" 1193 */ 1194 1195/* Register address for bitfield vl_rxq{F}[4:0] */ 1196#define HW_ATL_RPF_VL_RXQ_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1197/* Bitmask for bitfield vl_rxq{F}[4:0] */ 1198#define HW_ATL_RPF_VL_RXQ_F_MSK 0x01F00000 1199/* Inverted bitmask for bitfield vl_rxq{F}[4:0] */ 1200#define HW_ATL_RPF_VL_RXQ_F_MSKN 0xFE0FFFFF 1201/* Lower bit position of bitfield vl_rxq{F}[4:0] */ 1202#define HW_ATL_RPF_VL_RXQ_F_SHIFT 20 1203/* Width of bitfield vl_rxw{F}[4:0] */ 1204#define HW_ATL_RPF_VL_RXQ_F_WIDTH 5 1205/* Default value of bitfield vl_rxq{F}[4:0] */ 1206#define HW_ATL_RPF_VL_RXQ_F_DEFAULT 0x0 1207 1208/* rx et_en{f} bitfield definitions 1209 * preprocessor definitions for the bitfield "et_en{f}". 1210 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1211 * port="pif_rpf_et_en_i[0]" 1212 */ 1213 1214/* register address for bitfield et_en{f} */ 1215#define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4) 1216/* bitmask for bitfield et_en{f} */ 1217#define HW_ATL_RPF_ET_ENF_MSK 0x80000000 1218/* inverted bitmask for bitfield et_en{f} */ 1219#define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff 1220/* lower bit position of bitfield et_en{f} */ 1221#define HW_ATL_RPF_ET_ENF_SHIFT 31 1222/* width of bitfield et_en{f} */ 1223#define HW_ATL_RPF_ET_ENF_WIDTH 1 1224/* default value of bitfield et_en{f} */ 1225#define HW_ATL_RPF_ET_ENF_DEFAULT 0x0 1226 1227/* rx et_up{f}_en bitfield definitions 1228 * preprocessor definitions for the bitfield "et_up{f}_en". 1229 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1230 * port="pif_rpf_et_up_en_i[0]" 1231 */ 1232 1233/* register address for bitfield et_up{f}_en */ 1234#define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4) 1235/* bitmask for bitfield et_up{f}_en */ 1236#define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000 1237/* inverted bitmask for bitfield et_up{f}_en */ 1238#define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff 1239/* lower bit position of bitfield et_up{f}_en */ 1240#define HW_ATL_RPF_ET_UPFEN_SHIFT 30 1241/* width of bitfield et_up{f}_en */ 1242#define HW_ATL_RPF_ET_UPFEN_WIDTH 1 1243/* default value of bitfield et_up{f}_en */ 1244#define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0 1245 1246/* rx et_rxq{f}_en bitfield definitions 1247 * preprocessor definitions for the bitfield "et_rxq{f}_en". 1248 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1249 * port="pif_rpf_et_rxq_en_i[0]" 1250 */ 1251 1252/* register address for bitfield et_rxq{f}_en */ 1253#define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4) 1254/* bitmask for bitfield et_rxq{f}_en */ 1255#define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000 1256/* inverted bitmask for bitfield et_rxq{f}_en */ 1257#define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff 1258/* lower bit position of bitfield et_rxq{f}_en */ 1259#define HW_ATL_RPF_ET_RXQFEN_SHIFT 29 1260/* width of bitfield et_rxq{f}_en */ 1261#define HW_ATL_RPF_ET_RXQFEN_WIDTH 1 1262/* default value of bitfield et_rxq{f}_en */ 1263#define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0 1264 1265/* rx et_up{f}[2:0] bitfield definitions 1266 * preprocessor definitions for the bitfield "et_up{f}[2:0]". 1267 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1268 * port="pif_rpf_et_up0_i[2:0]" 1269 */ 1270 1271/* register address for bitfield et_up{f}[2:0] */ 1272#define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4) 1273/* bitmask for bitfield et_up{f}[2:0] */ 1274#define HW_ATL_RPF_ET_UPF_MSK 0x1c000000 1275/* inverted bitmask for bitfield et_up{f}[2:0] */ 1276#define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff 1277/* lower bit position of bitfield et_up{f}[2:0] */ 1278#define HW_ATL_RPF_ET_UPF_SHIFT 26 1279/* width of bitfield et_up{f}[2:0] */ 1280#define HW_ATL_RPF_ET_UPF_WIDTH 3 1281/* default value of bitfield et_up{f}[2:0] */ 1282#define HW_ATL_RPF_ET_UPF_DEFAULT 0x0 1283 1284/* rx et_rxq{f}[4:0] bitfield definitions 1285 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]". 1286 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1287 * port="pif_rpf_et_rxq0_i[4:0]" 1288 */ 1289 1290/* register address for bitfield et_rxq{f}[4:0] */ 1291#define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) 1292/* bitmask for bitfield et_rxq{f}[4:0] */ 1293#define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000 1294/* inverted bitmask for bitfield et_rxq{f}[4:0] */ 1295#define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff 1296/* lower bit position of bitfield et_rxq{f}[4:0] */ 1297#define HW_ATL_RPF_ET_RXQF_SHIFT 20 1298/* width of bitfield et_rxq{f}[4:0] */ 1299#define HW_ATL_RPF_ET_RXQF_WIDTH 5 1300/* default value of bitfield et_rxq{f}[4:0] */ 1301#define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0 1302 1303/* rx et_mng_rxq{f} bitfield definitions 1304 * preprocessor definitions for the bitfield "et_mng_rxq{f}". 1305 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1306 * port="pif_rpf_et_mng_rxq_i[0]" 1307 */ 1308 1309/* register address for bitfield et_mng_rxq{f} */ 1310#define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) 1311/* bitmask for bitfield et_mng_rxq{f} */ 1312#define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000 1313/* inverted bitmask for bitfield et_mng_rxq{f} */ 1314#define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff 1315/* lower bit position of bitfield et_mng_rxq{f} */ 1316#define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19 1317/* width of bitfield et_mng_rxq{f} */ 1318#define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1 1319/* default value of bitfield et_mng_rxq{f} */ 1320#define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0 1321 1322/* rx et_act{f}[2:0] bitfield definitions 1323 * preprocessor definitions for the bitfield "et_act{f}[2:0]". 1324 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1325 * port="pif_rpf_et_act0_i[2:0]" 1326 */ 1327 1328/* register address for bitfield et_act{f}[2:0] */ 1329#define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4) 1330/* bitmask for bitfield et_act{f}[2:0] */ 1331#define HW_ATL_RPF_ET_ACTF_MSK 0x00070000 1332/* inverted bitmask for bitfield et_act{f}[2:0] */ 1333#define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff 1334/* lower bit position of bitfield et_act{f}[2:0] */ 1335#define HW_ATL_RPF_ET_ACTF_SHIFT 16 1336/* width of bitfield et_act{f}[2:0] */ 1337#define HW_ATL_RPF_ET_ACTF_WIDTH 3 1338/* default value of bitfield et_act{f}[2:0] */ 1339#define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0 1340 1341/* rx et_val{f}[f:0] bitfield definitions 1342 * preprocessor definitions for the bitfield "et_val{f}[f:0]". 1343 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1344 * port="pif_rpf_et_val0_i[15:0]" 1345 */ 1346 1347/* register address for bitfield et_val{f}[f:0] */ 1348#define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4) 1349/* bitmask for bitfield et_val{f}[f:0] */ 1350#define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff 1351/* inverted bitmask for bitfield et_val{f}[f:0] */ 1352#define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000 1353/* lower bit position of bitfield et_val{f}[f:0] */ 1354#define HW_ATL_RPF_ET_VALF_SHIFT 0 1355/* width of bitfield et_val{f}[f:0] */ 1356#define HW_ATL_RPF_ET_VALF_WIDTH 16 1357/* default value of bitfield et_val{f}[f:0] */ 1358#define HW_ATL_RPF_ET_VALF_DEFAULT 0x0 1359 1360/* RX l3_l4_en{F} Bitfield Definitions 1361 * Preprocessor definitions for the bitfield "l3_l4_en{F}". 1362 * Parameter: filter {F} | stride size 0x4 | range [0, 7] 1363 * PORT="pif_rpf_l3_l4_en_i[0]" 1364 */ 1365 1366#define HW_ATL_RPF_L3_REG_CTRL_ADR(filter) (0x00005380 + (filter) * 0x4) 1367 1368/* RX rpf_l3_sa{D}[1F:0] Bitfield Definitions 1369 * Preprocessor definitions for the bitfield "l3_sa{D}[1F:0]". 1370 * Parameter: location {D} | stride size 0x4 | range [0, 7] 1371 * PORT="pif_rpf_l3_sa0_i[31:0]" 1372 */ 1373 1374/* Register address for bitfield pif_rpf_l3_sa0_i[31:0] */ 1375#define HW_ATL_RPF_L3_SRCA_ADR(filter) (0x000053B0 + (filter) * 0x4) 1376/* Bitmask for bitfield l3_sa0[1F:0] */ 1377#define HW_ATL_RPF_L3_SRCA_MSK 0xFFFFFFFFu 1378/* Inverted bitmask for bitfield l3_sa0[1F:0] */ 1379#define HW_ATL_RPF_L3_SRCA_MSKN 0xFFFFFFFFu 1380/* Lower bit position of bitfield l3_sa0[1F:0] */ 1381#define HW_ATL_RPF_L3_SRCA_SHIFT 0 1382/* Width of bitfield l3_sa0[1F:0] */ 1383#define HW_ATL_RPF_L3_SRCA_WIDTH 32 1384/* Default value of bitfield l3_sa0[1F:0] */ 1385#define HW_ATL_RPF_L3_SRCA_DEFAULT 0x0 1386 1387/* RX rpf_l3_da{D}[1F:0] Bitfield Definitions 1388 * Preprocessor definitions for the bitfield "l3_da{D}[1F:0]". 1389 * Parameter: location {D} | stride size 0x4 | range [0, 7] 1390 * PORT="pif_rpf_l3_da0_i[31:0]" 1391 */ 1392 1393 /* Register address for bitfield pif_rpf_l3_da0_i[31:0] */ 1394#define HW_ATL_RPF_L3_DSTA_ADR(filter) (0x000053D0 + (filter) * 0x4) 1395/* Bitmask for bitfield l3_da0[1F:0] */ 1396#define HW_ATL_RPF_L3_DSTA_MSK 0xFFFFFFFFu 1397/* Inverted bitmask for bitfield l3_da0[1F:0] */ 1398#define HW_ATL_RPF_L3_DSTA_MSKN 0xFFFFFFFFu 1399/* Lower bit position of bitfield l3_da0[1F:0] */ 1400#define HW_ATL_RPF_L3_DSTA_SHIFT 0 1401/* Width of bitfield l3_da0[1F:0] */ 1402#define HW_ATL_RPF_L3_DSTA_WIDTH 32 1403/* Default value of bitfield l3_da0[1F:0] */ 1404#define HW_ATL_RPF_L3_DSTA_DEFAULT 0x0 1405 1406/* RX l4_sp{D}[F:0] Bitfield Definitions 1407 * Preprocessor definitions for the bitfield "l4_sp{D}[F:0]". 1408 * Parameter: srcport {D} | stride size 0x4 | range [0, 7] 1409 * PORT="pif_rpf_l4_sp0_i[15:0]" 1410 */ 1411 1412/* Register address for bitfield l4_sp{D}[F:0] */ 1413#define HW_ATL_RPF_L4_SPD_ADR(srcport) (0x00005400u + (srcport) * 0x4) 1414/* Bitmask for bitfield l4_sp{D}[F:0] */ 1415#define HW_ATL_RPF_L4_SPD_MSK 0x0000FFFFu 1416/* Inverted bitmask for bitfield l4_sp{D}[F:0] */ 1417#define HW_ATL_RPF_L4_SPD_MSKN 0xFFFF0000u 1418/* Lower bit position of bitfield l4_sp{D}[F:0] */ 1419#define HW_ATL_RPF_L4_SPD_SHIFT 0 1420/* Width of bitfield l4_sp{D}[F:0] */ 1421#define HW_ATL_RPF_L4_SPD_WIDTH 16 1422/* Default value of bitfield l4_sp{D}[F:0] */ 1423#define HW_ATL_RPF_L4_SPD_DEFAULT 0x0 1424 1425/* RX l4_dp{D}[F:0] Bitfield Definitions 1426 * Preprocessor definitions for the bitfield "l4_dp{D}[F:0]". 1427 * Parameter: destport {D} | stride size 0x4 | range [0, 7] 1428 * PORT="pif_rpf_l4_dp0_i[15:0]" 1429 */ 1430 1431/* Register address for bitfield l4_dp{D}[F:0] */ 1432#define HW_ATL_RPF_L4_DPD_ADR(destport) (0x00005420u + (destport) * 0x4) 1433/* Bitmask for bitfield l4_dp{D}[F:0] */ 1434#define HW_ATL_RPF_L4_DPD_MSK 0x0000FFFFu 1435/* Inverted bitmask for bitfield l4_dp{D}[F:0] */ 1436#define HW_ATL_RPF_L4_DPD_MSKN 0xFFFF0000u 1437/* Lower bit position of bitfield l4_dp{D}[F:0] */ 1438#define HW_ATL_RPF_L4_DPD_SHIFT 0 1439/* Width of bitfield l4_dp{D}[F:0] */ 1440#define HW_ATL_RPF_L4_DPD_WIDTH 16 1441/* Default value of bitfield l4_dp{D}[F:0] */ 1442#define HW_ATL_RPF_L4_DPD_DEFAULT 0x0 1443 1444/* rx ipv4_chk_en bitfield definitions 1445 * preprocessor definitions for the bitfield "ipv4_chk_en". 1446 * port="pif_rpo_ipv4_chk_en_i" 1447 */ 1448 1449/* register address for bitfield ipv4_chk_en */ 1450#define HW_ATL_RPO_IPV4CHK_EN_ADR 0x00005580 1451/* bitmask for bitfield ipv4_chk_en */ 1452#define HW_ATL_RPO_IPV4CHK_EN_MSK 0x00000002 1453/* inverted bitmask for bitfield ipv4_chk_en */ 1454#define HW_ATL_RPO_IPV4CHK_EN_MSKN 0xfffffffd 1455/* lower bit position of bitfield ipv4_chk_en */ 1456#define HW_ATL_RPO_IPV4CHK_EN_SHIFT 1 1457/* width of bitfield ipv4_chk_en */ 1458#define HW_ATL_RPO_IPV4CHK_EN_WIDTH 1 1459/* default value of bitfield ipv4_chk_en */ 1460#define HW_ATL_RPO_IPV4CHK_EN_DEFAULT 0x0 1461 1462/* rx desc{d}_vl_strip bitfield definitions 1463 * preprocessor definitions for the bitfield "desc{d}_vl_strip". 1464 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 1465 * port="pif_rpo_desc_vl_strip_i[0]" 1466 */ 1467 1468/* register address for bitfield desc{d}_vl_strip */ 1469#define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) \ 1470 (0x00005b08 + (descriptor) * 0x20) 1471/* bitmask for bitfield desc{d}_vl_strip */ 1472#define HW_ATL_RPO_DESCDVL_STRIP_MSK 0x20000000 1473/* inverted bitmask for bitfield desc{d}_vl_strip */ 1474#define HW_ATL_RPO_DESCDVL_STRIP_MSKN 0xdfffffff 1475/* lower bit position of bitfield desc{d}_vl_strip */ 1476#define HW_ATL_RPO_DESCDVL_STRIP_SHIFT 29 1477/* width of bitfield desc{d}_vl_strip */ 1478#define HW_ATL_RPO_DESCDVL_STRIP_WIDTH 1 1479/* default value of bitfield desc{d}_vl_strip */ 1480#define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT 0x0 1481 1482/* rx l4_chk_en bitfield definitions 1483 * preprocessor definitions for the bitfield "l4_chk_en". 1484 * port="pif_rpo_l4_chk_en_i" 1485 */ 1486 1487/* register address for bitfield l4_chk_en */ 1488#define HW_ATL_RPOL4CHK_EN_ADR 0x00005580 1489/* bitmask for bitfield l4_chk_en */ 1490#define HW_ATL_RPOL4CHK_EN_MSK 0x00000001 1491/* inverted bitmask for bitfield l4_chk_en */ 1492#define HW_ATL_RPOL4CHK_EN_MSKN 0xfffffffe 1493/* lower bit position of bitfield l4_chk_en */ 1494#define HW_ATL_RPOL4CHK_EN_SHIFT 0 1495/* width of bitfield l4_chk_en */ 1496#define HW_ATL_RPOL4CHK_EN_WIDTH 1 1497/* default value of bitfield l4_chk_en */ 1498#define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0 1499 1500/* RX outer_vl_ins_mode Bitfield Definitions 1501 * Preprocessor definitions for the bitfield "outer_vl_ins_mode". 1502 * PORT="pif_rpo_outer_vl_mode_i" 1503 */ 1504 1505/* Register address for bitfield outer_vl_ins_mode */ 1506#define HW_ATL_RPO_OUTER_VL_INS_MODE_ADR 0x00005580 1507/* Bitmask for bitfield outer_vl_ins_mode */ 1508#define HW_ATL_RPO_OUTER_VL_INS_MODE_MSK 0x00000004 1509/* Inverted bitmask for bitfield outer_vl_ins_mode */ 1510#define HW_ATL_RPO_OUTER_VL_INS_MODE_MSKN 0xFFFFFFFB 1511/* Lower bit position of bitfield outer_vl_ins_mode */ 1512#define HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT 2 1513/* Width of bitfield outer_vl_ins_mode */ 1514#define HW_ATL_RPO_OUTER_VL_INS_MODE_WIDTH 1 1515/* Default value of bitfield outer_vl_ins_mode */ 1516#define HW_ATL_RPO_OUTER_VL_INS_MODE_DEFAULT 0x0 1517 1518/* rx reg_res_dsbl bitfield definitions 1519 * preprocessor definitions for the bitfield "reg_res_dsbl". 1520 * port="pif_rx_reg_res_dsbl_i" 1521 */ 1522 1523/* register address for bitfield reg_res_dsbl */ 1524#define HW_ATL_RX_REG_RES_DSBL_ADR 0x00005000 1525/* bitmask for bitfield reg_res_dsbl */ 1526#define HW_ATL_RX_REG_RES_DSBL_MSK 0x20000000 1527/* inverted bitmask for bitfield reg_res_dsbl */ 1528#define HW_ATL_RX_REG_RES_DSBL_MSKN 0xdfffffff 1529/* lower bit position of bitfield reg_res_dsbl */ 1530#define HW_ATL_RX_REG_RES_DSBL_SHIFT 29 1531/* width of bitfield reg_res_dsbl */ 1532#define HW_ATL_RX_REG_RES_DSBL_WIDTH 1 1533/* default value of bitfield reg_res_dsbl */ 1534#define HW_ATL_RX_REG_RES_DSBL_DEFAULT 0x1 1535 1536/* tx dca{d}_cpuid[7:0] bitfield definitions 1537 * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]". 1538 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1539 * port="pif_tdm_dca0_cpuid_i[7:0]" 1540 */ 1541 1542/* register address for bitfield dca{d}_cpuid[7:0] */ 1543#define HW_ATL_TDM_DCADCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) 1544/* bitmask for bitfield dca{d}_cpuid[7:0] */ 1545#define HW_ATL_TDM_DCADCPUID_MSK 0x000000ff 1546/* inverted bitmask for bitfield dca{d}_cpuid[7:0] */ 1547#define HW_ATL_TDM_DCADCPUID_MSKN 0xffffff00 1548/* lower bit position of bitfield dca{d}_cpuid[7:0] */ 1549#define HW_ATL_TDM_DCADCPUID_SHIFT 0 1550/* width of bitfield dca{d}_cpuid[7:0] */ 1551#define HW_ATL_TDM_DCADCPUID_WIDTH 8 1552/* default value of bitfield dca{d}_cpuid[7:0] */ 1553#define HW_ATL_TDM_DCADCPUID_DEFAULT 0x0 1554 1555/* tx lso_en[1f:0] bitfield definitions 1556 * preprocessor definitions for the bitfield "lso_en[1f:0]". 1557 * port="pif_tdm_lso_en_i[31:0]" 1558 */ 1559 1560/* register address for bitfield lso_en[1f:0] */ 1561#define HW_ATL_TDM_LSO_EN_ADR 0x00007810 1562/* bitmask for bitfield lso_en[1f:0] */ 1563#define HW_ATL_TDM_LSO_EN_MSK 0xffffffff 1564/* inverted bitmask for bitfield lso_en[1f:0] */ 1565#define HW_ATL_TDM_LSO_EN_MSKN 0x00000000 1566/* lower bit position of bitfield lso_en[1f:0] */ 1567#define HW_ATL_TDM_LSO_EN_SHIFT 0 1568/* width of bitfield lso_en[1f:0] */ 1569#define HW_ATL_TDM_LSO_EN_WIDTH 32 1570/* default value of bitfield lso_en[1f:0] */ 1571#define HW_ATL_TDM_LSO_EN_DEFAULT 0x0 1572 1573/* tx dca_en bitfield definitions 1574 * preprocessor definitions for the bitfield "dca_en". 1575 * port="pif_tdm_dca_en_i" 1576 */ 1577 1578/* register address for bitfield dca_en */ 1579#define HW_ATL_TDM_DCA_EN_ADR 0x00008480 1580/* bitmask for bitfield dca_en */ 1581#define HW_ATL_TDM_DCA_EN_MSK 0x80000000 1582/* inverted bitmask for bitfield dca_en */ 1583#define HW_ATL_TDM_DCA_EN_MSKN 0x7fffffff 1584/* lower bit position of bitfield dca_en */ 1585#define HW_ATL_TDM_DCA_EN_SHIFT 31 1586/* width of bitfield dca_en */ 1587#define HW_ATL_TDM_DCA_EN_WIDTH 1 1588/* default value of bitfield dca_en */ 1589#define HW_ATL_TDM_DCA_EN_DEFAULT 0x1 1590 1591/* tx dca_mode[3:0] bitfield definitions 1592 * preprocessor definitions for the bitfield "dca_mode[3:0]". 1593 * port="pif_tdm_dca_mode_i[3:0]" 1594 */ 1595 1596/* register address for bitfield dca_mode[3:0] */ 1597#define HW_ATL_TDM_DCA_MODE_ADR 0x00008480 1598/* bitmask for bitfield dca_mode[3:0] */ 1599#define HW_ATL_TDM_DCA_MODE_MSK 0x0000000f 1600/* inverted bitmask for bitfield dca_mode[3:0] */ 1601#define HW_ATL_TDM_DCA_MODE_MSKN 0xfffffff0 1602/* lower bit position of bitfield dca_mode[3:0] */ 1603#define HW_ATL_TDM_DCA_MODE_SHIFT 0 1604/* width of bitfield dca_mode[3:0] */ 1605#define HW_ATL_TDM_DCA_MODE_WIDTH 4 1606/* default value of bitfield dca_mode[3:0] */ 1607#define HW_ATL_TDM_DCA_MODE_DEFAULT 0x0 1608 1609/* tx dca{d}_desc_en bitfield definitions 1610 * preprocessor definitions for the bitfield "dca{d}_desc_en". 1611 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1612 * port="pif_tdm_dca_desc_en_i[0]" 1613 */ 1614 1615/* register address for bitfield dca{d}_desc_en */ 1616#define HW_ATL_TDM_DCADDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) 1617/* bitmask for bitfield dca{d}_desc_en */ 1618#define HW_ATL_TDM_DCADDESC_EN_MSK 0x80000000 1619/* inverted bitmask for bitfield dca{d}_desc_en */ 1620#define HW_ATL_TDM_DCADDESC_EN_MSKN 0x7fffffff 1621/* lower bit position of bitfield dca{d}_desc_en */ 1622#define HW_ATL_TDM_DCADDESC_EN_SHIFT 31 1623/* width of bitfield dca{d}_desc_en */ 1624#define HW_ATL_TDM_DCADDESC_EN_WIDTH 1 1625/* default value of bitfield dca{d}_desc_en */ 1626#define HW_ATL_TDM_DCADDESC_EN_DEFAULT 0x0 1627 1628/* tx desc{d}_en bitfield definitions 1629 * preprocessor definitions for the bitfield "desc{d}_en". 1630 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1631 * port="pif_tdm_desc_en_i[0]" 1632 */ 1633 1634/* register address for bitfield desc{d}_en */ 1635#define HW_ATL_TDM_DESCDEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) 1636/* bitmask for bitfield desc{d}_en */ 1637#define HW_ATL_TDM_DESCDEN_MSK 0x80000000 1638/* inverted bitmask for bitfield desc{d}_en */ 1639#define HW_ATL_TDM_DESCDEN_MSKN 0x7fffffff 1640/* lower bit position of bitfield desc{d}_en */ 1641#define HW_ATL_TDM_DESCDEN_SHIFT 31 1642/* width of bitfield desc{d}_en */ 1643#define HW_ATL_TDM_DESCDEN_WIDTH 1 1644/* default value of bitfield desc{d}_en */ 1645#define HW_ATL_TDM_DESCDEN_DEFAULT 0x0 1646 1647/* tx desc{d}_hd[c:0] bitfield definitions 1648 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 1649 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1650 * port="tdm_pif_desc0_hd_o[12:0]" 1651 */ 1652 1653/* register address for bitfield desc{d}_hd[c:0] */ 1654#define HW_ATL_TDM_DESCDHD_ADR(descriptor) (0x00007c0c + (descriptor) * 0x40) 1655/* bitmask for bitfield desc{d}_hd[c:0] */ 1656#define HW_ATL_TDM_DESCDHD_MSK 0x00001fff 1657/* inverted bitmask for bitfield desc{d}_hd[c:0] */ 1658#define HW_ATL_TDM_DESCDHD_MSKN 0xffffe000 1659/* lower bit position of bitfield desc{d}_hd[c:0] */ 1660#define HW_ATL_TDM_DESCDHD_SHIFT 0 1661/* width of bitfield desc{d}_hd[c:0] */ 1662#define HW_ATL_TDM_DESCDHD_WIDTH 13 1663 1664/* tx desc{d}_len[9:0] bitfield definitions 1665 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 1666 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1667 * port="pif_tdm_desc0_len_i[9:0]" 1668 */ 1669 1670/* register address for bitfield desc{d}_len[9:0] */ 1671#define HW_ATL_TDM_DESCDLEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) 1672/* bitmask for bitfield desc{d}_len[9:0] */ 1673#define HW_ATL_TDM_DESCDLEN_MSK 0x00001ff8 1674/* inverted bitmask for bitfield desc{d}_len[9:0] */ 1675#define HW_ATL_TDM_DESCDLEN_MSKN 0xffffe007 1676/* lower bit position of bitfield desc{d}_len[9:0] */ 1677#define HW_ATL_TDM_DESCDLEN_SHIFT 3 1678/* width of bitfield desc{d}_len[9:0] */ 1679#define HW_ATL_TDM_DESCDLEN_WIDTH 10 1680/* default value of bitfield desc{d}_len[9:0] */ 1681#define HW_ATL_TDM_DESCDLEN_DEFAULT 0x0 1682 1683/* tx int_desc_wrb_en bitfield definitions 1684 * preprocessor definitions for the bitfield "int_desc_wrb_en". 1685 * port="pif_tdm_int_desc_wrb_en_i" 1686 */ 1687 1688/* register address for bitfield int_desc_wrb_en */ 1689#define HW_ATL_TDM_INT_DESC_WRB_EN_ADR 0x00007b40 1690/* bitmask for bitfield int_desc_wrb_en */ 1691#define HW_ATL_TDM_INT_DESC_WRB_EN_MSK 0x00000002 1692/* inverted bitmask for bitfield int_desc_wrb_en */ 1693#define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN 0xfffffffd 1694/* lower bit position of bitfield int_desc_wrb_en */ 1695#define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT 1 1696/* width of bitfield int_desc_wrb_en */ 1697#define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH 1 1698/* default value of bitfield int_desc_wrb_en */ 1699#define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT 0x0 1700 1701/* tx desc{d}_wrb_thresh[6:0] bitfield definitions 1702 * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]". 1703 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1704 * port="pif_tdm_desc0_wrb_thresh_i[6:0]" 1705 */ 1706 1707/* register address for bitfield desc{d}_wrb_thresh[6:0] */ 1708#define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) \ 1709 (0x00007c18 + (descriptor) * 0x40) 1710/* bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1711#define HW_ATL_TDM_DESCDWRB_THRESH_MSK 0x00007f00 1712/* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1713#define HW_ATL_TDM_DESCDWRB_THRESH_MSKN 0xffff80ff 1714/* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */ 1715#define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT 8 1716/* width of bitfield desc{d}_wrb_thresh[6:0] */ 1717#define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH 7 1718/* default value of bitfield desc{d}_wrb_thresh[6:0] */ 1719#define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT 0x0 1720 1721/* tx lso_tcp_flag_first[b:0] bitfield definitions 1722 * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]". 1723 * port="pif_thm_lso_tcp_flag_first_i[11:0]" 1724 */ 1725 1726/* register address for bitfield lso_tcp_flag_first[b:0] */ 1727#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR 0x00007820 1728/* bitmask for bitfield lso_tcp_flag_first[b:0] */ 1729#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK 0x00000fff 1730/* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */ 1731#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN 0xfffff000 1732/* lower bit position of bitfield lso_tcp_flag_first[b:0] */ 1733#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT 0 1734/* width of bitfield lso_tcp_flag_first[b:0] */ 1735#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH 12 1736/* default value of bitfield lso_tcp_flag_first[b:0] */ 1737#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT 0x0 1738 1739/* tx lso_tcp_flag_last[b:0] bitfield definitions 1740 * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]". 1741 * port="pif_thm_lso_tcp_flag_last_i[11:0]" 1742 */ 1743 1744/* register address for bitfield lso_tcp_flag_last[b:0] */ 1745#define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR 0x00007824 1746/* bitmask for bitfield lso_tcp_flag_last[b:0] */ 1747#define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK 0x00000fff 1748/* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */ 1749#define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN 0xfffff000 1750/* lower bit position of bitfield lso_tcp_flag_last[b:0] */ 1751#define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT 0 1752/* width of bitfield lso_tcp_flag_last[b:0] */ 1753#define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH 12 1754/* default value of bitfield lso_tcp_flag_last[b:0] */ 1755#define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT 0x0 1756 1757/* tx lso_tcp_flag_mid[b:0] bitfield definitions 1758 * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]". 1759 * port="pif_thm_lso_tcp_flag_mid_i[11:0]" 1760 */ 1761 1762/* Register address for bitfield lro_rsc_max[1F:0] */ 1763#define HW_ATL_RPO_LRO_RSC_MAX_ADR 0x00005598 1764/* Bitmask for bitfield lro_rsc_max[1F:0] */ 1765#define HW_ATL_RPO_LRO_RSC_MAX_MSK 0xFFFFFFFF 1766/* Inverted bitmask for bitfield lro_rsc_max[1F:0] */ 1767#define HW_ATL_RPO_LRO_RSC_MAX_MSKN 0x00000000 1768/* Lower bit position of bitfield lro_rsc_max[1F:0] */ 1769#define HW_ATL_RPO_LRO_RSC_MAX_SHIFT 0 1770/* Width of bitfield lro_rsc_max[1F:0] */ 1771#define HW_ATL_RPO_LRO_RSC_MAX_WIDTH 32 1772/* Default value of bitfield lro_rsc_max[1F:0] */ 1773#define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT 0x0 1774 1775/* RX lro_en[1F:0] Bitfield Definitions 1776 * Preprocessor definitions for the bitfield "lro_en[1F:0]". 1777 * PORT="pif_rpo_lro_en_i[31:0]" 1778 */ 1779 1780/* Register address for bitfield lro_en[1F:0] */ 1781#define HW_ATL_RPO_LRO_EN_ADR 0x00005590 1782/* Bitmask for bitfield lro_en[1F:0] */ 1783#define HW_ATL_RPO_LRO_EN_MSK 0xFFFFFFFF 1784/* Inverted bitmask for bitfield lro_en[1F:0] */ 1785#define HW_ATL_RPO_LRO_EN_MSKN 0x00000000 1786/* Lower bit position of bitfield lro_en[1F:0] */ 1787#define HW_ATL_RPO_LRO_EN_SHIFT 0 1788/* Width of bitfield lro_en[1F:0] */ 1789#define HW_ATL_RPO_LRO_EN_WIDTH 32 1790/* Default value of bitfield lro_en[1F:0] */ 1791#define HW_ATL_RPO_LRO_EN_DEFAULT 0x0 1792 1793/* RX lro_ptopt_en Bitfield Definitions 1794 * Preprocessor definitions for the bitfield "lro_ptopt_en". 1795 * PORT="pif_rpo_lro_ptopt_en_i" 1796 */ 1797 1798/* Register address for bitfield lro_ptopt_en */ 1799#define HW_ATL_RPO_LRO_PTOPT_EN_ADR 0x00005594 1800/* Bitmask for bitfield lro_ptopt_en */ 1801#define HW_ATL_RPO_LRO_PTOPT_EN_MSK 0x00008000 1802/* Inverted bitmask for bitfield lro_ptopt_en */ 1803#define HW_ATL_RPO_LRO_PTOPT_EN_MSKN 0xFFFF7FFF 1804/* Lower bit position of bitfield lro_ptopt_en */ 1805#define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT 15 1806/* Width of bitfield lro_ptopt_en */ 1807#define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH 1 1808/* Default value of bitfield lro_ptopt_en */ 1809#define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT 0x1 1810 1811/* RX lro_q_ses_lmt Bitfield Definitions 1812 * Preprocessor definitions for the bitfield "lro_q_ses_lmt". 1813 * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]" 1814 */ 1815 1816/* Register address for bitfield lro_q_ses_lmt */ 1817#define HW_ATL_RPO_LRO_QSES_LMT_ADR 0x00005594 1818/* Bitmask for bitfield lro_q_ses_lmt */ 1819#define HW_ATL_RPO_LRO_QSES_LMT_MSK 0x00003000 1820/* Inverted bitmask for bitfield lro_q_ses_lmt */ 1821#define HW_ATL_RPO_LRO_QSES_LMT_MSKN 0xFFFFCFFF 1822/* Lower bit position of bitfield lro_q_ses_lmt */ 1823#define HW_ATL_RPO_LRO_QSES_LMT_SHIFT 12 1824/* Width of bitfield lro_q_ses_lmt */ 1825#define HW_ATL_RPO_LRO_QSES_LMT_WIDTH 2 1826/* Default value of bitfield lro_q_ses_lmt */ 1827#define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT 0x1 1828 1829/* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions 1830 * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]". 1831 * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]" 1832 */ 1833 1834/* Register address for bitfield lro_tot_dsc_lmt[1:0] */ 1835#define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR 0x00005594 1836/* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1837#define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK 0x00000060 1838/* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1839#define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN 0xFFFFFF9F 1840/* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */ 1841#define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT 5 1842/* Width of bitfield lro_tot_dsc_lmt[1:0] */ 1843#define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH 2 1844/* Default value of bitfield lro_tot_dsc_lmt[1:0] */ 1845#define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT 0x1 1846 1847/* RX lro_pkt_min[4:0] Bitfield Definitions 1848 * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]". 1849 * PORT="pif_rpo_lro_pkt_min_i[4:0]" 1850 */ 1851 1852/* Register address for bitfield lro_pkt_min[4:0] */ 1853#define HW_ATL_RPO_LRO_PKT_MIN_ADR 0x00005594 1854/* Bitmask for bitfield lro_pkt_min[4:0] */ 1855#define HW_ATL_RPO_LRO_PKT_MIN_MSK 0x0000001F 1856/* Inverted bitmask for bitfield lro_pkt_min[4:0] */ 1857#define HW_ATL_RPO_LRO_PKT_MIN_MSKN 0xFFFFFFE0 1858/* Lower bit position of bitfield lro_pkt_min[4:0] */ 1859#define HW_ATL_RPO_LRO_PKT_MIN_SHIFT 0 1860/* Width of bitfield lro_pkt_min[4:0] */ 1861#define HW_ATL_RPO_LRO_PKT_MIN_WIDTH 5 1862/* Default value of bitfield lro_pkt_min[4:0] */ 1863#define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT 0x8 1864 1865/* Width of bitfield lro{L}_des_max[1:0] */ 1866#define HW_ATL_RPO_LRO_LDES_MAX_WIDTH 2 1867/* Default value of bitfield lro{L}_des_max[1:0] */ 1868#define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT 0x0 1869 1870/* RX lro_tb_div[11:0] Bitfield Definitions 1871 * Preprocessor definitions for the bitfield "lro_tb_div[11:0]". 1872 * PORT="pif_rpo_lro_tb_div_i[11:0]" 1873 */ 1874 1875/* Register address for bitfield lro_tb_div[11:0] */ 1876#define HW_ATL_RPO_LRO_TB_DIV_ADR 0x00005620 1877/* Bitmask for bitfield lro_tb_div[11:0] */ 1878#define HW_ATL_RPO_LRO_TB_DIV_MSK 0xFFF00000 1879/* Inverted bitmask for bitfield lro_tb_div[11:0] */ 1880#define HW_ATL_RPO_LRO_TB_DIV_MSKN 0x000FFFFF 1881/* Lower bit position of bitfield lro_tb_div[11:0] */ 1882#define HW_ATL_RPO_LRO_TB_DIV_SHIFT 20 1883/* Width of bitfield lro_tb_div[11:0] */ 1884#define HW_ATL_RPO_LRO_TB_DIV_WIDTH 12 1885/* Default value of bitfield lro_tb_div[11:0] */ 1886#define HW_ATL_RPO_LRO_TB_DIV_DEFAULT 0xC35 1887 1888/* RX lro_ina_ival[9:0] Bitfield Definitions 1889 * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]". 1890 * PORT="pif_rpo_lro_ina_ival_i[9:0]" 1891 */ 1892 1893/* Register address for bitfield lro_ina_ival[9:0] */ 1894#define HW_ATL_RPO_LRO_INA_IVAL_ADR 0x00005620 1895/* Bitmask for bitfield lro_ina_ival[9:0] */ 1896#define HW_ATL_RPO_LRO_INA_IVAL_MSK 0x000FFC00 1897/* Inverted bitmask for bitfield lro_ina_ival[9:0] */ 1898#define HW_ATL_RPO_LRO_INA_IVAL_MSKN 0xFFF003FF 1899/* Lower bit position of bitfield lro_ina_ival[9:0] */ 1900#define HW_ATL_RPO_LRO_INA_IVAL_SHIFT 10 1901/* Width of bitfield lro_ina_ival[9:0] */ 1902#define HW_ATL_RPO_LRO_INA_IVAL_WIDTH 10 1903/* Default value of bitfield lro_ina_ival[9:0] */ 1904#define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT 0xA 1905 1906/* RX lro_max_ival[9:0] Bitfield Definitions 1907 * Preprocessor definitions for the bitfield "lro_max_ival[9:0]". 1908 * PORT="pif_rpo_lro_max_ival_i[9:0]" 1909 */ 1910 1911/* Register address for bitfield lro_max_ival[9:0] */ 1912#define HW_ATL_RPO_LRO_MAX_IVAL_ADR 0x00005620 1913/* Bitmask for bitfield lro_max_ival[9:0] */ 1914#define HW_ATL_RPO_LRO_MAX_IVAL_MSK 0x000003FF 1915/* Inverted bitmask for bitfield lro_max_ival[9:0] */ 1916#define HW_ATL_RPO_LRO_MAX_IVAL_MSKN 0xFFFFFC00 1917/* Lower bit position of bitfield lro_max_ival[9:0] */ 1918#define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT 0 1919/* Width of bitfield lro_max_ival[9:0] */ 1920#define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH 10 1921/* Default value of bitfield lro_max_ival[9:0] */ 1922#define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT 0x19 1923 1924/* TX dca{D}_cpuid[7:0] Bitfield Definitions 1925 * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]". 1926 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1927 * PORT="pif_tdm_dca0_cpuid_i[7:0]" 1928 */ 1929 1930/* Register address for bitfield dca{D}_cpuid[7:0] */ 1931#define HW_ATL_TDM_DCA_DCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) 1932/* Bitmask for bitfield dca{D}_cpuid[7:0] */ 1933#define HW_ATL_TDM_DCA_DCPUID_MSK 0x000000FF 1934/* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */ 1935#define HW_ATL_TDM_DCA_DCPUID_MSKN 0xFFFFFF00 1936/* Lower bit position of bitfield dca{D}_cpuid[7:0] */ 1937#define HW_ATL_TDM_DCA_DCPUID_SHIFT 0 1938/* Width of bitfield dca{D}_cpuid[7:0] */ 1939#define HW_ATL_TDM_DCA_DCPUID_WIDTH 8 1940/* Default value of bitfield dca{D}_cpuid[7:0] */ 1941#define HW_ATL_TDM_DCA_DCPUID_DEFAULT 0x0 1942 1943/* TX dca{D}_desc_en Bitfield Definitions 1944 * Preprocessor definitions for the bitfield "dca{D}_desc_en". 1945 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1946 * PORT="pif_tdm_dca_desc_en_i[0]" 1947 */ 1948 1949/* Register address for bitfield dca{D}_desc_en */ 1950#define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) 1951/* Bitmask for bitfield dca{D}_desc_en */ 1952#define HW_ATL_TDM_DCA_DDESC_EN_MSK 0x80000000 1953/* Inverted bitmask for bitfield dca{D}_desc_en */ 1954#define HW_ATL_TDM_DCA_DDESC_EN_MSKN 0x7FFFFFFF 1955/* Lower bit position of bitfield dca{D}_desc_en */ 1956#define HW_ATL_TDM_DCA_DDESC_EN_SHIFT 31 1957/* Width of bitfield dca{D}_desc_en */ 1958#define HW_ATL_TDM_DCA_DDESC_EN_WIDTH 1 1959/* Default value of bitfield dca{D}_desc_en */ 1960#define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT 0x0 1961 1962/* TX desc{D}_en Bitfield Definitions 1963 * Preprocessor definitions for the bitfield "desc{D}_en". 1964 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1965 * PORT="pif_tdm_desc_en_i[0]" 1966 */ 1967 1968/* Register address for bitfield desc{D}_en */ 1969#define HW_ATL_TDM_DESC_DEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) 1970/* Bitmask for bitfield desc{D}_en */ 1971#define HW_ATL_TDM_DESC_DEN_MSK 0x80000000 1972/* Inverted bitmask for bitfield desc{D}_en */ 1973#define HW_ATL_TDM_DESC_DEN_MSKN 0x7FFFFFFF 1974/* Lower bit position of bitfield desc{D}_en */ 1975#define HW_ATL_TDM_DESC_DEN_SHIFT 31 1976/* Width of bitfield desc{D}_en */ 1977#define HW_ATL_TDM_DESC_DEN_WIDTH 1 1978/* Default value of bitfield desc{D}_en */ 1979#define HW_ATL_TDM_DESC_DEN_DEFAULT 0x0 1980 1981/* TX desc{D}_hd[C:0] Bitfield Definitions 1982 * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]". 1983 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1984 * PORT="tdm_pif_desc0_hd_o[12:0]" 1985 */ 1986 1987/* Register address for bitfield desc{D}_hd[C:0] */ 1988#define HW_ATL_TDM_DESC_DHD_ADR(descriptor) (0x00007C0C + (descriptor) * 0x40) 1989/* Bitmask for bitfield desc{D}_hd[C:0] */ 1990#define HW_ATL_TDM_DESC_DHD_MSK 0x00001FFF 1991/* Inverted bitmask for bitfield desc{D}_hd[C:0] */ 1992#define HW_ATL_TDM_DESC_DHD_MSKN 0xFFFFE000 1993/* Lower bit position of bitfield desc{D}_hd[C:0] */ 1994#define HW_ATL_TDM_DESC_DHD_SHIFT 0 1995/* Width of bitfield desc{D}_hd[C:0] */ 1996#define HW_ATL_TDM_DESC_DHD_WIDTH 13 1997 1998/* TX desc{D}_len[9:0] Bitfield Definitions 1999 * Preprocessor definitions for the bitfield "desc{D}_len[9:0]". 2000 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 2001 * PORT="pif_tdm_desc0_len_i[9:0]" 2002 */ 2003 2004/* Register address for bitfield desc{D}_len[9:0] */ 2005#define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) 2006/* Bitmask for bitfield desc{D}_len[9:0] */ 2007#define HW_ATL_TDM_DESC_DLEN_MSK 0x00001FF8 2008/* Inverted bitmask for bitfield desc{D}_len[9:0] */ 2009#define HW_ATL_TDM_DESC_DLEN_MSKN 0xFFFFE007 2010/* Lower bit position of bitfield desc{D}_len[9:0] */ 2011#define HW_ATL_TDM_DESC_DLEN_SHIFT 3 2012/* Width of bitfield desc{D}_len[9:0] */ 2013#define HW_ATL_TDM_DESC_DLEN_WIDTH 10 2014/* Default value of bitfield desc{D}_len[9:0] */ 2015#define HW_ATL_TDM_DESC_DLEN_DEFAULT 0x0 2016 2017/* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions 2018 * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]". 2019 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 2020 * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]" 2021 */ 2022 2023/* Register address for bitfield desc{D}_wrb_thresh[6:0] */ 2024#define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) \ 2025 (0x00007C18 + (descriptor) * 0x40) 2026/* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 2027#define HW_ATL_TDM_DESC_DWRB_THRESH_MSK 0x00007F00 2028/* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 2029#define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN 0xFFFF80FF 2030/* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */ 2031#define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT 8 2032/* Width of bitfield desc{D}_wrb_thresh[6:0] */ 2033#define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH 7 2034/* Default value of bitfield desc{D}_wrb_thresh[6:0] */ 2035#define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT 0x0 2036 2037/* TX tdm_int_mod_en Bitfield Definitions 2038 * Preprocessor definitions for the bitfield "tdm_int_mod_en". 2039 * PORT="pif_tdm_int_mod_en_i" 2040 */ 2041 2042/* Register address for bitfield tdm_int_mod_en */ 2043#define HW_ATL_TDM_INT_MOD_EN_ADR 0x00007B40 2044/* Bitmask for bitfield tdm_int_mod_en */ 2045#define HW_ATL_TDM_INT_MOD_EN_MSK 0x00000010 2046/* Inverted bitmask for bitfield tdm_int_mod_en */ 2047#define HW_ATL_TDM_INT_MOD_EN_MSKN 0xFFFFFFEF 2048/* Lower bit position of bitfield tdm_int_mod_en */ 2049#define HW_ATL_TDM_INT_MOD_EN_SHIFT 4 2050/* Width of bitfield tdm_int_mod_en */ 2051#define HW_ATL_TDM_INT_MOD_EN_WIDTH 1 2052/* Default value of bitfield tdm_int_mod_en */ 2053#define HW_ATL_TDM_INT_MOD_EN_DEFAULT 0x0 2054 2055/* TX lso_tcp_flag_mid[B:0] Bitfield Definitions 2056 * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]". 2057 * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]" 2058 */ 2059/* register address for bitfield lso_tcp_flag_mid[b:0] */ 2060#define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR 0x00007820 2061/* bitmask for bitfield lso_tcp_flag_mid[b:0] */ 2062#define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK 0x0fff0000 2063/* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */ 2064#define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN 0xf000ffff 2065/* lower bit position of bitfield lso_tcp_flag_mid[b:0] */ 2066#define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT 16 2067/* width of bitfield lso_tcp_flag_mid[b:0] */ 2068#define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH 12 2069/* default value of bitfield lso_tcp_flag_mid[b:0] */ 2070#define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0 2071 2072/* tx tx_tc_mode bitfield definitions 2073 * preprocessor definitions for the bitfield "tx_tc_mode". 2074 * port="pif_tpb_tx_tc_mode_i,pif_tps_tx_tc_mode_i" 2075 */ 2076 2077/* register address for bitfield tx_tc_mode */ 2078#define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900 2079/* bitmask for bitfield tx_tc_mode */ 2080#define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100 2081/* inverted bitmask for bitfield tx_tc_mode */ 2082#define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF 2083/* lower bit position of bitfield tx_tc_mode */ 2084#define HW_ATL_TPB_TX_TC_MODE_SHIFT 8 2085/* width of bitfield tx_tc_mode */ 2086#define HW_ATL_TPB_TX_TC_MODE_WIDTH 1 2087/* default value of bitfield tx_tc_mode */ 2088#define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0 2089 2090/* tx tx_desc_rate_mode bitfield definitions 2091 * preprocessor definitions for the bitfield "tx_desc_rate_mode". 2092 * port="pif_tps_desc_rate_mode_i" 2093 */ 2094 2095/* register address for bitfield tx_desc_rate_mode */ 2096#define HW_ATL_TPS_TX_DESC_RATE_MODE_ADR 0x00007900 2097/* bitmask for bitfield tx_desc_rate_mode */ 2098#define HW_ATL_TPS_TX_DESC_RATE_MODE_MSK 0x00000080 2099/* inverted bitmask for bitfield tx_desc_rate_mode */ 2100#define HW_ATL_TPS_TX_DESC_RATE_MODE_MSKN 0xFFFFFF7F 2101/* lower bit position of bitfield tx_desc_rate_mode */ 2102#define HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT 7 2103/* width of bitfield tx_desc_rate_mode */ 2104#define HW_ATL_TPS_TX_DESC_RATE_MODE_WIDTH 1 2105/* default value of bitfield tx_desc_rate_mode */ 2106#define HW_ATL_TPS_TX_DESC_RATE_MODE_DEFAULT 0x0 2107 2108/* tx tx_buf_en bitfield definitions 2109 * preprocessor definitions for the bitfield "tx_buf_en". 2110 * port="pif_tpb_tx_buf_en_i" 2111 */ 2112 2113/* register address for bitfield tx_buf_en */ 2114#define HW_ATL_TPB_TX_BUF_EN_ADR 0x00007900 2115/* bitmask for bitfield tx_buf_en */ 2116#define HW_ATL_TPB_TX_BUF_EN_MSK 0x00000001 2117/* inverted bitmask for bitfield tx_buf_en */ 2118#define HW_ATL_TPB_TX_BUF_EN_MSKN 0xfffffffe 2119/* lower bit position of bitfield tx_buf_en */ 2120#define HW_ATL_TPB_TX_BUF_EN_SHIFT 0 2121/* width of bitfield tx_buf_en */ 2122#define HW_ATL_TPB_TX_BUF_EN_WIDTH 1 2123/* default value of bitfield tx_buf_en */ 2124#define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0 2125 2126/* tx tx{b}_hi_thresh[c:0] bitfield definitions 2127 * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". 2128 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 2129 * port="pif_tpb_tx0_hi_thresh_i[12:0]" 2130 */ 2131 2132/* register address for bitfield tx{b}_hi_thresh[c:0] */ 2133#define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) 2134/* bitmask for bitfield tx{b}_hi_thresh[c:0] */ 2135#define HW_ATL_TPB_TXBHI_THRESH_MSK 0x1fff0000 2136/* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */ 2137#define HW_ATL_TPB_TXBHI_THRESH_MSKN 0xe000ffff 2138/* lower bit position of bitfield tx{b}_hi_thresh[c:0] */ 2139#define HW_ATL_TPB_TXBHI_THRESH_SHIFT 16 2140/* width of bitfield tx{b}_hi_thresh[c:0] */ 2141#define HW_ATL_TPB_TXBHI_THRESH_WIDTH 13 2142/* default value of bitfield tx{b}_hi_thresh[c:0] */ 2143#define HW_ATL_TPB_TXBHI_THRESH_DEFAULT 0x0 2144 2145/* tx tx{b}_lo_thresh[c:0] bitfield definitions 2146 * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]". 2147 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 2148 * port="pif_tpb_tx0_lo_thresh_i[12:0]" 2149 */ 2150 2151/* register address for bitfield tx{b}_lo_thresh[c:0] */ 2152#define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) 2153/* bitmask for bitfield tx{b}_lo_thresh[c:0] */ 2154#define HW_ATL_TPB_TXBLO_THRESH_MSK 0x00001fff 2155/* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */ 2156#define HW_ATL_TPB_TXBLO_THRESH_MSKN 0xffffe000 2157/* lower bit position of bitfield tx{b}_lo_thresh[c:0] */ 2158#define HW_ATL_TPB_TXBLO_THRESH_SHIFT 0 2159/* width of bitfield tx{b}_lo_thresh[c:0] */ 2160#define HW_ATL_TPB_TXBLO_THRESH_WIDTH 13 2161/* default value of bitfield tx{b}_lo_thresh[c:0] */ 2162#define HW_ATL_TPB_TXBLO_THRESH_DEFAULT 0x0 2163 2164/* tx dma_sys_loopback bitfield definitions 2165 * preprocessor definitions for the bitfield "dma_sys_loopback". 2166 * port="pif_tpb_dma_sys_lbk_i" 2167 */ 2168 2169/* register address for bitfield dma_sys_loopback */ 2170#define HW_ATL_TPB_DMA_SYS_LBK_ADR 0x00007000 2171/* bitmask for bitfield dma_sys_loopback */ 2172#define HW_ATL_TPB_DMA_SYS_LBK_MSK 0x00000040 2173/* inverted bitmask for bitfield dma_sys_loopback */ 2174#define HW_ATL_TPB_DMA_SYS_LBK_MSKN 0xffffffbf 2175/* lower bit position of bitfield dma_sys_loopback */ 2176#define HW_ATL_TPB_DMA_SYS_LBK_SHIFT 6 2177/* width of bitfield dma_sys_loopback */ 2178#define HW_ATL_TPB_DMA_SYS_LBK_WIDTH 1 2179/* default value of bitfield dma_sys_loopback */ 2180#define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0 2181 2182/* tx dma_net_loopback bitfield definitions 2183 * preprocessor definitions for the bitfield "dma_net_loopback". 2184 * port="pif_tpb_dma_net_lbk_i" 2185 */ 2186 2187/* register address for bitfield dma_net_loopback */ 2188#define HW_ATL_TPB_DMA_NET_LBK_ADR 0x00007000 2189/* bitmask for bitfield dma_net_loopback */ 2190#define HW_ATL_TPB_DMA_NET_LBK_MSK 0x00000010 2191/* inverted bitmask for bitfield dma_net_loopback */ 2192#define HW_ATL_TPB_DMA_NET_LBK_MSKN 0xffffffef 2193/* lower bit position of bitfield dma_net_loopback */ 2194#define HW_ATL_TPB_DMA_NET_LBK_SHIFT 4 2195/* width of bitfield dma_net_loopback */ 2196#define HW_ATL_TPB_DMA_NET_LBK_WIDTH 1 2197/* default value of bitfield dma_net_loopback */ 2198#define HW_ATL_TPB_DMA_NET_LBK_DEFAULT 0x0 2199 2200/* tx tx{b}_buf_size[7:0] bitfield definitions 2201 * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]". 2202 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 2203 * port="pif_tpb_tx0_buf_size_i[7:0]" 2204 */ 2205 2206/* register address for bitfield tx{b}_buf_size[7:0] */ 2207#define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) (0x00007910 + (buffer) * 0x10) 2208/* bitmask for bitfield tx{b}_buf_size[7:0] */ 2209#define HW_ATL_TPB_TXBBUF_SIZE_MSK 0x000000ff 2210/* inverted bitmask for bitfield tx{b}_buf_size[7:0] */ 2211#define HW_ATL_TPB_TXBBUF_SIZE_MSKN 0xffffff00 2212/* lower bit position of bitfield tx{b}_buf_size[7:0] */ 2213#define HW_ATL_TPB_TXBBUF_SIZE_SHIFT 0 2214/* width of bitfield tx{b}_buf_size[7:0] */ 2215#define HW_ATL_TPB_TXBBUF_SIZE_WIDTH 8 2216/* default value of bitfield tx{b}_buf_size[7:0] */ 2217#define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT 0x0 2218 2219/* tx tx_scp_ins_en bitfield definitions 2220 * preprocessor definitions for the bitfield "tx_scp_ins_en". 2221 * port="pif_tpb_scp_ins_en_i" 2222 */ 2223 2224/* register address for bitfield tx_scp_ins_en */ 2225#define HW_ATL_TPB_TX_SCP_INS_EN_ADR 0x00007900 2226/* bitmask for bitfield tx_scp_ins_en */ 2227#define HW_ATL_TPB_TX_SCP_INS_EN_MSK 0x00000004 2228/* inverted bitmask for bitfield tx_scp_ins_en */ 2229#define HW_ATL_TPB_TX_SCP_INS_EN_MSKN 0xfffffffb 2230/* lower bit position of bitfield tx_scp_ins_en */ 2231#define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT 2 2232/* width of bitfield tx_scp_ins_en */ 2233#define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1 2234/* default value of bitfield tx_scp_ins_en */ 2235#define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0 2236 2237/* tx tx_clk_gate_en bitfield definitions 2238 * preprocessor definitions for the bitfield "tx_clk_gate_en". 2239 * port="pif_tpb_clk_gate_en_i" 2240 */ 2241 2242/* register address for bitfield tx_clk_gate_en */ 2243#define HW_ATL_TPB_TX_CLK_GATE_EN_ADR 0x00007900 2244/* bitmask for bitfield tx_clk_gate_en */ 2245#define HW_ATL_TPB_TX_CLK_GATE_EN_MSK 0x00000010 2246/* inverted bitmask for bitfield tx_clk_gate_en */ 2247#define HW_ATL_TPB_TX_CLK_GATE_EN_MSKN 0xffffffef 2248/* lower bit position of bitfield tx_clk_gate_en */ 2249#define HW_ATL_TPB_TX_CLK_GATE_EN_SHIFT 4 2250/* width of bitfield tx_clk_gate_en */ 2251#define HW_ATL_TPB_TX_CLK_GATE_EN_WIDTH 1 2252/* default value of bitfield tx_clk_gate_en */ 2253#define HW_ATL_TPB_TX_CLK_GATE_EN_DEFAULT 0x1 2254 2255/* tx ipv4_chk_en bitfield definitions 2256 * preprocessor definitions for the bitfield "ipv4_chk_en". 2257 * port="pif_tpo_ipv4_chk_en_i" 2258 */ 2259 2260/* register address for bitfield ipv4_chk_en */ 2261#define HW_ATL_TPO_IPV4CHK_EN_ADR 0x00007800 2262/* bitmask for bitfield ipv4_chk_en */ 2263#define HW_ATL_TPO_IPV4CHK_EN_MSK 0x00000002 2264/* inverted bitmask for bitfield ipv4_chk_en */ 2265#define HW_ATL_TPO_IPV4CHK_EN_MSKN 0xfffffffd 2266/* lower bit position of bitfield ipv4_chk_en */ 2267#define HW_ATL_TPO_IPV4CHK_EN_SHIFT 1 2268/* width of bitfield ipv4_chk_en */ 2269#define HW_ATL_TPO_IPV4CHK_EN_WIDTH 1 2270/* default value of bitfield ipv4_chk_en */ 2271#define HW_ATL_TPO_IPV4CHK_EN_DEFAULT 0x0 2272 2273/* tx l4_chk_en bitfield definitions 2274 * preprocessor definitions for the bitfield "l4_chk_en". 2275 * port="pif_tpo_l4_chk_en_i" 2276 */ 2277 2278/* register address for bitfield l4_chk_en */ 2279#define HW_ATL_TPOL4CHK_EN_ADR 0x00007800 2280/* bitmask for bitfield l4_chk_en */ 2281#define HW_ATL_TPOL4CHK_EN_MSK 0x00000001 2282/* inverted bitmask for bitfield l4_chk_en */ 2283#define HW_ATL_TPOL4CHK_EN_MSKN 0xfffffffe 2284/* lower bit position of bitfield l4_chk_en */ 2285#define HW_ATL_TPOL4CHK_EN_SHIFT 0 2286/* width of bitfield l4_chk_en */ 2287#define HW_ATL_TPOL4CHK_EN_WIDTH 1 2288/* default value of bitfield l4_chk_en */ 2289#define HW_ATL_TPOL4CHK_EN_DEFAULT 0x0 2290 2291/* tx pkt_sys_loopback bitfield definitions 2292 * preprocessor definitions for the bitfield "pkt_sys_loopback". 2293 * port="pif_tpo_pkt_sys_lbk_i" 2294 */ 2295 2296/* register address for bitfield pkt_sys_loopback */ 2297#define HW_ATL_TPO_PKT_SYS_LBK_ADR 0x00007000 2298/* bitmask for bitfield pkt_sys_loopback */ 2299#define HW_ATL_TPO_PKT_SYS_LBK_MSK 0x00000080 2300/* inverted bitmask for bitfield pkt_sys_loopback */ 2301#define HW_ATL_TPO_PKT_SYS_LBK_MSKN 0xffffff7f 2302/* lower bit position of bitfield pkt_sys_loopback */ 2303#define HW_ATL_TPO_PKT_SYS_LBK_SHIFT 7 2304/* width of bitfield pkt_sys_loopback */ 2305#define HW_ATL_TPO_PKT_SYS_LBK_WIDTH 1 2306/* default value of bitfield pkt_sys_loopback */ 2307#define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT 0x0 2308 2309/* tx data_tc_arb_mode bitfield definitions 2310 * preprocessor definitions for the bitfield "data_tc_arb_mode". 2311 * port="pif_tps_data_tc_arb_mode_i" 2312 */ 2313 2314/* register address for bitfield data_tc_arb_mode */ 2315#define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR 0x00007100 2316/* bitmask for bitfield data_tc_arb_mode */ 2317#define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK 0x00000001 2318/* inverted bitmask for bitfield data_tc_arb_mode */ 2319#define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffe 2320/* lower bit position of bitfield data_tc_arb_mode */ 2321#define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT 0 2322/* width of bitfield data_tc_arb_mode */ 2323#define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1 2324/* default value of bitfield data_tc_arb_mode */ 2325#define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0 2326 2327/* tx desc{r}_rate_en bitfield definitions 2328 * preprocessor definitions for the bitfield "desc{r}_rate_en". 2329 * port="pif_tps_desc_rate_en_i[0]" 2330 */ 2331 2332/* register address for bitfield desc{r}_rate_en */ 2333#define HW_ATL_TPS_DESC_RATE_EN_ADR(desc) (0x00007408 + (desc) * 0x10) 2334/* bitmask for bitfield desc{r}_rate_en */ 2335#define HW_ATL_TPS_DESC_RATE_EN_MSK 0x80000000 2336/* inverted bitmask for bitfield desc{r}_rate_en */ 2337#define HW_ATL_TPS_DESC_RATE_EN_MSKN 0x7FFFFFFF 2338/* lower bit position of bitfield desc{r}_rate_en */ 2339#define HW_ATL_TPS_DESC_RATE_EN_SHIFT 31 2340/* width of bitfield desc{r}_rate_en */ 2341#define HW_ATL_TPS_DESC_RATE_EN_WIDTH 1 2342/* default value of bitfield desc{r}_rate_en */ 2343#define HW_ATL_TPS_DESC_RATE_EN_DEFAULT 0x0 2344 2345/* tx desc{r}_rate_x bitfield definitions 2346 * preprocessor definitions for the bitfield "desc{r}_rate_x". 2347 * port="pif_tps_desc0_rate_x" 2348 */ 2349/* register address for bitfield desc{r}_rate_x */ 2350#define HW_ATL_TPS_DESC_RATE_X_ADR(desc) (0x00007408 + (desc) * 0x10) 2351/* bitmask for bitfield desc{r}_rate_x */ 2352#define HW_ATL_TPS_DESC_RATE_X_MSK 0x03FF0000 2353/* inverted bitmask for bitfield desc{r}_rate_x */ 2354#define HW_ATL_TPS_DESC_RATE_X_MSKN 0xFC00FFFF 2355/* lower bit position of bitfield desc{r}_rate_x */ 2356#define HW_ATL_TPS_DESC_RATE_X_SHIFT 16 2357/* width of bitfield desc{r}_rate_x */ 2358#define HW_ATL_TPS_DESC_RATE_X_WIDTH 10 2359/* default value of bitfield desc{r}_rate_x */ 2360#define HW_ATL_TPS_DESC_RATE_X_DEFAULT 0x0 2361 2362/* tx desc{r}_rate_y bitfield definitions 2363 * preprocessor definitions for the bitfield "desc{r}_rate_y". 2364 * port="pif_tps_desc0_rate_y" 2365 */ 2366/* register address for bitfield desc{r}_rate_y */ 2367#define HW_ATL_TPS_DESC_RATE_Y_ADR(desc) (0x00007408 + (desc) * 0x10) 2368/* bitmask for bitfield desc{r}_rate_y */ 2369#define HW_ATL_TPS_DESC_RATE_Y_MSK 0x00003FFF 2370/* inverted bitmask for bitfield desc{r}_rate_y */ 2371#define HW_ATL_TPS_DESC_RATE_Y_MSKN 0xFFFFC000 2372/* lower bit position of bitfield desc{r}_rate_y */ 2373#define HW_ATL_TPS_DESC_RATE_Y_SHIFT 0 2374/* width of bitfield desc{r}_rate_y */ 2375#define HW_ATL_TPS_DESC_RATE_Y_WIDTH 14 2376/* default value of bitfield desc{r}_rate_y */ 2377#define HW_ATL_TPS_DESC_RATE_Y_DEFAULT 0x0 2378 2379/* tx desc_rate_ta_rst bitfield definitions 2380 * preprocessor definitions for the bitfield "desc_rate_ta_rst". 2381 * port="pif_tps_desc_rate_ta_rst_i" 2382 */ 2383 2384/* register address for bitfield desc_rate_ta_rst */ 2385#define HW_ATL_TPS_DESC_RATE_TA_RST_ADR 0x00007310 2386/* bitmask for bitfield desc_rate_ta_rst */ 2387#define HW_ATL_TPS_DESC_RATE_TA_RST_MSK 0x80000000 2388/* inverted bitmask for bitfield desc_rate_ta_rst */ 2389#define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN 0x7fffffff 2390/* lower bit position of bitfield desc_rate_ta_rst */ 2391#define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT 31 2392/* width of bitfield desc_rate_ta_rst */ 2393#define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH 1 2394/* default value of bitfield desc_rate_ta_rst */ 2395#define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT 0x0 2396 2397/* tx desc_rate_limit[a:0] bitfield definitions 2398 * preprocessor definitions for the bitfield "desc_rate_limit[a:0]". 2399 * port="pif_tps_desc_rate_lim_i[10:0]" 2400 */ 2401 2402/* register address for bitfield desc_rate_limit[a:0] */ 2403#define HW_ATL_TPS_DESC_RATE_LIM_ADR 0x00007310 2404/* bitmask for bitfield desc_rate_limit[a:0] */ 2405#define HW_ATL_TPS_DESC_RATE_LIM_MSK 0x000007ff 2406/* inverted bitmask for bitfield desc_rate_limit[a:0] */ 2407#define HW_ATL_TPS_DESC_RATE_LIM_MSKN 0xfffff800 2408/* lower bit position of bitfield desc_rate_limit[a:0] */ 2409#define HW_ATL_TPS_DESC_RATE_LIM_SHIFT 0 2410/* width of bitfield desc_rate_limit[a:0] */ 2411#define HW_ATL_TPS_DESC_RATE_LIM_WIDTH 11 2412/* default value of bitfield desc_rate_limit[a:0] */ 2413#define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT 0x0 2414 2415/* tx desc_tc_arb_mode[1:0] bitfield definitions 2416 * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]". 2417 * port="pif_tps_desc_tc_arb_mode_i[1:0]" 2418 */ 2419 2420/* register address for bitfield desc_tc_arb_mode[1:0] */ 2421#define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR 0x00007200 2422/* bitmask for bitfield desc_tc_arb_mode[1:0] */ 2423#define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK 0x00000003 2424/* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */ 2425#define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN 0xfffffffc 2426/* lower bit position of bitfield desc_tc_arb_mode[1:0] */ 2427#define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT 0 2428/* width of bitfield desc_tc_arb_mode[1:0] */ 2429#define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH 2 2430/* default value of bitfield desc_tc_arb_mode[1:0] */ 2431#define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT 0x0 2432 2433/* tx desc_tc{t}_credit_max[b:0] bitfield definitions 2434 * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]". 2435 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2436 * port="pif_tps_desc_tc0_credit_max_i[11:0]" 2437 */ 2438 2439/* register address for bitfield desc_tc{t}_credit_max[b:0] */ 2440#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) (0x00007210 + (tc) * 0x4) 2441/* bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2442#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK 0x0fff0000 2443/* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2444#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN 0xf000ffff 2445/* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */ 2446#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT 16 2447/* width of bitfield desc_tc{t}_credit_max[b:0] */ 2448#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH 12 2449/* default value of bitfield desc_tc{t}_credit_max[b:0] */ 2450#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT 0x0 2451 2452/* tx desc_tc{t}_weight[8:0] bitfield definitions 2453 * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]". 2454 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2455 * port="pif_tps_desc_tc0_weight_i[8:0]" 2456 */ 2457 2458/* register address for bitfield desc_tc{t}_weight[8:0] */ 2459#define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) (0x00007210 + (tc) * 0x4) 2460/* bitmask for bitfield desc_tc{t}_weight[8:0] */ 2461#define HW_ATL_TPS_DESC_TCTWEIGHT_MSK 0x000001ff 2462/* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */ 2463#define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN 0xfffffe00 2464/* lower bit position of bitfield desc_tc{t}_weight[8:0] */ 2465#define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT 0 2466/* width of bitfield desc_tc{t}_weight[8:0] */ 2467#define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH 9 2468/* default value of bitfield desc_tc{t}_weight[8:0] */ 2469#define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT 0x0 2470 2471/* tx desc_vm_arb_mode bitfield definitions 2472 * preprocessor definitions for the bitfield "desc_vm_arb_mode". 2473 * port="pif_tps_desc_vm_arb_mode_i" 2474 */ 2475 2476/* register address for bitfield desc_vm_arb_mode */ 2477#define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR 0x00007300 2478/* bitmask for bitfield desc_vm_arb_mode */ 2479#define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK 0x00000001 2480/* inverted bitmask for bitfield desc_vm_arb_mode */ 2481#define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN 0xfffffffe 2482/* lower bit position of bitfield desc_vm_arb_mode */ 2483#define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT 0 2484/* width of bitfield desc_vm_arb_mode */ 2485#define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH 1 2486/* default value of bitfield desc_vm_arb_mode */ 2487#define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT 0x0 2488 2489/* tx data_tc{t}_credit_max[b:0] bitfield definitions 2490 * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]". 2491 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2492 * port="pif_tps_data_tc0_credit_max_i[11:0]" 2493 */ 2494 2495/* register address for bitfield data_tc{t}_credit_max[b:0] */ 2496#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4) 2497/* bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2498#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000 2499/* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2500#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff 2501/* lower bit position of bitfield data_tc{t}_credit_max[b:0] */ 2502#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT 16 2503/* width of bitfield data_tc{t}_credit_max[b:0] */ 2504#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH 12 2505/* default value of bitfield data_tc{t}_credit_max[b:0] */ 2506#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0 2507 2508/* tx data_tc{t}_weight[8:0] bitfield definitions 2509 * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]". 2510 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2511 * port="pif_tps_data_tc0_weight_i[8:0]" 2512 */ 2513 2514/* register address for bitfield data_tc{t}_weight[8:0] */ 2515#define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4) 2516/* bitmask for bitfield data_tc{t}_weight[8:0] */ 2517#define HW_ATL_TPS_DATA_TCTWEIGHT_MSK 0x000001ff 2518/* inverted bitmask for bitfield data_tc{t}_weight[8:0] */ 2519#define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00 2520/* lower bit position of bitfield data_tc{t}_weight[8:0] */ 2521#define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT 0 2522/* width of bitfield data_tc{t}_weight[8:0] */ 2523#define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH 9 2524/* default value of bitfield data_tc{t}_weight[8:0] */ 2525#define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT 0x0 2526 2527/* tx reg_res_dsbl bitfield definitions 2528 * preprocessor definitions for the bitfield "reg_res_dsbl". 2529 * port="pif_tx_reg_res_dsbl_i" 2530 */ 2531 2532/* register address for bitfield reg_res_dsbl */ 2533#define HW_ATL_TX_REG_RES_DSBL_ADR 0x00007000 2534/* bitmask for bitfield reg_res_dsbl */ 2535#define HW_ATL_TX_REG_RES_DSBL_MSK 0x20000000 2536/* inverted bitmask for bitfield reg_res_dsbl */ 2537#define HW_ATL_TX_REG_RES_DSBL_MSKN 0xdfffffff 2538/* lower bit position of bitfield reg_res_dsbl */ 2539#define HW_ATL_TX_REG_RES_DSBL_SHIFT 29 2540/* width of bitfield reg_res_dsbl */ 2541#define HW_ATL_TX_REG_RES_DSBL_WIDTH 1 2542/* default value of bitfield reg_res_dsbl */ 2543#define HW_ATL_TX_REG_RES_DSBL_DEFAULT 0x1 2544 2545/* mac_phy register access busy bitfield definitions 2546 * preprocessor definitions for the bitfield "register access busy". 2547 * port="msm_pif_reg_busy_o" 2548 */ 2549 2550/* register address for bitfield register access busy */ 2551#define HW_ATL_MSM_REG_ACCESS_BUSY_ADR 0x00004400 2552/* bitmask for bitfield register access busy */ 2553#define HW_ATL_MSM_REG_ACCESS_BUSY_MSK 0x00001000 2554/* inverted bitmask for bitfield register access busy */ 2555#define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN 0xffffefff 2556/* lower bit position of bitfield register access busy */ 2557#define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT 12 2558/* width of bitfield register access busy */ 2559#define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH 1 2560 2561/* mac_phy msm register address[7:0] bitfield definitions 2562 * preprocessor definitions for the bitfield "msm register address[7:0]". 2563 * port="pif_msm_reg_addr_i[7:0]" 2564 */ 2565 2566/* register address for bitfield msm register address[7:0] */ 2567#define HW_ATL_MSM_REG_ADDR_ADR 0x00004400 2568/* bitmask for bitfield msm register address[7:0] */ 2569#define HW_ATL_MSM_REG_ADDR_MSK 0x000000ff 2570/* inverted bitmask for bitfield msm register address[7:0] */ 2571#define HW_ATL_MSM_REG_ADDR_MSKN 0xffffff00 2572/* lower bit position of bitfield msm register address[7:0] */ 2573#define HW_ATL_MSM_REG_ADDR_SHIFT 0 2574/* width of bitfield msm register address[7:0] */ 2575#define HW_ATL_MSM_REG_ADDR_WIDTH 8 2576/* default value of bitfield msm register address[7:0] */ 2577#define HW_ATL_MSM_REG_ADDR_DEFAULT 0x0 2578 2579/* mac_phy register read strobe bitfield definitions 2580 * preprocessor definitions for the bitfield "register read strobe". 2581 * port="pif_msm_reg_rden_i" 2582 */ 2583 2584/* register address for bitfield register read strobe */ 2585#define HW_ATL_MSM_REG_RD_STROBE_ADR 0x00004400 2586/* bitmask for bitfield register read strobe */ 2587#define HW_ATL_MSM_REG_RD_STROBE_MSK 0x00000200 2588/* inverted bitmask for bitfield register read strobe */ 2589#define HW_ATL_MSM_REG_RD_STROBE_MSKN 0xfffffdff 2590/* lower bit position of bitfield register read strobe */ 2591#define HW_ATL_MSM_REG_RD_STROBE_SHIFT 9 2592/* width of bitfield register read strobe */ 2593#define HW_ATL_MSM_REG_RD_STROBE_WIDTH 1 2594/* default value of bitfield register read strobe */ 2595#define HW_ATL_MSM_REG_RD_STROBE_DEFAULT 0x0 2596 2597/* mac_phy msm register read data[31:0] bitfield definitions 2598 * preprocessor definitions for the bitfield "msm register read data[31:0]". 2599 * port="msm_pif_reg_rd_data_o[31:0]" 2600 */ 2601 2602/* register address for bitfield msm register read data[31:0] */ 2603#define HW_ATL_MSM_REG_RD_DATA_ADR 0x00004408 2604/* bitmask for bitfield msm register read data[31:0] */ 2605#define HW_ATL_MSM_REG_RD_DATA_MSK 0xffffffff 2606/* inverted bitmask for bitfield msm register read data[31:0] */ 2607#define HW_ATL_MSM_REG_RD_DATA_MSKN 0x00000000 2608/* lower bit position of bitfield msm register read data[31:0] */ 2609#define HW_ATL_MSM_REG_RD_DATA_SHIFT 0 2610/* width of bitfield msm register read data[31:0] */ 2611#define HW_ATL_MSM_REG_RD_DATA_WIDTH 32 2612 2613/* mac_phy msm register write data[31:0] bitfield definitions 2614 * preprocessor definitions for the bitfield "msm register write data[31:0]". 2615 * port="pif_msm_reg_wr_data_i[31:0]" 2616 */ 2617 2618/* register address for bitfield msm register write data[31:0] */ 2619#define HW_ATL_MSM_REG_WR_DATA_ADR 0x00004404 2620/* bitmask for bitfield msm register write data[31:0] */ 2621#define HW_ATL_MSM_REG_WR_DATA_MSK 0xffffffff 2622/* inverted bitmask for bitfield msm register write data[31:0] */ 2623#define HW_ATL_MSM_REG_WR_DATA_MSKN 0x00000000 2624/* lower bit position of bitfield msm register write data[31:0] */ 2625#define HW_ATL_MSM_REG_WR_DATA_SHIFT 0 2626/* width of bitfield msm register write data[31:0] */ 2627#define HW_ATL_MSM_REG_WR_DATA_WIDTH 32 2628/* default value of bitfield msm register write data[31:0] */ 2629#define HW_ATL_MSM_REG_WR_DATA_DEFAULT 0x0 2630 2631/* mac_phy register write strobe bitfield definitions 2632 * preprocessor definitions for the bitfield "register write strobe". 2633 * port="pif_msm_reg_wren_i" 2634 */ 2635 2636/* register address for bitfield register write strobe */ 2637#define HW_ATL_MSM_REG_WR_STROBE_ADR 0x00004400 2638/* bitmask for bitfield register write strobe */ 2639#define HW_ATL_MSM_REG_WR_STROBE_MSK 0x00000100 2640/* inverted bitmask for bitfield register write strobe */ 2641#define HW_ATL_MSM_REG_WR_STROBE_MSKN 0xfffffeff 2642/* lower bit position of bitfield register write strobe */ 2643#define HW_ATL_MSM_REG_WR_STROBE_SHIFT 8 2644/* width of bitfield register write strobe */ 2645#define HW_ATL_MSM_REG_WR_STROBE_WIDTH 1 2646/* default value of bitfield register write strobe */ 2647#define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0 2648 2649/* register address for bitfield PTP Digital Clock Read Enable */ 2650#define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_ADR 0x00004628 2651/* bitmask for bitfield PTP Digital Clock Read Enable */ 2652#define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSK 0x00000010 2653/* inverted bitmask for bitfield PTP Digital Clock Read Enable */ 2654#define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSKN 0xFFFFFFEF 2655/* lower bit position of bitfield PTP Digital Clock Read Enable */ 2656#define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_SHIFT 4 2657/* width of bitfield PTP Digital Clock Read Enable */ 2658#define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_WIDTH 1 2659/* default value of bitfield PTP Digital Clock Read Enable */ 2660#define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_DEFAULT 0x0 2661 2662/* register address for ptp counter reading */ 2663#define HW_ATL_PCS_PTP_TS_VAL_ADDR(index) (0x00004900 + (index) * 0x4) 2664 2665/* mif soft reset bitfield definitions 2666 * preprocessor definitions for the bitfield "soft reset". 2667 * port="pif_glb_res_i" 2668 */ 2669 2670/* register address for bitfield soft reset */ 2671#define HW_ATL_GLB_SOFT_RES_ADR 0x00000000 2672/* bitmask for bitfield soft reset */ 2673#define HW_ATL_GLB_SOFT_RES_MSK 0x00008000 2674/* inverted bitmask for bitfield soft reset */ 2675#define HW_ATL_GLB_SOFT_RES_MSKN 0xffff7fff 2676/* lower bit position of bitfield soft reset */ 2677#define HW_ATL_GLB_SOFT_RES_SHIFT 15 2678/* width of bitfield soft reset */ 2679#define HW_ATL_GLB_SOFT_RES_WIDTH 1 2680/* default value of bitfield soft reset */ 2681#define HW_ATL_GLB_SOFT_RES_DEFAULT 0x0 2682 2683/* mif register reset disable bitfield definitions 2684 * preprocessor definitions for the bitfield "register reset disable". 2685 * port="pif_glb_reg_res_dsbl_i" 2686 */ 2687 2688/* register address for bitfield register reset disable */ 2689#define HW_ATL_GLB_REG_RES_DIS_ADR 0x00000000 2690/* bitmask for bitfield register reset disable */ 2691#define HW_ATL_GLB_REG_RES_DIS_MSK 0x00004000 2692/* inverted bitmask for bitfield register reset disable */ 2693#define HW_ATL_GLB_REG_RES_DIS_MSKN 0xffffbfff 2694/* lower bit position of bitfield register reset disable */ 2695#define HW_ATL_GLB_REG_RES_DIS_SHIFT 14 2696/* width of bitfield register reset disable */ 2697#define HW_ATL_GLB_REG_RES_DIS_WIDTH 1 2698/* default value of bitfield register reset disable */ 2699#define HW_ATL_GLB_REG_RES_DIS_DEFAULT 0x1 2700 2701/* tx dma debug control definitions */ 2702#define HW_ATL_TX_DMA_DEBUG_CTL_ADR 0x00008920u 2703 2704/* tx dma descriptor base address msw definitions */ 2705#define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ 2706 (0x00007c04u + (descriptor) * 0x40) 2707 2708/* tx dma total request limit */ 2709#define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20u 2710 2711/* tx interrupt moderation control register definitions 2712 * Preprocessor definitions for TX Interrupt Moderation Control Register 2713 * Base Address: 0x00008980 2714 * Parameter: queue {Q} | stride size 0x4 | range [0, 31] 2715 */ 2716 2717#define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) (0x00008980u + (queue) * 0x4) 2718 2719/* pcie reg_res_dsbl bitfield definitions 2720 * preprocessor definitions for the bitfield "reg_res_dsbl". 2721 * port="pif_pci_reg_res_dsbl_i" 2722 */ 2723 2724/* register address for bitfield reg_res_dsbl */ 2725#define HW_ATL_PCI_REG_RES_DSBL_ADR 0x00001000 2726/* bitmask for bitfield reg_res_dsbl */ 2727#define HW_ATL_PCI_REG_RES_DSBL_MSK 0x20000000 2728/* inverted bitmask for bitfield reg_res_dsbl */ 2729#define HW_ATL_PCI_REG_RES_DSBL_MSKN 0xdfffffff 2730/* lower bit position of bitfield reg_res_dsbl */ 2731#define HW_ATL_PCI_REG_RES_DSBL_SHIFT 29 2732/* width of bitfield reg_res_dsbl */ 2733#define HW_ATL_PCI_REG_RES_DSBL_WIDTH 1 2734/* default value of bitfield reg_res_dsbl */ 2735#define HW_ATL_PCI_REG_RES_DSBL_DEFAULT 0x1 2736 2737/* PCI core control register */ 2738#define HW_ATL_PCI_REG_CONTROL6_ADR 0x1014u 2739 2740/* global microprocessor scratch pad definitions */ 2741#define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) \ 2742 (0x00000300u + (scratch_scp) * 0x4) 2743 2744/* register address for bitfield uP Force Interrupt */ 2745#define HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR 0x00000404 2746/* bitmask for bitfield uP Force Interrupt */ 2747#define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK 0x00000002 2748/* inverted bitmask for bitfield uP Force Interrupt */ 2749#define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSKN 0xFFFFFFFD 2750/* lower bit position of bitfield uP Force Interrupt */ 2751#define HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT 1 2752/* width of bitfield uP Force Interrupt */ 2753#define HW_ATL_MCP_UP_FORCE_INTERRUPT_WIDTH 1 2754/* default value of bitfield uP Force Interrupt */ 2755#define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT 0x0 2756 2757/* Preprocessor definitions for Global MDIO Interfaces 2758 * Address: 0x00000280 + 0x4 * Number of interface 2759 */ 2760#define HW_ATL_GLB_MDIO_IFACE_ADDR_BEGIN 0x00000280u 2761 2762#define HW_ATL_GLB_MDIO_IFACE_N_ADR(number) \ 2763 (HW_ATL_GLB_MDIO_IFACE_ADDR_BEGIN + (((number) - 1) * 0x4)) 2764 2765/* MIF MDIO Busy Bitfield Definitions 2766 * Preprocessor definitions for the bitfield "MDIO Busy". 2767 * PORT="mdio_pif_busy_o" 2768 */ 2769 2770/* Register address for bitfield MDIO Busy */ 2771#define HW_ATL_MDIO_BUSY_ADR 0x00000284 2772/* Bitmask for bitfield MDIO Busy */ 2773#define HW_ATL_MDIO_BUSY_MSK 0x80000000 2774/* Inverted bitmask for bitfield MDIO Busy */ 2775#define HW_ATL_MDIO_BUSY_MSKN 0x7FFFFFFF 2776/* Lower bit position of bitfield MDIO Busy */ 2777#define HW_ATL_MDIO_BUSY_SHIFT 31 2778/* Width of bitfield MDIO Busy */ 2779#define HW_ATL_MDIO_BUSY_WIDTH 1 2780 2781/* MIF MDIO Execute Operation Bitfield Definitions 2782 * Preprocessor definitions for the bitfield "MDIO Execute Operation". 2783 * PORT="pif_mdio_op_start_i" 2784 */ 2785 2786/* Register address for bitfield MDIO Execute Operation */ 2787#define HW_ATL_MDIO_EXECUTE_OPERATION_ADR 0x00000284 2788/* Bitmask for bitfield MDIO Execute Operation */ 2789#define HW_ATL_MDIO_EXECUTE_OPERATION_MSK 0x00008000 2790/* Inverted bitmask for bitfield MDIO Execute Operation */ 2791#define HW_ATL_MDIO_EXECUTE_OPERATION_MSKN 0xFFFF7FFF 2792/* Lower bit position of bitfield MDIO Execute Operation */ 2793#define HW_ATL_MDIO_EXECUTE_OPERATION_SHIFT 15 2794/* Width of bitfield MDIO Execute Operation */ 2795#define HW_ATL_MDIO_EXECUTE_OPERATION_WIDTH 1 2796/* Default value of bitfield MDIO Execute Operation */ 2797#define HW_ATL_MDIO_EXECUTE_OPERATION_DEFAULT 0x0 2798 2799/* MIF Op Mode [1:0] Bitfield Definitions 2800 * Preprocessor definitions for the bitfield "Op Mode [1:0]". 2801 * PORT="pif_mdio_mode_i[1:0]" 2802 */ 2803 2804/* Register address for bitfield Op Mode [1:0] */ 2805#define HW_ATL_MDIO_OP_MODE_ADR 0x00000284 2806/* Bitmask for bitfield Op Mode [1:0] */ 2807#define HW_ATL_MDIO_OP_MODE_MSK 0x00003000 2808/* Inverted bitmask for bitfield Op Mode [1:0] */ 2809#define HW_ATL_MDIO_OP_MODE_MSKN 0xFFFFCFFF 2810/* Lower bit position of bitfield Op Mode [1:0] */ 2811#define HW_ATL_MDIO_OP_MODE_SHIFT 12 2812/* Width of bitfield Op Mode [1:0] */ 2813#define HW_ATL_MDIO_OP_MODE_WIDTH 2 2814/* Default value of bitfield Op Mode [1:0] */ 2815#define HW_ATL_MDIO_OP_MODE_DEFAULT 0x0 2816 2817/* MIF PHY address Bitfield Definitions 2818 * Preprocessor definitions for the bitfield "PHY address". 2819 * PORT="pif_mdio_phy_addr_i[9:0]" 2820 */ 2821 2822/* Register address for bitfield PHY address */ 2823#define HW_ATL_MDIO_PHY_ADDRESS_ADR 0x00000284 2824/* Bitmask for bitfield PHY address */ 2825#define HW_ATL_MDIO_PHY_ADDRESS_MSK 0x000003FF 2826/* Inverted bitmask for bitfield PHY address */ 2827#define HW_ATL_MDIO_PHY_ADDRESS_MSKN 0xFFFFFC00 2828/* Lower bit position of bitfield PHY address */ 2829#define HW_ATL_MDIO_PHY_ADDRESS_SHIFT 0 2830/* Width of bitfield PHY address */ 2831#define HW_ATL_MDIO_PHY_ADDRESS_WIDTH 10 2832/* Default value of bitfield PHY address */ 2833#define HW_ATL_MDIO_PHY_ADDRESS_DEFAULT 0x0 2834 2835/* MIF MDIO WriteData [F:0] Bitfield Definitions 2836 * Preprocessor definitions for the bitfield "MDIO WriteData [F:0]". 2837 * PORT="pif_mdio_wdata_i[15:0]" 2838 */ 2839 2840/* Register address for bitfield MDIO WriteData [F:0] */ 2841#define HW_ATL_MDIO_WRITE_DATA_ADR 0x00000288 2842/* Bitmask for bitfield MDIO WriteData [F:0] */ 2843#define HW_ATL_MDIO_WRITE_DATA_MSK 0x0000FFFF 2844/* Inverted bitmask for bitfield MDIO WriteData [F:0] */ 2845#define HW_ATL_MDIO_WRITE_DATA_MSKN 0xFFFF0000 2846/* Lower bit position of bitfield MDIO WriteData [F:0] */ 2847#define HW_ATL_MDIO_WRITE_DATA_SHIFT 0 2848/* Width of bitfield MDIO WriteData [F:0] */ 2849#define HW_ATL_MDIO_WRITE_DATA_WIDTH 16 2850/* Default value of bitfield MDIO WriteData [F:0] */ 2851#define HW_ATL_MDIO_WRITE_DATA_DEFAULT 0x0 2852 2853/* MIF MDIO Address [F:0] Bitfield Definitions 2854 * Preprocessor definitions for the bitfield "MDIO Address [F:0]". 2855 * PORT="pif_mdio_addr_i[15:0]" 2856 */ 2857 2858/* Register address for bitfield MDIO Address [F:0] */ 2859#define HW_ATL_MDIO_ADDRESS_ADR 0x0000028C 2860/* Bitmask for bitfield MDIO Address [F:0] */ 2861#define HW_ATL_MDIO_ADDRESS_MSK 0x0000FFFF 2862/* Inverted bitmask for bitfield MDIO Address [F:0] */ 2863#define HW_ATL_MDIO_ADDRESS_MSKN 0xFFFF0000 2864/* Lower bit position of bitfield MDIO Address [F:0] */ 2865#define HW_ATL_MDIO_ADDRESS_SHIFT 0 2866/* Width of bitfield MDIO Address [F:0] */ 2867#define HW_ATL_MDIO_ADDRESS_WIDTH 16 2868/* Default value of bitfield MDIO Address [F:0] */ 2869#define HW_ATL_MDIO_ADDRESS_DEFAULT 0x0 2870 2871#define HW_ATL_MIF_RESET_TIMEOUT_ADR 0x00000348 2872 2873#define HW_ATL_FW_SM_MDIO 0x0U 2874#define HW_ATL_FW_SM_RAM 0x2U 2875#define HW_ATL_FW_SM_RESET1 0x3U 2876#define HW_ATL_FW_SM_RESET2 0x4U 2877 2878#endif /* HW_ATL_LLH_INTERNAL_H */ 2879