1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2/* 3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6#ifndef ENA_COM 7#define ENA_COM 8 9#include <linux/compiler.h> 10#include <linux/delay.h> 11#include <linux/dma-mapping.h> 12#include <linux/gfp.h> 13#include <linux/io.h> 14#include <linux/prefetch.h> 15#include <linux/sched.h> 16#include <linux/sizes.h> 17#include <linux/spinlock.h> 18#include <linux/types.h> 19#include <linux/wait.h> 20#include <linux/netdevice.h> 21 22#include "ena_common_defs.h" 23#include "ena_admin_defs.h" 24#include "ena_eth_io_defs.h" 25#include "ena_regs_defs.h" 26 27#undef pr_fmt 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30#define ENA_MAX_NUM_IO_QUEUES 128U 31/* We need to queues for each IO (on for Tx and one for Rx) */ 32#define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES)) 33 34#define ENA_MAX_HANDLERS 256 35 36#define ENA_MAX_PHYS_ADDR_SIZE_BITS 48 37 38/* Unit in usec */ 39#define ENA_REG_READ_TIMEOUT 200000 40 41#define ADMIN_SQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aq_entry)) 42#define ADMIN_CQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_acq_entry)) 43#define ADMIN_AENQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aenq_entry)) 44 45/*****************************************************************************/ 46/*****************************************************************************/ 47/* ENA adaptive interrupt moderation settings */ 48 49#define ENA_INTR_INITIAL_TX_INTERVAL_USECS 64 50#define ENA_INTR_INITIAL_RX_INTERVAL_USECS 0 51#define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1 52 53#define ENA_HASH_KEY_SIZE 40 54 55#define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF 56 57#define ENA_FEATURE_MAX_QUEUE_EXT_VER 1 58 59struct ena_llq_configurations { 60 enum ena_admin_llq_header_location llq_header_location; 61 enum ena_admin_llq_ring_entry_size llq_ring_entry_size; 62 enum ena_admin_llq_stride_ctrl llq_stride_ctrl; 63 enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header; 64 u16 llq_ring_entry_size_value; 65}; 66 67enum queue_direction { 68 ENA_COM_IO_QUEUE_DIRECTION_TX, 69 ENA_COM_IO_QUEUE_DIRECTION_RX 70}; 71 72struct ena_com_buf { 73 dma_addr_t paddr; /**< Buffer physical address */ 74 u16 len; /**< Buffer length in bytes */ 75}; 76 77struct ena_com_rx_buf_info { 78 u16 len; 79 u16 req_id; 80}; 81 82struct ena_com_io_desc_addr { 83 u8 __iomem *pbuf_dev_addr; /* LLQ address */ 84 u8 *virt_addr; 85 dma_addr_t phys_addr; 86}; 87 88struct ena_com_tx_meta { 89 u16 mss; 90 u16 l3_hdr_len; 91 u16 l3_hdr_offset; 92 u16 l4_hdr_len; /* In words */ 93}; 94 95struct ena_com_llq_info { 96 u16 header_location_ctrl; 97 u16 desc_stride_ctrl; 98 u16 desc_list_entry_size_ctrl; 99 u16 desc_list_entry_size; 100 u16 descs_num_before_header; 101 u16 descs_per_entry; 102 u16 max_entries_in_tx_burst; 103 bool disable_meta_caching; 104}; 105 106struct ena_com_io_cq { 107 struct ena_com_io_desc_addr cdesc_addr; 108 109 /* Interrupt unmask register */ 110 u32 __iomem *unmask_reg; 111 112 /* numa configuration register (for TPH) */ 113 u32 __iomem *numa_node_cfg_reg; 114 115 /* The value to write to the above register to unmask 116 * the interrupt of this queue 117 */ 118 u32 msix_vector ____cacheline_aligned; 119 120 enum queue_direction direction; 121 122 /* holds the number of cdesc of the current packet */ 123 u16 cur_rx_pkt_cdesc_count; 124 /* save the first cdesc idx of the current packet */ 125 u16 cur_rx_pkt_cdesc_start_idx; 126 127 u16 q_depth; 128 /* Caller qid */ 129 u16 qid; 130 131 /* Device queue index */ 132 u16 idx; 133 u16 head; 134 u8 phase; 135 u8 cdesc_entry_size_in_bytes; 136 137} ____cacheline_aligned; 138 139struct ena_com_io_bounce_buffer_control { 140 u8 *base_buffer; 141 u16 next_to_use; 142 u16 buffer_size; 143 u16 buffers_num; /* Must be a power of 2 */ 144}; 145 146/* This struct is to keep tracking the current location of the next llq entry */ 147struct ena_com_llq_pkt_ctrl { 148 u8 *curr_bounce_buf; 149 u16 idx; 150 u16 descs_left_in_line; 151}; 152 153struct ena_com_io_sq { 154 struct ena_com_io_desc_addr desc_addr; 155 156 u32 __iomem *db_addr; 157 158 enum queue_direction direction; 159 enum ena_admin_placement_policy_type mem_queue_type; 160 161 bool disable_meta_caching; 162 163 u32 msix_vector; 164 struct ena_com_tx_meta cached_tx_meta; 165 struct ena_com_llq_info llq_info; 166 struct ena_com_llq_pkt_ctrl llq_buf_ctrl; 167 struct ena_com_io_bounce_buffer_control bounce_buf_ctrl; 168 169 u16 q_depth; 170 u16 qid; 171 172 u16 idx; 173 u16 tail; 174 u16 next_to_comp; 175 u16 llq_last_copy_tail; 176 u32 tx_max_header_size; 177 u8 phase; 178 u8 desc_entry_size; 179 u8 dma_addr_bits; 180 u16 entries_in_tx_burst_left; 181} ____cacheline_aligned; 182 183struct ena_com_admin_cq { 184 struct ena_admin_acq_entry *entries; 185 dma_addr_t dma_addr; 186 187 u16 head; 188 u8 phase; 189}; 190 191struct ena_com_admin_sq { 192 struct ena_admin_aq_entry *entries; 193 dma_addr_t dma_addr; 194 195 u32 __iomem *db_addr; 196 197 u16 head; 198 u16 tail; 199 u8 phase; 200 201}; 202 203struct ena_com_stats_admin { 204 u64 aborted_cmd; 205 u64 submitted_cmd; 206 u64 completed_cmd; 207 u64 out_of_space; 208 u64 no_completion; 209}; 210 211struct ena_com_admin_queue { 212 void *q_dmadev; 213 struct ena_com_dev *ena_dev; 214 spinlock_t q_lock; /* spinlock for the admin queue */ 215 216 struct ena_comp_ctx *comp_ctx; 217 u32 completion_timeout; 218 u16 q_depth; 219 struct ena_com_admin_cq cq; 220 struct ena_com_admin_sq sq; 221 222 /* Indicate if the admin queue should poll for completion */ 223 bool polling; 224 225 /* Define if fallback to polling mode should occur */ 226 bool auto_polling; 227 228 u16 curr_cmd_id; 229 230 /* Indicate that the ena was initialized and can 231 * process new admin commands 232 */ 233 bool running_state; 234 235 /* Count the number of outstanding admin commands */ 236 atomic_t outstanding_cmds; 237 238 struct ena_com_stats_admin stats; 239}; 240 241struct ena_aenq_handlers; 242 243struct ena_com_aenq { 244 u16 head; 245 u8 phase; 246 struct ena_admin_aenq_entry *entries; 247 dma_addr_t dma_addr; 248 u16 q_depth; 249 struct ena_aenq_handlers *aenq_handlers; 250}; 251 252struct ena_com_mmio_read { 253 struct ena_admin_ena_mmio_req_read_less_resp *read_resp; 254 dma_addr_t read_resp_dma_addr; 255 u32 reg_read_to; /* in us */ 256 u16 seq_num; 257 bool readless_supported; 258 /* spin lock to ensure a single outstanding read */ 259 spinlock_t lock; 260}; 261 262struct ena_rss { 263 /* Indirect table */ 264 u16 *host_rss_ind_tbl; 265 struct ena_admin_rss_ind_table_entry *rss_ind_tbl; 266 dma_addr_t rss_ind_tbl_dma_addr; 267 u16 tbl_log_size; 268 269 /* Hash key */ 270 enum ena_admin_hash_functions hash_func; 271 struct ena_admin_feature_rss_flow_hash_control *hash_key; 272 dma_addr_t hash_key_dma_addr; 273 u32 hash_init_val; 274 275 /* Flow Control */ 276 struct ena_admin_feature_rss_hash_control *hash_ctrl; 277 dma_addr_t hash_ctrl_dma_addr; 278 279}; 280 281struct ena_host_attribute { 282 /* Debug area */ 283 u8 *debug_area_virt_addr; 284 dma_addr_t debug_area_dma_addr; 285 u32 debug_area_size; 286 287 /* Host information */ 288 struct ena_admin_host_info *host_info; 289 dma_addr_t host_info_dma_addr; 290}; 291 292/* Each ena_dev is a PCI function. */ 293struct ena_com_dev { 294 struct ena_com_admin_queue admin_queue; 295 struct ena_com_aenq aenq; 296 struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES]; 297 struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES]; 298 u8 __iomem *reg_bar; 299 void __iomem *mem_bar; 300 void *dmadev; 301 struct net_device *net_device; 302 303 enum ena_admin_placement_policy_type tx_mem_queue_type; 304 u32 tx_max_header_size; 305 u16 stats_func; /* Selected function for extended statistic dump */ 306 u16 stats_queue; /* Selected queue for extended statistic dump */ 307 308 struct ena_com_mmio_read mmio_read; 309 310 struct ena_rss rss; 311 u32 supported_features; 312 u32 capabilities; 313 u32 dma_addr_bits; 314 315 struct ena_host_attribute host_attr; 316 bool adaptive_coalescing; 317 u16 intr_delay_resolution; 318 319 /* interrupt moderation intervals are in usec divided by 320 * intr_delay_resolution, which is supplied by the device. 321 */ 322 u32 intr_moder_tx_interval; 323 u32 intr_moder_rx_interval; 324 325 struct ena_intr_moder_entry *intr_moder_tbl; 326 327 struct ena_com_llq_info llq_info; 328 329 u32 ena_min_poll_delay_us; 330}; 331 332struct ena_com_dev_get_features_ctx { 333 struct ena_admin_queue_feature_desc max_queues; 334 struct ena_admin_queue_ext_feature_desc max_queue_ext; 335 struct ena_admin_device_attr_feature_desc dev_attr; 336 struct ena_admin_feature_aenq_desc aenq; 337 struct ena_admin_feature_offload_desc offload; 338 struct ena_admin_ena_hw_hints hw_hints; 339 struct ena_admin_feature_llq_desc llq; 340}; 341 342struct ena_com_create_io_ctx { 343 enum ena_admin_placement_policy_type mem_queue_type; 344 enum queue_direction direction; 345 int numa_node; 346 u32 msix_vector; 347 u16 queue_size; 348 u16 qid; 349}; 350 351typedef void (*ena_aenq_handler)(void *data, 352 struct ena_admin_aenq_entry *aenq_e); 353 354/* Holds aenq handlers. Indexed by AENQ event group */ 355struct ena_aenq_handlers { 356 ena_aenq_handler handlers[ENA_MAX_HANDLERS]; 357 ena_aenq_handler unimplemented_handler; 358}; 359 360/*****************************************************************************/ 361/*****************************************************************************/ 362 363/* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism 364 * @ena_dev: ENA communication layer struct 365 * 366 * Initialize the register read mechanism. 367 * 368 * @note: This method must be the first stage in the initialization sequence. 369 * 370 * @return - 0 on success, negative value on failure. 371 */ 372int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev); 373 374/* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism 375 * @ena_dev: ENA communication layer struct 376 * @readless_supported: readless mode (enable/disable) 377 */ 378void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, 379 bool readless_supported); 380 381/* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return 382 * value physical address. 383 * @ena_dev: ENA communication layer struct 384 */ 385void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev); 386 387/* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism 388 * @ena_dev: ENA communication layer struct 389 */ 390void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev); 391 392/* ena_com_admin_init - Init the admin and the async queues 393 * @ena_dev: ENA communication layer struct 394 * @aenq_handlers: Those handlers to be called upon event. 395 * 396 * Initialize the admin submission and completion queues. 397 * Initialize the asynchronous events notification queues. 398 * 399 * @return - 0 on success, negative value on failure. 400 */ 401int ena_com_admin_init(struct ena_com_dev *ena_dev, 402 struct ena_aenq_handlers *aenq_handlers); 403 404/* ena_com_admin_destroy - Destroy the admin and the async events queues. 405 * @ena_dev: ENA communication layer struct 406 * 407 * @note: Before calling this method, the caller must validate that the device 408 * won't send any additional admin completions/aenq. 409 * To achieve that, a FLR is recommended. 410 */ 411void ena_com_admin_destroy(struct ena_com_dev *ena_dev); 412 413/* ena_com_dev_reset - Perform device FLR to the device. 414 * @ena_dev: ENA communication layer struct 415 * @reset_reason: Specify what is the trigger for the reset in case of an error. 416 * 417 * @return - 0 on success, negative value on failure. 418 */ 419int ena_com_dev_reset(struct ena_com_dev *ena_dev, 420 enum ena_regs_reset_reason_types reset_reason); 421 422/* ena_com_create_io_queue - Create io queue. 423 * @ena_dev: ENA communication layer struct 424 * @ctx - create context structure 425 * 426 * Create the submission and the completion queues. 427 * 428 * @return - 0 on success, negative value on failure. 429 */ 430int ena_com_create_io_queue(struct ena_com_dev *ena_dev, 431 struct ena_com_create_io_ctx *ctx); 432 433/* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid. 434 * @ena_dev: ENA communication layer struct 435 * @qid - the caller virtual queue id. 436 */ 437void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid); 438 439/* ena_com_get_io_handlers - Return the io queue handlers 440 * @ena_dev: ENA communication layer struct 441 * @qid - the caller virtual queue id. 442 * @io_sq - IO submission queue handler 443 * @io_cq - IO completion queue handler. 444 * 445 * @return - 0 on success, negative value on failure. 446 */ 447int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, 448 struct ena_com_io_sq **io_sq, 449 struct ena_com_io_cq **io_cq); 450 451/* ena_com_admin_aenq_enable - ENAble asynchronous event notifications 452 * @ena_dev: ENA communication layer struct 453 * 454 * After this method, aenq event can be received via AENQ. 455 */ 456void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev); 457 458/* ena_com_set_admin_running_state - Set the state of the admin queue 459 * @ena_dev: ENA communication layer struct 460 * 461 * Change the state of the admin queue (enable/disable) 462 */ 463void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state); 464 465/* ena_com_get_admin_running_state - Get the admin queue state 466 * @ena_dev: ENA communication layer struct 467 * 468 * Retrieve the state of the admin queue (enable/disable) 469 * 470 * @return - current polling mode (enable/disable) 471 */ 472bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev); 473 474/* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode 475 * @ena_dev: ENA communication layer struct 476 * @polling: ENAble/Disable polling mode 477 * 478 * Set the admin completion mode. 479 */ 480void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling); 481 482/* ena_com_set_admin_auto_polling_mode - Enable autoswitch to polling mode 483 * @ena_dev: ENA communication layer struct 484 * @polling: Enable/Disable polling mode 485 * 486 * Set the autopolling mode. 487 * If autopolling is on: 488 * In case of missing interrupt when data is available switch to polling. 489 */ 490void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev, 491 bool polling); 492 493/* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler 494 * @ena_dev: ENA communication layer struct 495 * 496 * This method goes over the admin completion queue and wakes up all the pending 497 * threads that wait on the commands wait event. 498 * 499 * @note: Should be called after MSI-X interrupt. 500 */ 501void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev); 502 503/* ena_com_aenq_intr_handler - AENQ interrupt handler 504 * @ena_dev: ENA communication layer struct 505 * 506 * This method goes over the async event notification queue and calls the proper 507 * aenq handler. 508 */ 509void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data); 510 511/* ena_com_abort_admin_commands - Abort all the outstanding admin commands. 512 * @ena_dev: ENA communication layer struct 513 * 514 * This method aborts all the outstanding admin commands. 515 * The caller should then call ena_com_wait_for_abort_completion to make sure 516 * all the commands were completed. 517 */ 518void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev); 519 520/* ena_com_wait_for_abort_completion - Wait for admin commands abort. 521 * @ena_dev: ENA communication layer struct 522 * 523 * This method waits until all the outstanding admin commands are completed. 524 */ 525void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev); 526 527/* ena_com_validate_version - Validate the device parameters 528 * @ena_dev: ENA communication layer struct 529 * 530 * This method verifies the device parameters are the same as the saved 531 * parameters in ena_dev. 532 * This method is useful after device reset, to validate the device mac address 533 * and the device offloads are the same as before the reset. 534 * 535 * @return - 0 on success negative value otherwise. 536 */ 537int ena_com_validate_version(struct ena_com_dev *ena_dev); 538 539/* ena_com_get_link_params - Retrieve physical link parameters. 540 * @ena_dev: ENA communication layer struct 541 * @resp: Link parameters 542 * 543 * Retrieve the physical link parameters, 544 * like speed, auto-negotiation and full duplex support. 545 * 546 * @return - 0 on Success negative value otherwise. 547 */ 548int ena_com_get_link_params(struct ena_com_dev *ena_dev, 549 struct ena_admin_get_feat_resp *resp); 550 551/* ena_com_get_dma_width - Retrieve physical dma address width the device 552 * supports. 553 * @ena_dev: ENA communication layer struct 554 * 555 * Retrieve the maximum physical address bits the device can handle. 556 * 557 * @return: > 0 on Success and negative value otherwise. 558 */ 559int ena_com_get_dma_width(struct ena_com_dev *ena_dev); 560 561/* ena_com_set_aenq_config - Set aenq groups configurations 562 * @ena_dev: ENA communication layer struct 563 * @groups flag: bit fields flags of enum ena_admin_aenq_group. 564 * 565 * Configure which aenq event group the driver would like to receive. 566 * 567 * @return: 0 on Success and negative value otherwise. 568 */ 569int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag); 570 571/* ena_com_get_dev_attr_feat - Get device features 572 * @ena_dev: ENA communication layer struct 573 * @get_feat_ctx: returned context that contain the get features. 574 * 575 * @return: 0 on Success and negative value otherwise. 576 */ 577int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, 578 struct ena_com_dev_get_features_ctx *get_feat_ctx); 579 580/* ena_com_get_dev_basic_stats - Get device basic statistics 581 * @ena_dev: ENA communication layer struct 582 * @stats: stats return value 583 * 584 * @return: 0 on Success and negative value otherwise. 585 */ 586int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, 587 struct ena_admin_basic_stats *stats); 588 589/* ena_com_get_eni_stats - Get extended network interface statistics 590 * @ena_dev: ENA communication layer struct 591 * @stats: stats return value 592 * 593 * @return: 0 on Success and negative value otherwise. 594 */ 595int ena_com_get_eni_stats(struct ena_com_dev *ena_dev, 596 struct ena_admin_eni_stats *stats); 597 598/* ena_com_set_dev_mtu - Configure the device mtu. 599 * @ena_dev: ENA communication layer struct 600 * @mtu: mtu value 601 * 602 * @return: 0 on Success and negative value otherwise. 603 */ 604int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, u32 mtu); 605 606/* ena_com_get_offload_settings - Retrieve the device offloads capabilities 607 * @ena_dev: ENA communication layer struct 608 * @offlad: offload return value 609 * 610 * @return: 0 on Success and negative value otherwise. 611 */ 612int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, 613 struct ena_admin_feature_offload_desc *offload); 614 615/* ena_com_rss_init - Init RSS 616 * @ena_dev: ENA communication layer struct 617 * @log_size: indirection log size 618 * 619 * Allocate RSS/RFS resources. 620 * The caller then can configure rss using ena_com_set_hash_function, 621 * ena_com_set_hash_ctrl and ena_com_indirect_table_set. 622 * 623 * @return: 0 on Success and negative value otherwise. 624 */ 625int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size); 626 627/* ena_com_rss_destroy - Destroy rss 628 * @ena_dev: ENA communication layer struct 629 * 630 * Free all the RSS/RFS resources. 631 */ 632void ena_com_rss_destroy(struct ena_com_dev *ena_dev); 633 634/* ena_com_get_current_hash_function - Get RSS hash function 635 * @ena_dev: ENA communication layer struct 636 * 637 * Return the current hash function. 638 * @return: 0 or one of the ena_admin_hash_functions values. 639 */ 640int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev); 641 642/* ena_com_fill_hash_function - Fill RSS hash function 643 * @ena_dev: ENA communication layer struct 644 * @func: The hash function (Toeplitz or crc) 645 * @key: Hash key (for toeplitz hash) 646 * @key_len: key length (max length 10 DW) 647 * @init_val: initial value for the hash function 648 * 649 * Fill the ena_dev resources with the desire hash function, hash key, key_len 650 * and key initial value (if needed by the hash function). 651 * To flush the key into the device the caller should call 652 * ena_com_set_hash_function. 653 * 654 * @return: 0 on Success and negative value otherwise. 655 */ 656int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, 657 enum ena_admin_hash_functions func, 658 const u8 *key, u16 key_len, u32 init_val); 659 660/* ena_com_set_hash_function - Flush the hash function and it dependencies to 661 * the device. 662 * @ena_dev: ENA communication layer struct 663 * 664 * Flush the hash function and it dependencies (key, key length and 665 * initial value) if needed. 666 * 667 * @note: Prior to this method the caller should call ena_com_fill_hash_function 668 * 669 * @return: 0 on Success and negative value otherwise. 670 */ 671int ena_com_set_hash_function(struct ena_com_dev *ena_dev); 672 673/* ena_com_get_hash_function - Retrieve the hash function from the device. 674 * @ena_dev: ENA communication layer struct 675 * @func: hash function 676 * 677 * Retrieve the hash function from the device. 678 * 679 * @note: If the caller called ena_com_fill_hash_function but didn't flush 680 * it to the device, the new configuration will be lost. 681 * 682 * @return: 0 on Success and negative value otherwise. 683 */ 684int ena_com_get_hash_function(struct ena_com_dev *ena_dev, 685 enum ena_admin_hash_functions *func); 686 687/* ena_com_get_hash_key - Retrieve the hash key 688 * @ena_dev: ENA communication layer struct 689 * @key: hash key 690 * 691 * Retrieve the hash key. 692 * 693 * @note: If the caller called ena_com_fill_hash_key but didn't flush 694 * it to the device, the new configuration will be lost. 695 * 696 * @return: 0 on Success and negative value otherwise. 697 */ 698int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key); 699/* ena_com_fill_hash_ctrl - Fill RSS hash control 700 * @ena_dev: ENA communication layer struct. 701 * @proto: The protocol to configure. 702 * @hash_fields: bit mask of ena_admin_flow_hash_fields 703 * 704 * Fill the ena_dev resources with the desire hash control (the ethernet 705 * fields that take part of the hash) for a specific protocol. 706 * To flush the hash control to the device, the caller should call 707 * ena_com_set_hash_ctrl. 708 * 709 * @return: 0 on Success and negative value otherwise. 710 */ 711int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, 712 enum ena_admin_flow_hash_proto proto, 713 u16 hash_fields); 714 715/* ena_com_set_hash_ctrl - Flush the hash control resources to the device. 716 * @ena_dev: ENA communication layer struct 717 * 718 * Flush the hash control (the ethernet fields that take part of the hash) 719 * 720 * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl. 721 * 722 * @return: 0 on Success and negative value otherwise. 723 */ 724int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev); 725 726/* ena_com_get_hash_ctrl - Retrieve the hash control from the device. 727 * @ena_dev: ENA communication layer struct 728 * @proto: The protocol to retrieve. 729 * @fields: bit mask of ena_admin_flow_hash_fields. 730 * 731 * Retrieve the hash control from the device. 732 * 733 * @note: If the caller called ena_com_fill_hash_ctrl but didn't flush 734 * it to the device, the new configuration will be lost. 735 * 736 * @return: 0 on Success and negative value otherwise. 737 */ 738int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, 739 enum ena_admin_flow_hash_proto proto, 740 u16 *fields); 741 742/* ena_com_set_default_hash_ctrl - Set the hash control to a default 743 * configuration. 744 * @ena_dev: ENA communication layer struct 745 * 746 * Fill the ena_dev resources with the default hash control configuration. 747 * To flush the hash control to the device, the caller should call 748 * ena_com_set_hash_ctrl. 749 * 750 * @return: 0 on Success and negative value otherwise. 751 */ 752int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev); 753 754/* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS 755 * indirection table 756 * @ena_dev: ENA communication layer struct. 757 * @entry_idx - indirection table entry. 758 * @entry_value - redirection value 759 * 760 * Fill a single entry of the RSS indirection table in the ena_dev resources. 761 * To flush the indirection table to the device, the called should call 762 * ena_com_indirect_table_set. 763 * 764 * @return: 0 on Success and negative value otherwise. 765 */ 766int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, 767 u16 entry_idx, u16 entry_value); 768 769/* ena_com_indirect_table_set - Flush the indirection table to the device. 770 * @ena_dev: ENA communication layer struct 771 * 772 * Flush the indirection hash control to the device. 773 * Prior to this method the caller should call ena_com_indirect_table_fill_entry 774 * 775 * @return: 0 on Success and negative value otherwise. 776 */ 777int ena_com_indirect_table_set(struct ena_com_dev *ena_dev); 778 779/* ena_com_indirect_table_get - Retrieve the indirection table from the device. 780 * @ena_dev: ENA communication layer struct 781 * @ind_tbl: indirection table 782 * 783 * Retrieve the RSS indirection table from the device. 784 * 785 * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flush 786 * it to the device, the new configuration will be lost. 787 * 788 * @return: 0 on Success and negative value otherwise. 789 */ 790int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl); 791 792/* ena_com_allocate_host_info - Allocate host info resources. 793 * @ena_dev: ENA communication layer struct 794 * 795 * @return: 0 on Success and negative value otherwise. 796 */ 797int ena_com_allocate_host_info(struct ena_com_dev *ena_dev); 798 799/* ena_com_allocate_debug_area - Allocate debug area. 800 * @ena_dev: ENA communication layer struct 801 * @debug_area_size - debug area size. 802 * 803 * @return: 0 on Success and negative value otherwise. 804 */ 805int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, 806 u32 debug_area_size); 807 808/* ena_com_delete_debug_area - Free the debug area resources. 809 * @ena_dev: ENA communication layer struct 810 * 811 * Free the allocated debug area. 812 */ 813void ena_com_delete_debug_area(struct ena_com_dev *ena_dev); 814 815/* ena_com_delete_host_info - Free the host info resources. 816 * @ena_dev: ENA communication layer struct 817 * 818 * Free the allocated host info. 819 */ 820void ena_com_delete_host_info(struct ena_com_dev *ena_dev); 821 822/* ena_com_set_host_attributes - Update the device with the host 823 * attributes (debug area and host info) base address. 824 * @ena_dev: ENA communication layer struct 825 * 826 * @return: 0 on Success and negative value otherwise. 827 */ 828int ena_com_set_host_attributes(struct ena_com_dev *ena_dev); 829 830/* ena_com_create_io_cq - Create io completion queue. 831 * @ena_dev: ENA communication layer struct 832 * @io_cq - io completion queue handler 833 834 * Create IO completion queue. 835 * 836 * @return - 0 on success, negative value on failure. 837 */ 838int ena_com_create_io_cq(struct ena_com_dev *ena_dev, 839 struct ena_com_io_cq *io_cq); 840 841/* ena_com_destroy_io_cq - Destroy io completion queue. 842 * @ena_dev: ENA communication layer struct 843 * @io_cq - io completion queue handler 844 845 * Destroy IO completion queue. 846 * 847 * @return - 0 on success, negative value on failure. 848 */ 849int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, 850 struct ena_com_io_cq *io_cq); 851 852/* ena_com_execute_admin_command - Execute admin command 853 * @admin_queue: admin queue. 854 * @cmd: the admin command to execute. 855 * @cmd_size: the command size. 856 * @cmd_completion: command completion return value. 857 * @cmd_comp_size: command completion size. 858 859 * Submit an admin command and then wait until the device returns a 860 * completion. 861 * The completion will be copied into cmd_comp. 862 * 863 * @return - 0 on success, negative value on failure. 864 */ 865int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, 866 struct ena_admin_aq_entry *cmd, 867 size_t cmd_size, 868 struct ena_admin_acq_entry *cmd_comp, 869 size_t cmd_comp_size); 870 871/* ena_com_init_interrupt_moderation - Init interrupt moderation 872 * @ena_dev: ENA communication layer struct 873 * 874 * @return - 0 on success, negative value on failure. 875 */ 876int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev); 877 878/* ena_com_interrupt_moderation_supported - Return if interrupt moderation 879 * capability is supported by the device. 880 * 881 * @return - supported or not. 882 */ 883bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev); 884 885/* ena_com_update_nonadaptive_moderation_interval_tx - Update the 886 * non-adaptive interval in Tx direction. 887 * @ena_dev: ENA communication layer struct 888 * @tx_coalesce_usecs: Interval in usec. 889 * 890 * @return - 0 on success, negative value on failure. 891 */ 892int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, 893 u32 tx_coalesce_usecs); 894 895/* ena_com_update_nonadaptive_moderation_interval_rx - Update the 896 * non-adaptive interval in Rx direction. 897 * @ena_dev: ENA communication layer struct 898 * @rx_coalesce_usecs: Interval in usec. 899 * 900 * @return - 0 on success, negative value on failure. 901 */ 902int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, 903 u32 rx_coalesce_usecs); 904 905/* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the 906 * non-adaptive interval in Tx direction. 907 * @ena_dev: ENA communication layer struct 908 * 909 * @return - interval in usec 910 */ 911unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev); 912 913/* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the 914 * non-adaptive interval in Rx direction. 915 * @ena_dev: ENA communication layer struct 916 * 917 * @return - interval in usec 918 */ 919unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev); 920 921/* ena_com_config_dev_mode - Configure the placement policy of the device. 922 * @ena_dev: ENA communication layer struct 923 * @llq_features: LLQ feature descriptor, retrieve via 924 * ena_com_get_dev_attr_feat. 925 * @ena_llq_config: The default driver LLQ parameters configurations 926 */ 927int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, 928 struct ena_admin_feature_llq_desc *llq_features, 929 struct ena_llq_configurations *llq_default_config); 930 931/* ena_com_io_sq_to_ena_dev - Extract ena_com_dev using contained field io_sq. 932 * @io_sq: IO submit queue struct 933 * 934 * @return - ena_com_dev struct extracted from io_sq 935 */ 936static inline struct ena_com_dev *ena_com_io_sq_to_ena_dev(struct ena_com_io_sq *io_sq) 937{ 938 return container_of(io_sq, struct ena_com_dev, io_sq_queues[io_sq->qid]); 939} 940 941/* ena_com_io_cq_to_ena_dev - Extract ena_com_dev using contained field io_cq. 942 * @io_sq: IO submit queue struct 943 * 944 * @return - ena_com_dev struct extracted from io_sq 945 */ 946static inline struct ena_com_dev *ena_com_io_cq_to_ena_dev(struct ena_com_io_cq *io_cq) 947{ 948 return container_of(io_cq, struct ena_com_dev, io_cq_queues[io_cq->qid]); 949} 950 951static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev) 952{ 953 return ena_dev->adaptive_coalescing; 954} 955 956static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev) 957{ 958 ena_dev->adaptive_coalescing = true; 959} 960 961static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev) 962{ 963 ena_dev->adaptive_coalescing = false; 964} 965 966/* ena_com_get_cap - query whether device supports a capability. 967 * @ena_dev: ENA communication layer struct 968 * @cap_id: enum value representing the capability 969 * 970 * @return - true if capability is supported or false otherwise 971 */ 972static inline bool ena_com_get_cap(struct ena_com_dev *ena_dev, 973 enum ena_admin_aq_caps_id cap_id) 974{ 975 return !!(ena_dev->capabilities & BIT(cap_id)); 976} 977 978/* ena_com_update_intr_reg - Prepare interrupt register 979 * @intr_reg: interrupt register to update. 980 * @rx_delay_interval: Rx interval in usecs 981 * @tx_delay_interval: Tx interval in usecs 982 * @unmask: unmask enable/disable 983 * 984 * Prepare interrupt update register with the supplied parameters. 985 */ 986static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg, 987 u32 rx_delay_interval, 988 u32 tx_delay_interval, 989 bool unmask) 990{ 991 intr_reg->intr_control = 0; 992 intr_reg->intr_control |= rx_delay_interval & 993 ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 994 995 intr_reg->intr_control |= 996 (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) 997 & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; 998 999 if (unmask) 1000 intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; 1001} 1002 1003static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl) 1004{ 1005 u16 size, buffers_num; 1006 u8 *buf; 1007 1008 size = bounce_buf_ctrl->buffer_size; 1009 buffers_num = bounce_buf_ctrl->buffers_num; 1010 1011 buf = bounce_buf_ctrl->base_buffer + 1012 (bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size; 1013 1014 prefetchw(bounce_buf_ctrl->base_buffer + 1015 (bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size); 1016 1017 return buf; 1018} 1019 1020#endif /* !(ENA_COM) */ 1021