1// SPDX-License-Identifier: GPL-2.0-only 2/* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface 3 * 4 * Copyright(C) Timesys Corporation 2016 5 * 6 * Based on Microchip 251x CAN Controller (mcp251x) Linux kernel driver 7 * Copyright 2009 Christian Pellegrin EVOL S.r.l. 8 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. 9 * Copyright 2006 Arcom Control Systems Ltd. 10 * 11 * Based on CAN bus driver for the CCAN controller written by 12 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix 13 * - Simon Kallweit, intefo AG 14 * Copyright 2007 15 */ 16 17#include <linux/can/core.h> 18#include <linux/can/dev.h> 19#include <linux/clk.h> 20#include <linux/completion.h> 21#include <linux/delay.h> 22#include <linux/device.h> 23#include <linux/ethtool.h> 24#include <linux/freezer.h> 25#include <linux/interrupt.h> 26#include <linux/io.h> 27#include <linux/kernel.h> 28#include <linux/mod_devicetable.h> 29#include <linux/module.h> 30#include <linux/netdevice.h> 31#include <linux/platform_device.h> 32#include <linux/property.h> 33#include <linux/regulator/consumer.h> 34#include <linux/slab.h> 35#include <linux/spi/spi.h> 36#include <linux/uaccess.h> 37 38#define HI3110_MASTER_RESET 0x56 39#define HI3110_READ_CTRL0 0xD2 40#define HI3110_READ_CTRL1 0xD4 41#define HI3110_READ_STATF 0xE2 42#define HI3110_WRITE_CTRL0 0x14 43#define HI3110_WRITE_CTRL1 0x16 44#define HI3110_WRITE_INTE 0x1C 45#define HI3110_WRITE_BTR0 0x18 46#define HI3110_WRITE_BTR1 0x1A 47#define HI3110_READ_BTR0 0xD6 48#define HI3110_READ_BTR1 0xD8 49#define HI3110_READ_INTF 0xDE 50#define HI3110_READ_ERR 0xDC 51#define HI3110_READ_FIFO_WOTIME 0x48 52#define HI3110_WRITE_FIFO 0x12 53#define HI3110_READ_MESSTAT 0xDA 54#define HI3110_READ_REC 0xEA 55#define HI3110_READ_TEC 0xEC 56 57#define HI3110_CTRL0_MODE_MASK (7 << 5) 58#define HI3110_CTRL0_NORMAL_MODE (0 << 5) 59#define HI3110_CTRL0_LOOPBACK_MODE (1 << 5) 60#define HI3110_CTRL0_MONITOR_MODE (2 << 5) 61#define HI3110_CTRL0_SLEEP_MODE (3 << 5) 62#define HI3110_CTRL0_INIT_MODE (4 << 5) 63 64#define HI3110_CTRL1_TXEN BIT(7) 65 66#define HI3110_INT_RXTMP BIT(7) 67#define HI3110_INT_RXFIFO BIT(6) 68#define HI3110_INT_TXCPLT BIT(5) 69#define HI3110_INT_BUSERR BIT(4) 70#define HI3110_INT_MCHG BIT(3) 71#define HI3110_INT_WAKEUP BIT(2) 72#define HI3110_INT_F1MESS BIT(1) 73#define HI3110_INT_F0MESS BIT(0) 74 75#define HI3110_ERR_BUSOFF BIT(7) 76#define HI3110_ERR_TXERRP BIT(6) 77#define HI3110_ERR_RXERRP BIT(5) 78#define HI3110_ERR_BITERR BIT(4) 79#define HI3110_ERR_FRMERR BIT(3) 80#define HI3110_ERR_CRCERR BIT(2) 81#define HI3110_ERR_ACKERR BIT(1) 82#define HI3110_ERR_STUFERR BIT(0) 83#define HI3110_ERR_PROTOCOL_MASK (0x1F) 84#define HI3110_ERR_PASSIVE_MASK (0x60) 85 86#define HI3110_STAT_RXFMTY BIT(1) 87#define HI3110_STAT_BUSOFF BIT(2) 88#define HI3110_STAT_ERRP BIT(3) 89#define HI3110_STAT_ERRW BIT(4) 90#define HI3110_STAT_TXMTY BIT(7) 91 92#define HI3110_BTR0_SJW_SHIFT 6 93#define HI3110_BTR0_BRP_SHIFT 0 94 95#define HI3110_BTR1_SAMP_3PERBIT (1 << 7) 96#define HI3110_BTR1_SAMP_1PERBIT (0 << 7) 97#define HI3110_BTR1_TSEG2_SHIFT 4 98#define HI3110_BTR1_TSEG1_SHIFT 0 99 100#define HI3110_FIFO_WOTIME_TAG_OFF 0 101#define HI3110_FIFO_WOTIME_ID_OFF 1 102#define HI3110_FIFO_WOTIME_DLC_OFF 5 103#define HI3110_FIFO_WOTIME_DAT_OFF 6 104 105#define HI3110_FIFO_WOTIME_TAG_IDE BIT(7) 106#define HI3110_FIFO_WOTIME_ID_RTR BIT(0) 107 108#define HI3110_FIFO_TAG_OFF 0 109#define HI3110_FIFO_ID_OFF 1 110#define HI3110_FIFO_STD_DLC_OFF 3 111#define HI3110_FIFO_STD_DATA_OFF 4 112#define HI3110_FIFO_EXT_DLC_OFF 5 113#define HI3110_FIFO_EXT_DATA_OFF 6 114 115#define HI3110_CAN_MAX_DATA_LEN 8 116#define HI3110_RX_BUF_LEN 15 117#define HI3110_TX_STD_BUF_LEN 12 118#define HI3110_TX_EXT_BUF_LEN 14 119#define HI3110_CAN_FRAME_MAX_BITS 128 120#define HI3110_EFF_FLAGS 0x18 /* IDE + SRR */ 121 122#define HI3110_TX_ECHO_SKB_MAX 1 123 124#define HI3110_OST_DELAY_MS (10) 125 126#define DEVICE_NAME "hi3110" 127 128static const struct can_bittiming_const hi3110_bittiming_const = { 129 .name = DEVICE_NAME, 130 .tseg1_min = 2, 131 .tseg1_max = 16, 132 .tseg2_min = 2, 133 .tseg2_max = 8, 134 .sjw_max = 4, 135 .brp_min = 1, 136 .brp_max = 64, 137 .brp_inc = 1, 138}; 139 140enum hi3110_model { 141 CAN_HI3110_HI3110 = 0x3110, 142}; 143 144struct hi3110_priv { 145 struct can_priv can; 146 struct net_device *net; 147 struct spi_device *spi; 148 enum hi3110_model model; 149 150 struct mutex hi3110_lock; /* SPI device lock */ 151 152 u8 *spi_tx_buf; 153 u8 *spi_rx_buf; 154 155 struct sk_buff *tx_skb; 156 157 struct workqueue_struct *wq; 158 struct work_struct tx_work; 159 struct work_struct restart_work; 160 161 int force_quit; 162 int after_suspend; 163#define HI3110_AFTER_SUSPEND_UP 1 164#define HI3110_AFTER_SUSPEND_DOWN 2 165#define HI3110_AFTER_SUSPEND_POWER 4 166#define HI3110_AFTER_SUSPEND_RESTART 8 167 int restart_tx; 168 bool tx_busy; 169 170 struct regulator *power; 171 struct regulator *transceiver; 172 struct clk *clk; 173}; 174 175static void hi3110_clean(struct net_device *net) 176{ 177 struct hi3110_priv *priv = netdev_priv(net); 178 179 if (priv->tx_skb || priv->tx_busy) 180 net->stats.tx_errors++; 181 dev_kfree_skb(priv->tx_skb); 182 if (priv->tx_busy) 183 can_free_echo_skb(priv->net, 0, NULL); 184 priv->tx_skb = NULL; 185 priv->tx_busy = false; 186} 187 188/* Note about handling of error return of hi3110_spi_trans: accessing 189 * registers via SPI is not really different conceptually than using 190 * normal I/O assembler instructions, although it's much more 191 * complicated from a practical POV. So it's not advisable to always 192 * check the return value of this function. Imagine that every 193 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) 194 * error();", it would be a great mess (well there are some situation 195 * when exception handling C++ like could be useful after all). So we 196 * just check that transfers are OK at the beginning of our 197 * conversation with the chip and to avoid doing really nasty things 198 * (like injecting bogus packets in the network stack). 199 */ 200static int hi3110_spi_trans(struct spi_device *spi, int len) 201{ 202 struct hi3110_priv *priv = spi_get_drvdata(spi); 203 struct spi_transfer t = { 204 .tx_buf = priv->spi_tx_buf, 205 .rx_buf = priv->spi_rx_buf, 206 .len = len, 207 .cs_change = 0, 208 }; 209 struct spi_message m; 210 int ret; 211 212 spi_message_init(&m); 213 spi_message_add_tail(&t, &m); 214 215 ret = spi_sync(spi, &m); 216 217 if (ret) 218 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); 219 return ret; 220} 221 222static int hi3110_cmd(struct spi_device *spi, u8 command) 223{ 224 struct hi3110_priv *priv = spi_get_drvdata(spi); 225 226 priv->spi_tx_buf[0] = command; 227 dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command); 228 229 return hi3110_spi_trans(spi, 1); 230} 231 232static u8 hi3110_read(struct spi_device *spi, u8 command) 233{ 234 struct hi3110_priv *priv = spi_get_drvdata(spi); 235 u8 val = 0; 236 237 priv->spi_tx_buf[0] = command; 238 hi3110_spi_trans(spi, 2); 239 val = priv->spi_rx_buf[1]; 240 241 return val; 242} 243 244static void hi3110_write(struct spi_device *spi, u8 reg, u8 val) 245{ 246 struct hi3110_priv *priv = spi_get_drvdata(spi); 247 248 priv->spi_tx_buf[0] = reg; 249 priv->spi_tx_buf[1] = val; 250 hi3110_spi_trans(spi, 2); 251} 252 253static void hi3110_hw_tx_frame(struct spi_device *spi, u8 *buf, int len) 254{ 255 struct hi3110_priv *priv = spi_get_drvdata(spi); 256 257 priv->spi_tx_buf[0] = HI3110_WRITE_FIFO; 258 memcpy(priv->spi_tx_buf + 1, buf, len); 259 hi3110_spi_trans(spi, len + 1); 260} 261 262static void hi3110_hw_tx(struct spi_device *spi, struct can_frame *frame) 263{ 264 u8 buf[HI3110_TX_EXT_BUF_LEN]; 265 266 buf[HI3110_FIFO_TAG_OFF] = 0; 267 268 if (frame->can_id & CAN_EFF_FLAG) { 269 /* Extended frame */ 270 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21; 271 buf[HI3110_FIFO_ID_OFF + 1] = 272 (((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) | 273 HI3110_EFF_FLAGS | 274 (((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07); 275 buf[HI3110_FIFO_ID_OFF + 2] = 276 (frame->can_id & CAN_EFF_MASK) >> 7; 277 buf[HI3110_FIFO_ID_OFF + 3] = 278 ((frame->can_id & CAN_EFF_MASK) << 1) | 279 ((frame->can_id & CAN_RTR_FLAG) ? 1 : 0); 280 281 buf[HI3110_FIFO_EXT_DLC_OFF] = frame->len; 282 283 memcpy(buf + HI3110_FIFO_EXT_DATA_OFF, 284 frame->data, frame->len); 285 286 hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN - 287 (HI3110_CAN_MAX_DATA_LEN - frame->len)); 288 } else { 289 /* Standard frame */ 290 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_SFF_MASK) >> 3; 291 buf[HI3110_FIFO_ID_OFF + 1] = 292 ((frame->can_id & CAN_SFF_MASK) << 5) | 293 ((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0); 294 295 buf[HI3110_FIFO_STD_DLC_OFF] = frame->len; 296 297 memcpy(buf + HI3110_FIFO_STD_DATA_OFF, 298 frame->data, frame->len); 299 300 hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN - 301 (HI3110_CAN_MAX_DATA_LEN - frame->len)); 302 } 303} 304 305static void hi3110_hw_rx_frame(struct spi_device *spi, u8 *buf) 306{ 307 struct hi3110_priv *priv = spi_get_drvdata(spi); 308 309 priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME; 310 hi3110_spi_trans(spi, HI3110_RX_BUF_LEN); 311 memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1); 312} 313 314static void hi3110_hw_rx(struct spi_device *spi) 315{ 316 struct hi3110_priv *priv = spi_get_drvdata(spi); 317 struct sk_buff *skb; 318 struct can_frame *frame; 319 u8 buf[HI3110_RX_BUF_LEN - 1]; 320 321 skb = alloc_can_skb(priv->net, &frame); 322 if (!skb) { 323 priv->net->stats.rx_dropped++; 324 return; 325 } 326 327 hi3110_hw_rx_frame(spi, buf); 328 if (buf[HI3110_FIFO_WOTIME_TAG_OFF] & HI3110_FIFO_WOTIME_TAG_IDE) { 329 /* IDE is recessive (1), indicating extended 29-bit frame */ 330 frame->can_id = CAN_EFF_FLAG; 331 frame->can_id |= 332 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 21) | 333 (((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5) << 18) | 334 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0x07) << 15) | 335 (buf[HI3110_FIFO_WOTIME_ID_OFF + 2] << 7) | 336 (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] >> 1); 337 } else { 338 /* IDE is dominant (0), frame indicating standard 11-bit */ 339 frame->can_id = 340 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 3) | 341 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5); 342 } 343 344 /* Data length */ 345 frame->len = can_cc_dlc2len(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F); 346 347 if (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] & HI3110_FIFO_WOTIME_ID_RTR) { 348 frame->can_id |= CAN_RTR_FLAG; 349 } else { 350 memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF, 351 frame->len); 352 353 priv->net->stats.rx_bytes += frame->len; 354 } 355 priv->net->stats.rx_packets++; 356 357 netif_rx(skb); 358} 359 360static void hi3110_hw_sleep(struct spi_device *spi) 361{ 362 hi3110_write(spi, HI3110_WRITE_CTRL0, HI3110_CTRL0_SLEEP_MODE); 363} 364 365static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb, 366 struct net_device *net) 367{ 368 struct hi3110_priv *priv = netdev_priv(net); 369 struct spi_device *spi = priv->spi; 370 371 if (priv->tx_skb || priv->tx_busy) { 372 dev_err(&spi->dev, "hard_xmit called while tx busy\n"); 373 return NETDEV_TX_BUSY; 374 } 375 376 if (can_dev_dropped_skb(net, skb)) 377 return NETDEV_TX_OK; 378 379 netif_stop_queue(net); 380 priv->tx_skb = skb; 381 queue_work(priv->wq, &priv->tx_work); 382 383 return NETDEV_TX_OK; 384} 385 386static int hi3110_do_set_mode(struct net_device *net, enum can_mode mode) 387{ 388 struct hi3110_priv *priv = netdev_priv(net); 389 390 switch (mode) { 391 case CAN_MODE_START: 392 hi3110_clean(net); 393 /* We have to delay work since SPI I/O may sleep */ 394 priv->can.state = CAN_STATE_ERROR_ACTIVE; 395 priv->restart_tx = 1; 396 if (priv->can.restart_ms == 0) 397 priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART; 398 queue_work(priv->wq, &priv->restart_work); 399 break; 400 default: 401 return -EOPNOTSUPP; 402 } 403 404 return 0; 405} 406 407static int hi3110_get_berr_counter(const struct net_device *net, 408 struct can_berr_counter *bec) 409{ 410 struct hi3110_priv *priv = netdev_priv(net); 411 struct spi_device *spi = priv->spi; 412 413 mutex_lock(&priv->hi3110_lock); 414 bec->txerr = hi3110_read(spi, HI3110_READ_TEC); 415 bec->rxerr = hi3110_read(spi, HI3110_READ_REC); 416 mutex_unlock(&priv->hi3110_lock); 417 418 return 0; 419} 420 421static int hi3110_set_normal_mode(struct spi_device *spi) 422{ 423 struct hi3110_priv *priv = spi_get_drvdata(spi); 424 u8 reg = 0; 425 426 hi3110_write(spi, HI3110_WRITE_INTE, HI3110_INT_BUSERR | 427 HI3110_INT_RXFIFO | HI3110_INT_TXCPLT); 428 429 /* Enable TX */ 430 hi3110_write(spi, HI3110_WRITE_CTRL1, HI3110_CTRL1_TXEN); 431 432 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 433 reg = HI3110_CTRL0_LOOPBACK_MODE; 434 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 435 reg = HI3110_CTRL0_MONITOR_MODE; 436 else 437 reg = HI3110_CTRL0_NORMAL_MODE; 438 439 hi3110_write(spi, HI3110_WRITE_CTRL0, reg); 440 441 /* Wait for the device to enter the mode */ 442 mdelay(HI3110_OST_DELAY_MS); 443 reg = hi3110_read(spi, HI3110_READ_CTRL0); 444 if ((reg & HI3110_CTRL0_MODE_MASK) != reg) 445 return -EBUSY; 446 447 priv->can.state = CAN_STATE_ERROR_ACTIVE; 448 return 0; 449} 450 451static int hi3110_do_set_bittiming(struct net_device *net) 452{ 453 struct hi3110_priv *priv = netdev_priv(net); 454 struct can_bittiming *bt = &priv->can.bittiming; 455 struct spi_device *spi = priv->spi; 456 457 hi3110_write(spi, HI3110_WRITE_BTR0, 458 ((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) | 459 ((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT)); 460 461 hi3110_write(spi, HI3110_WRITE_BTR1, 462 (priv->can.ctrlmode & 463 CAN_CTRLMODE_3_SAMPLES ? 464 HI3110_BTR1_SAMP_3PERBIT : HI3110_BTR1_SAMP_1PERBIT) | 465 ((bt->phase_seg1 + bt->prop_seg - 1) 466 << HI3110_BTR1_TSEG1_SHIFT) | 467 ((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT)); 468 469 dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n", 470 hi3110_read(spi, HI3110_READ_BTR0), 471 hi3110_read(spi, HI3110_READ_BTR1)); 472 473 return 0; 474} 475 476static int hi3110_setup(struct net_device *net) 477{ 478 hi3110_do_set_bittiming(net); 479 return 0; 480} 481 482static int hi3110_hw_reset(struct spi_device *spi) 483{ 484 u8 reg; 485 int ret; 486 487 /* Wait for oscillator startup timer after power up */ 488 mdelay(HI3110_OST_DELAY_MS); 489 490 ret = hi3110_cmd(spi, HI3110_MASTER_RESET); 491 if (ret) 492 return ret; 493 494 /* Wait for oscillator startup timer after reset */ 495 mdelay(HI3110_OST_DELAY_MS); 496 497 reg = hi3110_read(spi, HI3110_READ_CTRL0); 498 if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE) 499 return -ENODEV; 500 501 /* As per the datasheet it appears the error flags are 502 * not cleared on reset. Explicitly clear them by performing a read 503 */ 504 hi3110_read(spi, HI3110_READ_ERR); 505 506 return 0; 507} 508 509static int hi3110_hw_probe(struct spi_device *spi) 510{ 511 u8 statf; 512 513 hi3110_hw_reset(spi); 514 515 /* Confirm correct operation by checking against reset values 516 * in datasheet 517 */ 518 statf = hi3110_read(spi, HI3110_READ_STATF); 519 520 dev_dbg(&spi->dev, "statf: %02X\n", statf); 521 522 if (statf != 0x82) 523 return -ENODEV; 524 525 return 0; 526} 527 528static int hi3110_power_enable(struct regulator *reg, int enable) 529{ 530 if (IS_ERR_OR_NULL(reg)) 531 return 0; 532 533 if (enable) 534 return regulator_enable(reg); 535 else 536 return regulator_disable(reg); 537} 538 539static int hi3110_stop(struct net_device *net) 540{ 541 struct hi3110_priv *priv = netdev_priv(net); 542 struct spi_device *spi = priv->spi; 543 544 close_candev(net); 545 546 priv->force_quit = 1; 547 free_irq(spi->irq, priv); 548 destroy_workqueue(priv->wq); 549 priv->wq = NULL; 550 551 mutex_lock(&priv->hi3110_lock); 552 553 /* Disable transmit, interrupts and clear flags */ 554 hi3110_write(spi, HI3110_WRITE_CTRL1, 0x0); 555 hi3110_write(spi, HI3110_WRITE_INTE, 0x0); 556 hi3110_read(spi, HI3110_READ_INTF); 557 558 hi3110_clean(net); 559 560 hi3110_hw_sleep(spi); 561 562 hi3110_power_enable(priv->transceiver, 0); 563 564 priv->can.state = CAN_STATE_STOPPED; 565 566 mutex_unlock(&priv->hi3110_lock); 567 568 return 0; 569} 570 571static void hi3110_tx_work_handler(struct work_struct *ws) 572{ 573 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv, 574 tx_work); 575 struct spi_device *spi = priv->spi; 576 struct net_device *net = priv->net; 577 struct can_frame *frame; 578 579 mutex_lock(&priv->hi3110_lock); 580 if (priv->tx_skb) { 581 if (priv->can.state == CAN_STATE_BUS_OFF) { 582 hi3110_clean(net); 583 } else { 584 frame = (struct can_frame *)priv->tx_skb->data; 585 hi3110_hw_tx(spi, frame); 586 priv->tx_busy = true; 587 can_put_echo_skb(priv->tx_skb, net, 0, 0); 588 priv->tx_skb = NULL; 589 } 590 } 591 mutex_unlock(&priv->hi3110_lock); 592} 593 594static void hi3110_restart_work_handler(struct work_struct *ws) 595{ 596 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv, 597 restart_work); 598 struct spi_device *spi = priv->spi; 599 struct net_device *net = priv->net; 600 601 mutex_lock(&priv->hi3110_lock); 602 if (priv->after_suspend) { 603 hi3110_hw_reset(spi); 604 hi3110_setup(net); 605 if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) { 606 hi3110_set_normal_mode(spi); 607 } else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { 608 netif_device_attach(net); 609 hi3110_clean(net); 610 hi3110_set_normal_mode(spi); 611 netif_wake_queue(net); 612 } else { 613 hi3110_hw_sleep(spi); 614 } 615 priv->after_suspend = 0; 616 priv->force_quit = 0; 617 } 618 619 if (priv->restart_tx) { 620 priv->restart_tx = 0; 621 hi3110_hw_reset(spi); 622 hi3110_setup(net); 623 hi3110_clean(net); 624 hi3110_set_normal_mode(spi); 625 netif_wake_queue(net); 626 } 627 mutex_unlock(&priv->hi3110_lock); 628} 629 630static irqreturn_t hi3110_can_ist(int irq, void *dev_id) 631{ 632 struct hi3110_priv *priv = dev_id; 633 struct spi_device *spi = priv->spi; 634 struct net_device *net = priv->net; 635 636 mutex_lock(&priv->hi3110_lock); 637 638 while (!priv->force_quit) { 639 enum can_state new_state; 640 u8 intf, eflag, statf; 641 642 while (!(HI3110_STAT_RXFMTY & 643 (statf = hi3110_read(spi, HI3110_READ_STATF)))) { 644 hi3110_hw_rx(spi); 645 } 646 647 intf = hi3110_read(spi, HI3110_READ_INTF); 648 eflag = hi3110_read(spi, HI3110_READ_ERR); 649 /* Update can state */ 650 if (eflag & HI3110_ERR_BUSOFF) 651 new_state = CAN_STATE_BUS_OFF; 652 else if (eflag & HI3110_ERR_PASSIVE_MASK) 653 new_state = CAN_STATE_ERROR_PASSIVE; 654 else if (statf & HI3110_STAT_ERRW) 655 new_state = CAN_STATE_ERROR_WARNING; 656 else 657 new_state = CAN_STATE_ERROR_ACTIVE; 658 659 if (new_state != priv->can.state) { 660 struct can_frame *cf; 661 struct sk_buff *skb; 662 enum can_state rx_state, tx_state; 663 u8 rxerr, txerr; 664 665 skb = alloc_can_err_skb(net, &cf); 666 if (!skb) 667 break; 668 669 txerr = hi3110_read(spi, HI3110_READ_TEC); 670 rxerr = hi3110_read(spi, HI3110_READ_REC); 671 tx_state = txerr >= rxerr ? new_state : 0; 672 rx_state = txerr <= rxerr ? new_state : 0; 673 can_change_state(net, cf, tx_state, rx_state); 674 netif_rx(skb); 675 676 if (new_state == CAN_STATE_BUS_OFF) { 677 can_bus_off(net); 678 if (priv->can.restart_ms == 0) { 679 priv->force_quit = 1; 680 hi3110_hw_sleep(spi); 681 break; 682 } 683 } else { 684 cf->can_id |= CAN_ERR_CNT; 685 cf->data[6] = txerr; 686 cf->data[7] = rxerr; 687 } 688 } 689 690 /* Update bus errors */ 691 if ((intf & HI3110_INT_BUSERR) && 692 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { 693 struct can_frame *cf; 694 struct sk_buff *skb; 695 696 /* Check for protocol errors */ 697 if (eflag & HI3110_ERR_PROTOCOL_MASK) { 698 skb = alloc_can_err_skb(net, &cf); 699 if (!skb) 700 break; 701 702 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 703 priv->can.can_stats.bus_error++; 704 priv->net->stats.rx_errors++; 705 if (eflag & HI3110_ERR_BITERR) 706 cf->data[2] |= CAN_ERR_PROT_BIT; 707 else if (eflag & HI3110_ERR_FRMERR) 708 cf->data[2] |= CAN_ERR_PROT_FORM; 709 else if (eflag & HI3110_ERR_STUFERR) 710 cf->data[2] |= CAN_ERR_PROT_STUFF; 711 else if (eflag & HI3110_ERR_CRCERR) 712 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 713 else if (eflag & HI3110_ERR_ACKERR) 714 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 715 716 cf->data[6] = hi3110_read(spi, HI3110_READ_TEC); 717 cf->data[7] = hi3110_read(spi, HI3110_READ_REC); 718 netdev_dbg(priv->net, "Bus Error\n"); 719 netif_rx(skb); 720 } 721 } 722 723 if (priv->tx_busy && statf & HI3110_STAT_TXMTY) { 724 net->stats.tx_packets++; 725 net->stats.tx_bytes += can_get_echo_skb(net, 0, NULL); 726 priv->tx_busy = false; 727 netif_wake_queue(net); 728 } 729 730 if (intf == 0) 731 break; 732 } 733 mutex_unlock(&priv->hi3110_lock); 734 return IRQ_HANDLED; 735} 736 737static int hi3110_open(struct net_device *net) 738{ 739 struct hi3110_priv *priv = netdev_priv(net); 740 struct spi_device *spi = priv->spi; 741 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_HIGH; 742 int ret; 743 744 ret = open_candev(net); 745 if (ret) 746 return ret; 747 748 mutex_lock(&priv->hi3110_lock); 749 hi3110_power_enable(priv->transceiver, 1); 750 751 priv->force_quit = 0; 752 priv->tx_skb = NULL; 753 priv->tx_busy = false; 754 755 ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist, 756 flags, DEVICE_NAME, priv); 757 if (ret) { 758 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); 759 goto out_close; 760 } 761 762 priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM, 763 0); 764 if (!priv->wq) { 765 ret = -ENOMEM; 766 goto out_free_irq; 767 } 768 INIT_WORK(&priv->tx_work, hi3110_tx_work_handler); 769 INIT_WORK(&priv->restart_work, hi3110_restart_work_handler); 770 771 ret = hi3110_hw_reset(spi); 772 if (ret) 773 goto out_free_wq; 774 775 ret = hi3110_setup(net); 776 if (ret) 777 goto out_free_wq; 778 779 ret = hi3110_set_normal_mode(spi); 780 if (ret) 781 goto out_free_wq; 782 783 netif_wake_queue(net); 784 mutex_unlock(&priv->hi3110_lock); 785 786 return 0; 787 788 out_free_wq: 789 destroy_workqueue(priv->wq); 790 out_free_irq: 791 free_irq(spi->irq, priv); 792 hi3110_hw_sleep(spi); 793 out_close: 794 hi3110_power_enable(priv->transceiver, 0); 795 close_candev(net); 796 mutex_unlock(&priv->hi3110_lock); 797 return ret; 798} 799 800static const struct net_device_ops hi3110_netdev_ops = { 801 .ndo_open = hi3110_open, 802 .ndo_stop = hi3110_stop, 803 .ndo_start_xmit = hi3110_hard_start_xmit, 804}; 805 806static const struct ethtool_ops hi3110_ethtool_ops = { 807 .get_ts_info = ethtool_op_get_ts_info, 808}; 809 810static const struct of_device_id hi3110_of_match[] = { 811 { 812 .compatible = "holt,hi3110", 813 .data = (void *)CAN_HI3110_HI3110, 814 }, 815 { } 816}; 817MODULE_DEVICE_TABLE(of, hi3110_of_match); 818 819static const struct spi_device_id hi3110_id_table[] = { 820 { 821 .name = "hi3110", 822 .driver_data = (kernel_ulong_t)CAN_HI3110_HI3110, 823 }, 824 { } 825}; 826MODULE_DEVICE_TABLE(spi, hi3110_id_table); 827 828static int hi3110_can_probe(struct spi_device *spi) 829{ 830 struct device *dev = &spi->dev; 831 struct net_device *net; 832 struct hi3110_priv *priv; 833 const void *match; 834 struct clk *clk; 835 u32 freq; 836 int ret; 837 838 clk = devm_clk_get_optional(&spi->dev, NULL); 839 if (IS_ERR(clk)) 840 return dev_err_probe(dev, PTR_ERR(clk), "no CAN clock source defined\n"); 841 842 if (clk) { 843 freq = clk_get_rate(clk); 844 } else { 845 ret = device_property_read_u32(dev, "clock-frequency", &freq); 846 if (ret) 847 return dev_err_probe(dev, ret, "Failed to get clock-frequency!\n"); 848 } 849 850 /* Sanity check */ 851 if (freq > 40000000) 852 return -ERANGE; 853 854 /* Allocate can/net device */ 855 net = alloc_candev(sizeof(struct hi3110_priv), HI3110_TX_ECHO_SKB_MAX); 856 if (!net) 857 return -ENOMEM; 858 859 ret = clk_prepare_enable(clk); 860 if (ret) 861 goto out_free; 862 863 net->netdev_ops = &hi3110_netdev_ops; 864 net->ethtool_ops = &hi3110_ethtool_ops; 865 net->flags |= IFF_ECHO; 866 867 priv = netdev_priv(net); 868 priv->can.bittiming_const = &hi3110_bittiming_const; 869 priv->can.do_set_mode = hi3110_do_set_mode; 870 priv->can.do_get_berr_counter = hi3110_get_berr_counter; 871 priv->can.clock.freq = freq / 2; 872 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 873 CAN_CTRLMODE_LOOPBACK | 874 CAN_CTRLMODE_LISTENONLY | 875 CAN_CTRLMODE_BERR_REPORTING; 876 877 match = device_get_match_data(dev); 878 if (match) 879 priv->model = (enum hi3110_model)(uintptr_t)match; 880 else 881 priv->model = spi_get_device_id(spi)->driver_data; 882 priv->net = net; 883 priv->clk = clk; 884 885 spi_set_drvdata(spi, priv); 886 887 /* Configure the SPI bus */ 888 spi->bits_per_word = 8; 889 ret = spi_setup(spi); 890 if (ret) 891 goto out_clk; 892 893 priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); 894 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 895 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || 896 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) { 897 ret = -EPROBE_DEFER; 898 goto out_clk; 899 } 900 901 ret = hi3110_power_enable(priv->power, 1); 902 if (ret) 903 goto out_clk; 904 905 priv->spi = spi; 906 mutex_init(&priv->hi3110_lock); 907 908 priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, 909 GFP_KERNEL); 910 if (!priv->spi_tx_buf) { 911 ret = -ENOMEM; 912 goto error_probe; 913 } 914 priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, 915 GFP_KERNEL); 916 917 if (!priv->spi_rx_buf) { 918 ret = -ENOMEM; 919 goto error_probe; 920 } 921 922 SET_NETDEV_DEV(net, &spi->dev); 923 924 ret = hi3110_hw_probe(spi); 925 if (ret) { 926 dev_err_probe(dev, ret, "Cannot initialize %x. Wrong wiring?\n", priv->model); 927 goto error_probe; 928 } 929 hi3110_hw_sleep(spi); 930 931 ret = register_candev(net); 932 if (ret) 933 goto error_probe; 934 935 netdev_info(net, "%x successfully initialized.\n", priv->model); 936 937 return 0; 938 939 error_probe: 940 hi3110_power_enable(priv->power, 0); 941 942 out_clk: 943 clk_disable_unprepare(clk); 944 945 out_free: 946 free_candev(net); 947 948 return dev_err_probe(dev, ret, "Probe failed\n"); 949} 950 951static void hi3110_can_remove(struct spi_device *spi) 952{ 953 struct hi3110_priv *priv = spi_get_drvdata(spi); 954 struct net_device *net = priv->net; 955 956 unregister_candev(net); 957 958 hi3110_power_enable(priv->power, 0); 959 960 clk_disable_unprepare(priv->clk); 961 962 free_candev(net); 963} 964 965static int __maybe_unused hi3110_can_suspend(struct device *dev) 966{ 967 struct spi_device *spi = to_spi_device(dev); 968 struct hi3110_priv *priv = spi_get_drvdata(spi); 969 struct net_device *net = priv->net; 970 971 priv->force_quit = 1; 972 disable_irq(spi->irq); 973 974 /* Note: at this point neither IST nor workqueues are running. 975 * open/stop cannot be called anyway so locking is not needed 976 */ 977 if (netif_running(net)) { 978 netif_device_detach(net); 979 980 hi3110_hw_sleep(spi); 981 hi3110_power_enable(priv->transceiver, 0); 982 priv->after_suspend = HI3110_AFTER_SUSPEND_UP; 983 } else { 984 priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN; 985 } 986 987 if (!IS_ERR_OR_NULL(priv->power)) { 988 regulator_disable(priv->power); 989 priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER; 990 } 991 992 return 0; 993} 994 995static int __maybe_unused hi3110_can_resume(struct device *dev) 996{ 997 struct spi_device *spi = to_spi_device(dev); 998 struct hi3110_priv *priv = spi_get_drvdata(spi); 999 1000 if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER) 1001 hi3110_power_enable(priv->power, 1); 1002 1003 if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { 1004 hi3110_power_enable(priv->transceiver, 1); 1005 queue_work(priv->wq, &priv->restart_work); 1006 } else { 1007 priv->after_suspend = 0; 1008 } 1009 1010 priv->force_quit = 0; 1011 enable_irq(spi->irq); 1012 return 0; 1013} 1014 1015static SIMPLE_DEV_PM_OPS(hi3110_can_pm_ops, hi3110_can_suspend, hi3110_can_resume); 1016 1017static struct spi_driver hi3110_can_driver = { 1018 .driver = { 1019 .name = DEVICE_NAME, 1020 .of_match_table = hi3110_of_match, 1021 .pm = &hi3110_can_pm_ops, 1022 }, 1023 .id_table = hi3110_id_table, 1024 .probe = hi3110_can_probe, 1025 .remove = hi3110_can_remove, 1026}; 1027 1028module_spi_driver(hi3110_can_driver); 1029 1030MODULE_AUTHOR("Akshay Bhat <akshay.bhat@timesys.com>"); 1031MODULE_AUTHOR("Casey Fitzpatrick <casey.fitzpatrick@timesys.com>"); 1032MODULE_DESCRIPTION("Holt HI-3110 CAN driver"); 1033MODULE_LICENSE("GPL v2"); 1034