1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ck804xrom.c
4 *
5 * Normal mappings of chips in physical memory
6 *
7 * Dave Olsen <dolsen@lnxi.com>
8 * Ryan Jackson <rjackson@lnxi.com>
9 */
10
11#include <linux/module.h>
12#include <linux/types.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <asm/io.h>
17#include <linux/mtd/mtd.h>
18#include <linux/mtd/map.h>
19#include <linux/mtd/cfi.h>
20#include <linux/mtd/flashchip.h>
21#include <linux/pci.h>
22#include <linux/pci_ids.h>
23#include <linux/list.h>
24
25
26#define MOD_NAME KBUILD_BASENAME
27
28#define ADDRESS_NAME_LEN 18
29
30#define ROM_PROBE_STEP_SIZE (64*1024)
31
32#define DEV_CK804 1
33#define DEV_MCP55 2
34
35struct ck804xrom_window {
36	void __iomem *virt;
37	unsigned long phys;
38	unsigned long size;
39	struct list_head maps;
40	struct resource rsrc;
41	struct pci_dev *pdev;
42};
43
44struct ck804xrom_map_info {
45	struct list_head list;
46	struct map_info map;
47	struct mtd_info *mtd;
48	struct resource rsrc;
49	char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];
50};
51
52/*
53 * The following applies to ck804 only:
54 * The 2 bits controlling the window size are often set to allow reading
55 * the BIOS, but too small to allow writing, since the lock registers are
56 * 4MiB lower in the address space than the data.
57 *
58 * This is intended to prevent flashing the bios, perhaps accidentally.
59 *
60 * This parameter allows the normal driver to override the BIOS settings.
61 *
62 * The bits are 6 and 7.  If both bits are set, it is a 5MiB window.
63 * If only the 7 Bit is set, it is a 4MiB window.  Otherwise, a
64 * 64KiB window.
65 *
66 * The following applies to mcp55 only:
67 * The 15 bits controlling the window size are distributed as follows:
68 * byte @0x88: bit 0..7
69 * byte @0x8c: bit 8..15
70 * word @0x90: bit 16..30
71 * If all bits are enabled, we have a 16? MiB window
72 * Please set win_size_bits to 0x7fffffff if you actually want to do something
73 */
74static uint win_size_bits = 0;
75module_param(win_size_bits, uint, 0);
76MODULE_PARM_DESC(win_size_bits, "ROM window size bits override, normally set by BIOS.");
77
78static struct ck804xrom_window ck804xrom_window = {
79	.maps = LIST_HEAD_INIT(ck804xrom_window.maps),
80};
81
82static void ck804xrom_cleanup(struct ck804xrom_window *window)
83{
84	struct ck804xrom_map_info *map, *scratch;
85	u8 byte;
86
87	if (window->pdev) {
88		/* Disable writes through the rom window */
89		pci_read_config_byte(window->pdev, 0x6d, &byte);
90		pci_write_config_byte(window->pdev, 0x6d, byte & ~1);
91	}
92
93	/* Free all of the mtd devices */
94	list_for_each_entry_safe(map, scratch, &window->maps, list) {
95		if (map->rsrc.parent)
96			release_resource(&map->rsrc);
97
98		mtd_device_unregister(map->mtd);
99		map_destroy(map->mtd);
100		list_del(&map->list);
101		kfree(map);
102	}
103	if (window->rsrc.parent)
104		release_resource(&window->rsrc);
105
106	if (window->virt) {
107		iounmap(window->virt);
108		window->virt = NULL;
109		window->phys = 0;
110		window->size = 0;
111	}
112	pci_dev_put(window->pdev);
113}
114
115
116static int __init ck804xrom_init_one(struct pci_dev *pdev,
117				     const struct pci_device_id *ent)
118{
119	static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };
120	u8 byte;
121	u16 word;
122	struct ck804xrom_window *window = &ck804xrom_window;
123	struct ck804xrom_map_info *map = NULL;
124	unsigned long map_top;
125
126	/* Remember the pci dev I find the window in */
127	window->pdev = pci_dev_get(pdev);
128
129	switch (ent->driver_data) {
130	case DEV_CK804:
131		/* Enable the selected rom window.  This is often incorrectly
132		 * set up by the BIOS, and the 4MiB offset for the lock registers
133		 * requires the full 5MiB of window space.
134		 *
135		 * This 'write, then read' approach leaves the bits for
136		 * other uses of the hardware info.
137		 */
138		pci_read_config_byte(pdev, 0x88, &byte);
139		pci_write_config_byte(pdev, 0x88, byte | win_size_bits );
140
141		/* Assume the rom window is properly setup, and find it's size */
142		pci_read_config_byte(pdev, 0x88, &byte);
143
144		if ((byte & ((1<<7)|(1<<6))) == ((1<<7)|(1<<6)))
145			window->phys = 0xffb00000; /* 5MiB */
146		else if ((byte & (1<<7)) == (1<<7))
147			window->phys = 0xffc00000; /* 4MiB */
148		else
149			window->phys = 0xffff0000; /* 64KiB */
150		break;
151
152	case DEV_MCP55:
153		pci_read_config_byte(pdev, 0x88, &byte);
154		pci_write_config_byte(pdev, 0x88, byte | (win_size_bits & 0xff));
155
156		pci_read_config_byte(pdev, 0x8c, &byte);
157		pci_write_config_byte(pdev, 0x8c, byte | ((win_size_bits & 0xff00) >> 8));
158
159		pci_read_config_word(pdev, 0x90, &word);
160		pci_write_config_word(pdev, 0x90, word | ((win_size_bits & 0x7fff0000) >> 16));
161
162		window->phys = 0xff000000; /* 16MiB, hardcoded for now */
163		break;
164	}
165
166	window->size = 0xffffffffUL - window->phys + 1UL;
167
168	/*
169	 * Try to reserve the window mem region.  If this fails then
170	 * it is likely due to a fragment of the window being
171	 * "reserved" by the BIOS.  In the case that the
172	 * request_mem_region() fails then once the rom size is
173	 * discovered we will try to reserve the unreserved fragment.
174	 */
175	window->rsrc.name = MOD_NAME;
176	window->rsrc.start = window->phys;
177	window->rsrc.end   = window->phys + window->size - 1;
178	window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
179	if (request_resource(&iomem_resource, &window->rsrc)) {
180		window->rsrc.parent = NULL;
181		printk(KERN_ERR MOD_NAME
182		       " %s(): Unable to register resource %pR - kernel bug?\n",
183			__func__, &window->rsrc);
184	}
185
186
187	/* Enable writes through the rom window */
188	pci_read_config_byte(pdev, 0x6d, &byte);
189	pci_write_config_byte(pdev, 0x6d, byte | 1);
190
191	/* FIXME handle registers 0x80 - 0x8C the bios region locks */
192
193	/* For write accesses caches are useless */
194	window->virt = ioremap(window->phys, window->size);
195	if (!window->virt) {
196		printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",
197			window->phys, window->size);
198		goto out;
199	}
200
201	/* Get the first address to look for a rom chip at */
202	map_top = window->phys;
203#if 1
204	/* The probe sequence run over the firmware hub lock
205	 * registers sets them to 0x7 (no access).
206	 * Probe at most the last 4MiB of the address space.
207	 */
208	if (map_top < 0xffc00000)
209		map_top = 0xffc00000;
210#endif
211	/* Loop  through and look for rom chips.  Since we don't know the
212	 * starting address for each chip, probe every ROM_PROBE_STEP_SIZE
213	 * bytes from the starting address of the window.
214	 */
215	while((map_top - 1) < 0xffffffffUL) {
216		struct cfi_private *cfi;
217		unsigned long offset;
218		int i;
219
220		if (!map) {
221			map = kmalloc(sizeof(*map), GFP_KERNEL);
222			if (!map)
223				goto out;
224		}
225		memset(map, 0, sizeof(*map));
226		INIT_LIST_HEAD(&map->list);
227		map->map.name = map->map_name;
228		map->map.phys = map_top;
229		offset = map_top - window->phys;
230		map->map.virt = (void __iomem *)
231			(((unsigned long)(window->virt)) + offset);
232		map->map.size = 0xffffffffUL - map_top + 1UL;
233		/* Set the name of the map to the address I am trying */
234		sprintf(map->map_name, "%s @%08Lx",
235			MOD_NAME, (unsigned long long)map->map.phys);
236
237		/* There is no generic VPP support */
238		for(map->map.bankwidth = 32; map->map.bankwidth;
239			map->map.bankwidth >>= 1)
240		{
241			char **probe_type;
242			/* Skip bankwidths that are not supported */
243			if (!map_bankwidth_supported(map->map.bankwidth))
244				continue;
245
246			/* Setup the map methods */
247			simple_map_init(&map->map);
248
249			/* Try all of the probe methods */
250			probe_type = rom_probe_types;
251			for(; *probe_type; probe_type++) {
252				map->mtd = do_map_probe(*probe_type, &map->map);
253				if (map->mtd)
254					goto found;
255			}
256		}
257		map_top += ROM_PROBE_STEP_SIZE;
258		continue;
259	found:
260		/* Trim the size if we are larger than the map */
261		if (map->mtd->size > map->map.size) {
262			printk(KERN_WARNING MOD_NAME
263				" rom(%llu) larger than window(%lu). fixing...\n",
264				(unsigned long long)map->mtd->size, map->map.size);
265			map->mtd->size = map->map.size;
266		}
267		if (window->rsrc.parent) {
268			/*
269			 * Registering the MTD device in iomem may not be possible
270			 * if there is a BIOS "reserved" and BUSY range.  If this
271			 * fails then continue anyway.
272			 */
273			map->rsrc.name  = map->map_name;
274			map->rsrc.start = map->map.phys;
275			map->rsrc.end   = map->map.phys + map->mtd->size - 1;
276			map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
277			if (request_resource(&window->rsrc, &map->rsrc)) {
278				printk(KERN_ERR MOD_NAME
279					": cannot reserve MTD resource\n");
280				map->rsrc.parent = NULL;
281			}
282		}
283
284		/* Make the whole region visible in the map */
285		map->map.virt = window->virt;
286		map->map.phys = window->phys;
287		cfi = map->map.fldrv_priv;
288		for(i = 0; i < cfi->numchips; i++)
289			cfi->chips[i].start += offset;
290
291		/* Now that the mtd devices is complete claim and export it */
292		map->mtd->owner = THIS_MODULE;
293		if (mtd_device_register(map->mtd, NULL, 0)) {
294			map_destroy(map->mtd);
295			map->mtd = NULL;
296			goto out;
297		}
298
299
300		/* Calculate the new value of map_top */
301		map_top += map->mtd->size;
302
303		/* File away the map structure */
304		list_add(&map->list, &window->maps);
305		map = NULL;
306	}
307
308 out:
309	/* Free any left over map structures */
310	kfree(map);
311
312	/* See if I have any map structures */
313	if (list_empty(&window->maps)) {
314		ck804xrom_cleanup(window);
315		return -ENODEV;
316	}
317	return 0;
318}
319
320
321static void ck804xrom_remove_one(struct pci_dev *pdev)
322{
323	struct ck804xrom_window *window = &ck804xrom_window;
324
325	ck804xrom_cleanup(window);
326}
327
328static const struct pci_device_id ck804xrom_pci_tbl[] = {
329	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0051), .driver_data = DEV_CK804 },
330	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0360), .driver_data = DEV_MCP55 },
331	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0361), .driver_data = DEV_MCP55 },
332	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0362), .driver_data = DEV_MCP55 },
333	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0363), .driver_data = DEV_MCP55 },
334	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0364), .driver_data = DEV_MCP55 },
335	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0365), .driver_data = DEV_MCP55 },
336	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0366), .driver_data = DEV_MCP55 },
337	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0367), .driver_data = DEV_MCP55 },
338	{ 0, }
339};
340
341#if 0
342MODULE_DEVICE_TABLE(pci, ck804xrom_pci_tbl);
343
344static struct pci_driver ck804xrom_driver = {
345	.name =		MOD_NAME,
346	.id_table =	ck804xrom_pci_tbl,
347	.probe =	ck804xrom_init_one,
348	.remove =	ck804xrom_remove_one,
349};
350#endif
351
352static int __init init_ck804xrom(void)
353{
354	struct pci_dev *pdev;
355	const struct pci_device_id *id;
356	int retVal;
357	pdev = NULL;
358
359	for(id = ck804xrom_pci_tbl; id->vendor; id++) {
360		pdev = pci_get_device(id->vendor, id->device, NULL);
361		if (pdev)
362			break;
363	}
364	if (pdev) {
365		retVal = ck804xrom_init_one(pdev, id);
366		pci_dev_put(pdev);
367		return retVal;
368	}
369	return -ENXIO;
370#if 0
371	return pci_register_driver(&ck804xrom_driver);
372#endif
373}
374
375static void __exit cleanup_ck804xrom(void)
376{
377	ck804xrom_remove_one(ck804xrom_window.pdev);
378}
379
380module_init(init_ck804xrom);
381module_exit(cleanup_ck804xrom);
382
383MODULE_LICENSE("GPL");
384MODULE_AUTHOR("Eric Biederman <ebiederman@lnxi.com>, Dave Olsen <dolsen@lnxi.com>");
385MODULE_DESCRIPTION("MTD map driver for BIOS chips on the Nvidia ck804 southbridge");
386
387