1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2016 Marvell, All Rights Reserved.
4 *
5 * Author:	Hu Ziji <huziji@marvell.com>
6 * Date:	2016-8-24
7 */
8#ifndef SDHCI_XENON_H_
9#define SDHCI_XENON_H_
10
11/* Register Offset of Xenon SDHC self-defined register */
12#define XENON_SYS_CFG_INFO			0x0104
13#define XENON_SLOT_TYPE_SDIO_SHIFT		24
14#define XENON_NR_SUPPORTED_SLOT_MASK		0x7
15
16#define XENON_SYS_OP_CTRL			0x0108
17#define XENON_AUTO_CLKGATE_DISABLE_MASK		BIT(20)
18#define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT	8
19#define XENON_SLOT_ENABLE_SHIFT			0
20
21#define XENON_SYS_EXT_OP_CTRL			0x010C
22#define XENON_MASK_CMD_CONFLICT_ERR		BIT(8)
23
24#define XENON_SLOT_OP_STATUS_CTRL		0x0128
25#define XENON_TUN_CONSECUTIVE_TIMES_SHIFT	16
26#define XENON_TUN_CONSECUTIVE_TIMES_MASK	0x7
27#define XENON_TUN_CONSECUTIVE_TIMES		0x4
28#define XENON_TUNING_STEP_SHIFT			12
29#define XENON_TUNING_STEP_MASK			0xF
30#define XENON_TUNING_STEP_DIVIDER		BIT(6)
31
32#define XENON_SLOT_EMMC_CTRL			0x0130
33#define XENON_ENABLE_RESP_STROBE		BIT(25)
34#define XENON_ENABLE_DATA_STROBE		BIT(24)
35
36#define XENON_SLOT_RETUNING_REQ_CTRL		0x0144
37/* retuning compatible */
38#define XENON_RETUNING_COMPATIBLE		0x1
39
40#define XENON_SLOT_EXT_PRESENT_STATE		0x014C
41#define XENON_DLL_LOCK_STATE			0x1
42
43#define XENON_SLOT_DLL_CUR_DLY_VAL		0x0150
44
45/* Tuning Parameter */
46#define XENON_TMR_RETUN_NO_PRESENT		0xF
47#define XENON_DEF_TUNING_COUNT			0x9
48
49#define XENON_DEFAULT_SDCLK_FREQ		400000
50#define XENON_LOWEST_SDCLK_FREQ			100000
51
52/* Xenon specific Mode Select value */
53#define XENON_CTRL_HS200			0x5
54#define XENON_CTRL_HS400			0x6
55
56enum xenon_variant {
57	XENON_A3700,
58	XENON_AP806,
59	XENON_AP807,
60	XENON_CP110,
61	XENON_AC5
62};
63
64struct xenon_priv {
65	unsigned char	tuning_count;
66	/* idx of SDHC */
67	u8		sdhc_id;
68
69	/*
70	 * eMMC/SD/SDIO require different register settings.
71	 * Xenon driver has to recognize card type
72	 * before mmc_host->card is not available.
73	 * This field records the card type during init.
74	 * It is updated in xenon_init_card().
75	 *
76	 * It is only valid during initialization after it is updated.
77	 * Do not access this variable in normal transfers after
78	 * initialization completes.
79	 */
80	unsigned int	init_card_type;
81
82	/*
83	 * The bus_width, timing, and clock fields in below
84	 * record the current ios setting of Xenon SDHC.
85	 * Driver will adjust PHY setting if any change to
86	 * ios affects PHY timing.
87	 */
88	unsigned char	bus_width;
89	unsigned char	timing;
90	unsigned int	clock;
91	struct clk      *axi_clk;
92
93	int		phy_type;
94	/*
95	 * Contains board-specific PHY parameters
96	 * passed from device tree.
97	 */
98	void		*phy_params;
99	struct xenon_emmc_phy_regs *emmc_phy_regs;
100	bool restore_needed;
101	enum xenon_variant hw_version;
102};
103
104int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
105int xenon_phy_parse_params(struct device *dev,
106			   struct sdhci_host *host);
107void xenon_soc_pad_ctrl(struct sdhci_host *host,
108			unsigned char signal_voltage);
109#endif
110