1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for Amlogic Meson IR remote receiver 4 * 5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6 */ 7 8#include <linux/device.h> 9#include <linux/err.h> 10#include <linux/interrupt.h> 11#include <linux/io.h> 12#include <linux/module.h> 13#include <linux/of.h> 14#include <linux/platform_device.h> 15#include <linux/spinlock.h> 16#include <linux/bitfield.h> 17#include <linux/regmap.h> 18 19#include <media/rc-core.h> 20 21#define DRIVER_NAME "meson-ir" 22 23#define IR_DEC_LDR_ACTIVE 0x00 24#define IR_DEC_LDR_ACTIVE_MAX GENMASK(28, 16) 25#define IR_DEC_LDR_ACTIVE_MIN GENMASK(12, 0) 26#define IR_DEC_LDR_IDLE 0x04 27#define IR_DEC_LDR_IDLE_MAX GENMASK(28, 16) 28#define IR_DEC_LDR_IDLE_MIN GENMASK(12, 0) 29#define IR_DEC_LDR_REPEAT 0x08 30#define IR_DEC_LDR_REPEAT_MAX GENMASK(25, 16) 31#define IR_DEC_LDR_REPEAT_MIN GENMASK(9, 0) 32#define IR_DEC_BIT_0 0x0c 33#define IR_DEC_BIT_0_MAX GENMASK(25, 16) 34#define IR_DEC_BIT_0_MIN GENMASK(9, 0) 35#define IR_DEC_REG0 0x10 36#define IR_DEC_REG0_FILTER GENMASK(30, 28) 37#define IR_DEC_REG0_FRAME_TIME_MAX GENMASK(24, 12) 38#define IR_DEC_REG0_BASE_TIME GENMASK(11, 0) 39#define IR_DEC_FRAME 0x14 40#define IR_DEC_STATUS 0x18 41#define IR_DEC_STATUS_BIT_1_ENABLE BIT(30) 42#define IR_DEC_STATUS_BIT_1_MAX GENMASK(29, 20) 43#define IR_DEC_STATUS_BIT_1_MIN GENMASK(19, 10) 44#define IR_DEC_STATUS_PULSE BIT(8) 45#define IR_DEC_STATUS_BUSY BIT(7) 46#define IR_DEC_STATUS_FRAME_STATUS GENMASK(3, 0) 47#define IR_DEC_REG1 0x1c 48#define IR_DEC_REG1_TIME_IV GENMASK(28, 16) 49#define IR_DEC_REG1_FRAME_LEN GENMASK(13, 8) 50#define IR_DEC_REG1_ENABLE BIT(15) 51#define IR_DEC_REG1_HOLD_CODE BIT(6) 52#define IR_DEC_REG1_IRQSEL GENMASK(3, 2) 53#define IR_DEC_REG1_RESET BIT(0) 54/* Meson 6b uses REG1 to configure IR mode */ 55#define IR_DEC_REG1_MODE GENMASK(8, 7) 56 57/* The following registers are only available on Meson 8b and newer */ 58#define IR_DEC_REG2 0x20 59#define IR_DEC_REG2_TICK_MODE BIT(15) 60#define IR_DEC_REG2_REPEAT_COUNTER BIT(13) 61#define IR_DEC_REG2_REPEAT_TIME BIT(12) 62#define IR_DEC_REG2_COMPARE_FRAME BIT(11) 63#define IR_DEC_REG2_BIT_ORDER BIT(8) 64/* Meson 8b / GXBB use REG2 to configure IR mode */ 65#define IR_DEC_REG2_MODE GENMASK(3, 0) 66#define IR_DEC_DURATN2 0x24 67#define IR_DEC_DURATN2_MAX GENMASK(25, 16) 68#define IR_DEC_DURATN2_MIN GENMASK(9, 0) 69#define IR_DEC_DURATN3 0x28 70#define IR_DEC_DURATN3_MAX GENMASK(25, 16) 71#define IR_DEC_DURATN3_MIN GENMASK(9, 0) 72#define IR_DEC_FRAME1 0x2c 73 74#define FRAME_MSB_FIRST true 75#define FRAME_LSB_FIRST false 76 77#define DEC_MODE_NEC 0x0 78#define DEC_MODE_RAW 0x2 79#define DEC_MODE_RC6 0x9 80#define DEC_MODE_XMP 0xE 81#define DEC_MODE_UNKNOW 0xFF 82 83#define DEC_STATUS_VALID BIT(3) 84#define DEC_STATUS_DATA_CODE_ERR BIT(2) 85#define DEC_STATUS_CUSTOM_CODE_ERR BIT(1) 86#define DEC_STATUS_REPEAT BIT(0) 87 88#define IRQSEL_DEC_MODE 0 89#define IRQSEL_RISE_FALL 1 90#define IRQSEL_FALL 2 91#define IRQSEL_RISE 3 92 93#define MESON_RAW_TRATE 10 /* us */ 94#define MESON_HW_TRATE 20 /* us */ 95 96/** 97 * struct meson_ir_protocol - describe IR Protocol parameter 98 * 99 * @hw_protocol: select IR Protocol from IR Controller 100 * @repeat_counter_enable: enable frame-to-frame time counter, it should work 101 * with @repeat_compare_enable to detect the repeat frame 102 * @repeat_check_enable: enable repeat time check for repeat detection 103 * @repeat_compare_enable: enable to compare frame for repeat frame detection. 104 * Some IR Protocol send the same data as repeat frame. 105 * In this case, it should work with 106 * @repeat_counter_enable to detect the repeat frame. 107 * @bit_order: bit order, LSB or MSB 108 * @bit1_match_enable: enable to check bit 1 109 * @hold_code_enable: hold frame code in register IR_DEC_FRAME1, the new one 110 * frame code will not be store in IR_DEC_FRAME1. 111 * until IR_DEC_FRAME1 has been read 112 * @count_tick_mode: increasing time unit of frame-to-frame time counter. 113 * 0 = 100us, 1 = 10us 114 * @code_length: length (N-1) of data frame 115 * @frame_time_max: max time for whole frame. Unit: MESON_HW_TRATE 116 * @leader_active_max: max time for NEC/RC6 leader active part. Unit: MESON_HW_TRATE 117 * @leader_active_min: min time for NEC/RC6 leader active part. Unit: MESON_HW_TRATE 118 * @leader_idle_max: max time for NEC/RC6 leader idle part. Unit: MESON_HW_TRATE 119 * @leader_idle_min: min time for NEC/RC6 leader idle part. Unit: MESON_HW_TRATE 120 * @repeat_leader_max: max time for NEC repeat leader idle part. Unit: MESON_HW_TRATE 121 * @repeat_leader_min: min time for NEC repeat leader idle part. Unit: MESON_HW_TRATE 122 * @bit0_max: max time for NEC Logic '0', half of RC6 trailer bit, XMP Logic '00' 123 * @bit0_min: min time for NEC Logic '0', half of RC6 trailer bit, XMP Logic '00' 124 * @bit1_max: max time for NEC Logic '1', whole of RC6 trailer bit, XMP Logic '01' 125 * @bit1_min: min time for NEC Logic '1', whole of RC6 trailer bit, XMP Logic '01' 126 * @duration2_max: max time for half of RC6 normal bit, XMP Logic '10' 127 * @duration2_min: min time for half of RC6 normal bit, XMP Logic '10' 128 * @duration3_max: max time for whole of RC6 normal bit, XMP Logic '11' 129 * @duration3_min: min time for whole of RC6 normal bit, XMP Logic '11' 130 */ 131 132struct meson_ir_protocol { 133 u8 hw_protocol; 134 bool repeat_counter_enable; 135 bool repeat_check_enable; 136 bool repeat_compare_enable; 137 bool bit_order; 138 bool bit1_match_enable; 139 bool hold_code_enable; 140 bool count_tick_mode; 141 u8 code_length; 142 u16 frame_time_max; 143 u16 leader_active_max; 144 u16 leader_active_min; 145 u16 leader_idle_max; 146 u16 leader_idle_min; 147 u16 repeat_leader_max; 148 u16 repeat_leader_min; 149 u16 bit0_max; 150 u16 bit0_min; 151 u16 bit1_max; 152 u16 bit1_min; 153 u16 duration2_max; 154 u16 duration2_min; 155 u16 duration3_max; 156 u16 duration3_min; 157}; 158 159struct meson_ir_param { 160 bool support_hw_decoder; 161 unsigned int max_register; 162}; 163 164struct meson_ir { 165 const struct meson_ir_param *param; 166 struct regmap *reg; 167 struct rc_dev *rc; 168 spinlock_t lock; 169}; 170 171static struct regmap_config meson_ir_regmap_config = { 172 .reg_bits = 32, 173 .val_bits = 32, 174 .reg_stride = 4, 175}; 176 177static const struct meson_ir_protocol protocol_timings[] = { 178 /* protocol, repeat counter, repeat check, repeat compare, order */ 179 {DEC_MODE_NEC, false, false, false, FRAME_LSB_FIRST, 180 /* bit 1 match, hold code, count tick, len, frame time */ 181 true, false, false, 32, 4000, 182 /* leader active max/min, leader idle max/min, repeat leader max/min */ 183 500, 400, 300, 200, 150, 80, 184 /* bit0 max/min, bit1 max/min, duration2 max/min, duration3 max/min */ 185 72, 40, 134, 90, 0, 0, 0, 0} 186}; 187 188static void meson_ir_nec_handler(struct meson_ir *ir) 189{ 190 u32 code = 0; 191 u32 status = 0; 192 enum rc_proto proto; 193 194 regmap_read(ir->reg, IR_DEC_STATUS, &status); 195 196 if (status & DEC_STATUS_REPEAT) { 197 rc_repeat(ir->rc); 198 } else { 199 regmap_read(ir->reg, IR_DEC_FRAME, &code); 200 201 code = ir_nec_bytes_to_scancode(code, code >> 8, 202 code >> 16, code >> 24, &proto); 203 rc_keydown(ir->rc, proto, code, 0); 204 } 205} 206 207static void meson_ir_hw_handler(struct meson_ir *ir) 208{ 209 if (ir->rc->enabled_protocols & RC_PROTO_BIT_NEC) 210 meson_ir_nec_handler(ir); 211} 212 213static irqreturn_t meson_ir_irq(int irqno, void *dev_id) 214{ 215 struct meson_ir *ir = dev_id; 216 u32 duration, status; 217 struct ir_raw_event rawir = {}; 218 219 spin_lock(&ir->lock); 220 221 regmap_read(ir->reg, IR_DEC_STATUS, &status); 222 223 if (ir->rc->driver_type == RC_DRIVER_IR_RAW) { 224 rawir.pulse = !!(status & IR_DEC_STATUS_PULSE); 225 226 regmap_read(ir->reg, IR_DEC_REG1, &duration); 227 duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration); 228 rawir.duration = duration * MESON_RAW_TRATE; 229 230 ir_raw_event_store_with_timeout(ir->rc, &rawir); 231 } else if (ir->rc->driver_type == RC_DRIVER_SCANCODE) { 232 if (status & DEC_STATUS_VALID) 233 meson_ir_hw_handler(ir); 234 } 235 236 spin_unlock(&ir->lock); 237 238 return IRQ_HANDLED; 239} 240 241static int meson_ir_hw_decoder_init(struct rc_dev *dev, u64 *rc_type) 242{ 243 u8 protocol; 244 u32 regval; 245 int i; 246 unsigned long flags; 247 const struct meson_ir_protocol *timings; 248 struct meson_ir *ir = dev->priv; 249 250 if (*rc_type & RC_PROTO_BIT_NEC) 251 protocol = DEC_MODE_NEC; 252 else 253 return 0; 254 255 for (i = 0; i < ARRAY_SIZE(protocol_timings); i++) 256 if (protocol_timings[i].hw_protocol == protocol) 257 break; 258 259 if (i == ARRAY_SIZE(protocol_timings)) { 260 dev_err(&dev->dev, "hw protocol isn't supported: %d\n", 261 protocol); 262 return -EINVAL; 263 } 264 timings = &protocol_timings[i]; 265 266 spin_lock_irqsave(&ir->lock, flags); 267 268 /* Clear controller status */ 269 regmap_read(ir->reg, IR_DEC_STATUS, ®val); 270 regmap_read(ir->reg, IR_DEC_FRAME, ®val); 271 272 /* Reset ir decoder and disable decoder */ 273 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0); 274 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 275 IR_DEC_REG1_RESET); 276 277 /* Base time resolution, (19+1)*1us=20us */ 278 regval = FIELD_PREP(IR_DEC_REG0_BASE_TIME, MESON_HW_TRATE - 1); 279 regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, regval); 280 281 /* Monitor timing for input filter */ 282 regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_FILTER, 283 FIELD_PREP(IR_DEC_REG0_FILTER, 7)); 284 285 /* HW protocol */ 286 regval = FIELD_PREP(IR_DEC_REG2_MODE, timings->hw_protocol); 287 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE, regval); 288 289 /* Hold frame data until register was read */ 290 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_HOLD_CODE, 291 timings->hold_code_enable ? 292 IR_DEC_REG1_HOLD_CODE : 0); 293 294 /* Bit order */ 295 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_BIT_ORDER, 296 timings->bit_order ? IR_DEC_REG2_BIT_ORDER : 0); 297 298 /* Select tick mode */ 299 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_TICK_MODE, 300 timings->count_tick_mode ? 301 IR_DEC_REG2_TICK_MODE : 0); 302 303 /* 304 * Some protocols transmit the same data frame as repeat frame 305 * when the key is pressing. In this case, it could be detected as 306 * repeat frame if the repeat checker was enabled. 307 */ 308 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_REPEAT_COUNTER, 309 timings->repeat_counter_enable ? 310 IR_DEC_REG2_REPEAT_COUNTER : 0); 311 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_REPEAT_TIME, 312 timings->repeat_check_enable ? 313 IR_DEC_REG2_REPEAT_TIME : 0); 314 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_COMPARE_FRAME, 315 timings->repeat_compare_enable ? 316 IR_DEC_REG2_COMPARE_FRAME : 0); 317 318 /* 319 * FRAME_TIME_MAX should be larger than the time between 320 * data frame and repeat frame 321 */ 322 regval = FIELD_PREP(IR_DEC_REG0_FRAME_TIME_MAX, 323 timings->frame_time_max); 324 regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_FRAME_TIME_MAX, 325 regval); 326 327 /* Length(N-1) of data frame */ 328 regval = FIELD_PREP(IR_DEC_REG1_FRAME_LEN, timings->code_length - 1); 329 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_FRAME_LEN, regval); 330 331 /* Time for leader active part */ 332 regval = FIELD_PREP(IR_DEC_LDR_ACTIVE_MAX, 333 timings->leader_active_max) | 334 FIELD_PREP(IR_DEC_LDR_ACTIVE_MIN, 335 timings->leader_active_min); 336 regmap_update_bits(ir->reg, IR_DEC_LDR_ACTIVE, IR_DEC_LDR_ACTIVE_MAX | 337 IR_DEC_LDR_ACTIVE_MIN, regval); 338 339 /* Time for leader idle part */ 340 regval = FIELD_PREP(IR_DEC_LDR_IDLE_MAX, timings->leader_idle_max) | 341 FIELD_PREP(IR_DEC_LDR_IDLE_MIN, timings->leader_idle_min); 342 regmap_update_bits(ir->reg, IR_DEC_LDR_IDLE, 343 IR_DEC_LDR_IDLE_MAX | IR_DEC_LDR_IDLE_MIN, regval); 344 345 /* Time for repeat leader idle part */ 346 regval = FIELD_PREP(IR_DEC_LDR_REPEAT_MAX, timings->repeat_leader_max) | 347 FIELD_PREP(IR_DEC_LDR_REPEAT_MIN, timings->repeat_leader_min); 348 regmap_update_bits(ir->reg, IR_DEC_LDR_REPEAT, IR_DEC_LDR_REPEAT_MAX | 349 IR_DEC_LDR_REPEAT_MIN, regval); 350 351 /* 352 * NEC: Time for logic '0' 353 * RC6: Time for half of trailer bit 354 */ 355 regval = FIELD_PREP(IR_DEC_BIT_0_MAX, timings->bit0_max) | 356 FIELD_PREP(IR_DEC_BIT_0_MIN, timings->bit0_min); 357 regmap_update_bits(ir->reg, IR_DEC_BIT_0, 358 IR_DEC_BIT_0_MAX | IR_DEC_BIT_0_MIN, regval); 359 360 /* 361 * NEC: Time for logic '1' 362 * RC6: Time for whole of trailer bit 363 */ 364 regval = FIELD_PREP(IR_DEC_STATUS_BIT_1_MAX, timings->bit1_max) | 365 FIELD_PREP(IR_DEC_STATUS_BIT_1_MIN, timings->bit1_min); 366 regmap_update_bits(ir->reg, IR_DEC_STATUS, IR_DEC_STATUS_BIT_1_MAX | 367 IR_DEC_STATUS_BIT_1_MIN, regval); 368 369 /* Enable to match logic '1' */ 370 regmap_update_bits(ir->reg, IR_DEC_STATUS, IR_DEC_STATUS_BIT_1_ENABLE, 371 timings->bit1_match_enable ? 372 IR_DEC_STATUS_BIT_1_ENABLE : 0); 373 374 /* 375 * NEC: Unused 376 * RC6: Time for halt of logic 0/1 377 */ 378 regval = FIELD_PREP(IR_DEC_DURATN2_MAX, timings->duration2_max) | 379 FIELD_PREP(IR_DEC_DURATN2_MIN, timings->duration2_min); 380 regmap_update_bits(ir->reg, IR_DEC_DURATN2, 381 IR_DEC_DURATN2_MAX | IR_DEC_DURATN2_MIN, regval); 382 383 /* 384 * NEC: Unused 385 * RC6: Time for whole logic 0/1 386 */ 387 regval = FIELD_PREP(IR_DEC_DURATN3_MAX, timings->duration3_max) | 388 FIELD_PREP(IR_DEC_DURATN3_MIN, timings->duration3_min); 389 regmap_update_bits(ir->reg, IR_DEC_DURATN3, 390 IR_DEC_DURATN3_MAX | IR_DEC_DURATN3_MIN, regval); 391 392 /* Reset ir decoder and enable decode */ 393 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 394 IR_DEC_REG1_RESET); 395 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0); 396 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 397 IR_DEC_REG1_ENABLE); 398 399 spin_unlock_irqrestore(&ir->lock, flags); 400 401 dev_info(&dev->dev, "hw decoder init, protocol: %d\n", protocol); 402 403 return 0; 404} 405 406static void meson_ir_sw_decoder_init(struct rc_dev *dev) 407{ 408 unsigned long flags; 409 struct meson_ir *ir = dev->priv; 410 411 spin_lock_irqsave(&ir->lock, flags); 412 413 /* Reset the decoder */ 414 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 415 IR_DEC_REG1_RESET); 416 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0); 417 418 /* Set general operation mode (= raw/software decoding) */ 419 if (of_device_is_compatible(dev->dev.of_node, "amlogic,meson6-ir")) 420 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE, 421 FIELD_PREP(IR_DEC_REG1_MODE, 422 DEC_MODE_RAW)); 423 else 424 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE, 425 FIELD_PREP(IR_DEC_REG2_MODE, 426 DEC_MODE_RAW)); 427 428 /* Set rate */ 429 regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, 430 FIELD_PREP(IR_DEC_REG0_BASE_TIME, 431 MESON_RAW_TRATE - 1)); 432 /* IRQ on rising and falling edges */ 433 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_IRQSEL, 434 FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL)); 435 /* Enable the decoder */ 436 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 437 IR_DEC_REG1_ENABLE); 438 439 spin_unlock_irqrestore(&ir->lock, flags); 440 441 dev_info(&dev->dev, "sw decoder init\n"); 442} 443 444static int meson_ir_probe(struct platform_device *pdev) 445{ 446 const struct meson_ir_param *match_data; 447 struct device *dev = &pdev->dev; 448 struct device_node *node = dev->of_node; 449 void __iomem *res_start; 450 const char *map_name; 451 struct meson_ir *ir; 452 int irq, ret; 453 454 ir = devm_kzalloc(dev, sizeof(struct meson_ir), GFP_KERNEL); 455 if (!ir) 456 return -ENOMEM; 457 458 match_data = of_device_get_match_data(dev); 459 if (!match_data) 460 return dev_err_probe(dev, -ENODEV, "failed to get match data\n"); 461 462 ir->param = match_data; 463 464 res_start = devm_platform_ioremap_resource(pdev, 0); 465 if (IS_ERR(res_start)) 466 return PTR_ERR(res_start); 467 468 meson_ir_regmap_config.max_register = ir->param->max_register; 469 ir->reg = devm_regmap_init_mmio(&pdev->dev, res_start, 470 &meson_ir_regmap_config); 471 if (IS_ERR(ir->reg)) 472 return PTR_ERR(ir->reg); 473 474 irq = platform_get_irq(pdev, 0); 475 if (irq < 0) 476 return irq; 477 478 if (ir->param->support_hw_decoder) 479 ir->rc = devm_rc_allocate_device(&pdev->dev, 480 RC_DRIVER_SCANCODE); 481 else 482 ir->rc = devm_rc_allocate_device(&pdev->dev, RC_DRIVER_IR_RAW); 483 484 if (!ir->rc) { 485 dev_err(dev, "failed to allocate rc device\n"); 486 return -ENOMEM; 487 } 488 489 if (ir->rc->driver_type == RC_DRIVER_IR_RAW) { 490 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; 491 ir->rc->rx_resolution = MESON_RAW_TRATE; 492 ir->rc->min_timeout = 1; 493 ir->rc->timeout = IR_DEFAULT_TIMEOUT; 494 ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT; 495 } else if (ir->rc->driver_type == RC_DRIVER_SCANCODE) { 496 ir->rc->allowed_protocols = RC_PROTO_BIT_NEC; 497 ir->rc->change_protocol = meson_ir_hw_decoder_init; 498 } 499 500 ir->rc->priv = ir; 501 ir->rc->device_name = DRIVER_NAME; 502 ir->rc->input_phys = DRIVER_NAME "/input0"; 503 ir->rc->input_id.bustype = BUS_HOST; 504 map_name = of_get_property(node, "linux,rc-map-name", NULL); 505 ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY; 506 ir->rc->driver_name = DRIVER_NAME; 507 508 spin_lock_init(&ir->lock); 509 platform_set_drvdata(pdev, ir); 510 511 ret = devm_rc_register_device(dev, ir->rc); 512 if (ret) { 513 dev_err(dev, "failed to register rc device\n"); 514 return ret; 515 } 516 517 if (ir->rc->driver_type == RC_DRIVER_IR_RAW) 518 meson_ir_sw_decoder_init(ir->rc); 519 520 ret = devm_request_irq(dev, irq, meson_ir_irq, 0, "meson_ir", ir); 521 if (ret) { 522 dev_err(dev, "failed to request irq\n"); 523 return ret; 524 } 525 526 dev_info(dev, "receiver initialized\n"); 527 528 return 0; 529} 530 531static void meson_ir_remove(struct platform_device *pdev) 532{ 533 struct meson_ir *ir = platform_get_drvdata(pdev); 534 unsigned long flags; 535 536 /* Disable the decoder */ 537 spin_lock_irqsave(&ir->lock, flags); 538 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0); 539 spin_unlock_irqrestore(&ir->lock, flags); 540} 541 542static void meson_ir_shutdown(struct platform_device *pdev) 543{ 544 struct device *dev = &pdev->dev; 545 struct device_node *node = dev->of_node; 546 struct meson_ir *ir = platform_get_drvdata(pdev); 547 unsigned long flags; 548 549 spin_lock_irqsave(&ir->lock, flags); 550 551 /* 552 * Set operation mode to NEC/hardware decoding to give 553 * bootloader a chance to power the system back on 554 */ 555 if (of_device_is_compatible(node, "amlogic,meson6-ir")) 556 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE, 557 FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_NEC)); 558 else 559 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE, 560 FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_NEC)); 561 562 /* Set rate to default value */ 563 regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, 564 FIELD_PREP(IR_DEC_REG0_BASE_TIME, 565 MESON_HW_TRATE - 1)); 566 567 spin_unlock_irqrestore(&ir->lock, flags); 568} 569 570static const struct meson_ir_param meson6_ir_param = { 571 .support_hw_decoder = false, 572 .max_register = IR_DEC_REG1, 573}; 574 575static const struct meson_ir_param meson8b_ir_param = { 576 .support_hw_decoder = false, 577 .max_register = IR_DEC_REG2, 578}; 579 580static const struct meson_ir_param meson_s4_ir_param = { 581 .support_hw_decoder = true, 582 .max_register = IR_DEC_FRAME1, 583}; 584 585static const struct of_device_id meson_ir_match[] = { 586 { 587 .compatible = "amlogic,meson6-ir", 588 .data = &meson6_ir_param, 589 }, { 590 .compatible = "amlogic,meson8b-ir", 591 .data = &meson8b_ir_param, 592 }, { 593 .compatible = "amlogic,meson-gxbb-ir", 594 .data = &meson8b_ir_param, 595 }, { 596 .compatible = "amlogic,meson-s4-ir", 597 .data = &meson_s4_ir_param, 598 }, 599 {}, 600}; 601MODULE_DEVICE_TABLE(of, meson_ir_match); 602 603static struct platform_driver meson_ir_driver = { 604 .probe = meson_ir_probe, 605 .remove_new = meson_ir_remove, 606 .shutdown = meson_ir_shutdown, 607 .driver = { 608 .name = DRIVER_NAME, 609 .of_match_table = meson_ir_match, 610 }, 611}; 612 613module_platform_driver(meson_ir_driver); 614 615MODULE_DESCRIPTION("Amlogic Meson IR remote receiver driver"); 616MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); 617MODULE_LICENSE("GPL v2"); 618