1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2023 MediaTek Inc.
4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
5 */
6
7#ifndef __MDP_SM_MT8195_H__
8#define __MDP_SM_MT8195_H__
9
10#include "mtk-mdp3-type.h"
11
12/*
13 * ISP-MDP generic output information
14 * MD5 of the target SCP prebuild:
15 *     a49ec487e458b5971880f1b63dc2a9d5
16 */
17
18#define IMG_MAX_SUBFRAMES_8195	20
19
20struct img_comp_frame_8195 {
21	u32 output_disable;
22	u32 bypass;
23	u32 in_width;
24	u32 in_height;
25	u32 out_width;
26	u32 out_height;
27	struct img_crop crop;
28	u32 in_total_width;
29	u32 out_total_width;
30} __packed;
31
32struct img_comp_subfrm_8195 {
33	u32 tile_disable;
34	struct img_region in;
35	struct img_region out;
36	struct img_offset luma;
37	struct img_offset chroma;
38	s32 out_vertical; /* Output vertical index */
39	s32 out_horizontal; /* Output horizontal index */
40} __packed;
41
42struct mdp_rdma_subfrm_8195 {
43	u32 offset[IMG_MAX_PLANES];
44	u32 offset_0_p;
45	u32 src;
46	u32 clip;
47	u32 clip_ofst;
48	u32 in_tile_xleft;
49	u32 in_tile_ytop;
50} __packed;
51
52struct mdp_rdma_data_8195 {
53	u32 src_ctrl;
54	u32 comp_ctrl;
55	u32 control;
56	u32 iova[IMG_MAX_PLANES];
57	u32 iova_end[IMG_MAX_PLANES];
58	u32 mf_bkgd;
59	u32 mf_bkgd_in_pxl;
60	u32 sf_bkgd;
61	u32 ufo_dec_y;
62	u32 ufo_dec_c;
63	u32 transform;
64	u32 dmabuf_con0;
65	u32 ultra_th_high_con0;
66	u32 ultra_th_low_con0;
67	u32 dmabuf_con1;
68	u32 ultra_th_high_con1;
69	u32 ultra_th_low_con1;
70	u32 dmabuf_con2;
71	u32 ultra_th_high_con2;
72	u32 ultra_th_low_con2;
73	u32 dmabuf_con3;
74	struct mdp_rdma_subfrm_8195 subfrms[IMG_MAX_SUBFRAMES_8195];
75} __packed;
76
77struct mdp_fg_subfrm_8195 {
78	u32 info_0;
79	u32 info_1;
80} __packed;
81
82struct mdp_fg_data_8195 {
83	u32 ctrl_0;
84	u32 ck_en;
85	struct mdp_fg_subfrm_8195 subfrms[IMG_MAX_SUBFRAMES_8195];
86} __packed;
87
88struct mdp_hdr_subfrm_8195 {
89	u32 win_size;
90	u32 src;
91	u32 clip_ofst0;
92	u32 clip_ofst1;
93	u32 hist_ctrl_0;
94	u32 hist_ctrl_1;
95	u32 hdr_top;
96	u32 hist_addr;
97} __packed;
98
99struct mdp_hdr_data_8195 {
100	u32 top;
101	u32 relay;
102	struct mdp_hdr_subfrm_8195   subfrms[IMG_MAX_SUBFRAMES_8195];
103} __packed;
104
105struct mdp_aal_subfrm_8195 {
106	u32 src;
107	u32 clip;
108	u32 clip_ofst;
109} __packed;
110
111struct mdp_aal_data_8195 {
112	u32 cfg_main;
113	u32 cfg;
114	struct mdp_aal_subfrm_8195   subfrms[IMG_MAX_SUBFRAMES_8195];
115} __packed;
116
117struct mdp_rsz_subfrm_8195 {
118	u32 control2;
119	u32 src;
120	u32 clip;
121	u32 hdmirx_en;
122	u32 luma_h_int_ofst;
123	u32 luma_h_sub_ofst;
124	u32 luma_v_int_ofst;
125	u32 luma_v_sub_ofst;
126	u32 chroma_h_int_ofst;
127	u32 chroma_h_sub_ofst;
128	u32 rsz_switch;
129	u32 merge_cfg;
130} __packed;
131
132struct mdp_rsz_data_8195 {
133	u32 coeff_step_x;
134	u32 coeff_step_y;
135	u32 control1;
136	u32 control2;
137	u32 etc_control;
138	u32 prz_enable;
139	u32 ibse_softclip;
140	u32 tap_adapt;
141	u32 ibse_gaincontrol1;
142	u32 ibse_gaincontrol2;
143	u32 ibse_ylevel_1;
144	u32 ibse_ylevel_2;
145	u32 ibse_ylevel_3;
146	u32 ibse_ylevel_4;
147	u32 ibse_ylevel_5;
148	struct mdp_rsz_subfrm_8195 subfrms[IMG_MAX_SUBFRAMES_8195];
149} __packed;
150
151struct mdp_tdshp_subfrm_8195 {
152	u32 src;
153	u32 clip;
154	u32 clip_ofst;
155	u32 hist_cfg_0;
156	u32 hist_cfg_1;
157} __packed;
158
159struct mdp_tdshp_data_8195 {
160	u32 cfg;
161	struct mdp_tdshp_subfrm_8195 subfrms[IMG_MAX_SUBFRAMES_8195];
162} __packed;
163
164struct mdp_color_subfrm_8195 {
165	u32 in_hsize;
166	u32 in_vsize;
167} __packed;
168
169struct mdp_color_data_8195 {
170	u32 start;
171	struct mdp_color_subfrm_8195 subfrms[IMG_MAX_SUBFRAMES_8195];
172} __packed;
173
174struct mdp_ovl_subfrm_8195 {
175	u32 L0_src_size;
176	u32 roi_size;
177} __packed;
178
179struct mdp_ovl_data_8195 {
180	u32 L0_con;
181	u32 src_con;
182	struct mdp_ovl_subfrm_8195 subfrms[IMG_MAX_SUBFRAMES_8195];
183} __packed;
184
185struct mdp_pad_subfrm_8195 {
186	u32 pic_size;
187} __packed;
188
189struct mdp_pad_data_8195 {
190	struct mdp_pad_subfrm_8195 subfrms[IMG_MAX_SUBFRAMES_8195];
191} __packed;
192
193struct mdp_tcc_subfrm_8195 {
194	u32 pic_size;
195} __packed;
196
197struct mdp_tcc_data_8195 {
198	struct mdp_tcc_subfrm_8195 subfrms[IMG_MAX_SUBFRAMES_8195];
199} __packed;
200
201struct mdp_wrot_subfrm_8195 {
202	u32 offset[IMG_MAX_PLANES];
203	u32 src;
204	u32 clip;
205	u32 clip_ofst;
206	u32 main_buf;
207} __packed;
208
209struct mdp_wrot_data_8195 {
210	u32 iova[IMG_MAX_PLANES];
211	u32 control;
212	u32 stride[IMG_MAX_PLANES];
213	u32 mat_ctrl;
214	u32 fifo_test;
215	u32 filter;
216	u32 pre_ultra;
217	u32 framesize;
218	u32 afbc_yuvtrans;
219	u32 scan_10bit;
220	u32 pending_zero;
221	u32 bit_number;
222	u32 pvric;
223	u32 vpp02vpp1;
224	struct mdp_wrot_subfrm_8195 subfrms[IMG_MAX_SUBFRAMES_8195];
225} __packed;
226
227struct mdp_wdma_subfrm_8195 {
228	u32 offset[IMG_MAX_PLANES];
229	u32 src;
230	u32 clip;
231	u32 clip_ofst;
232} __packed;
233
234struct mdp_wdma_data_8195 {
235	u32 wdma_cfg;
236	u32 iova[IMG_MAX_PLANES];
237	u32 w_in_byte;
238	u32 uv_stride;
239	struct mdp_wdma_subfrm_8195 subfrms[IMG_MAX_SUBFRAMES_8195];
240} __packed;
241
242struct isp_data_8195 {
243	u64 dl_flags; /* 1 << (enum mdp_comp_type) */
244	u32 smxi_iova[4];
245	u32 cq_idx;
246	u32 cq_iova;
247	u32 tpipe_iova[IMG_MAX_SUBFRAMES_8195];
248} __packed;
249
250struct img_compparam_8195 {
251	u32 type; /* enum mdp_comp_id */
252	u32 id; /* engine alias_id */
253	u32 input;
254	u32 outputs[IMG_MAX_HW_OUTPUTS];
255	u32 num_outputs;
256	struct img_comp_frame_8195 frame;
257	struct img_comp_subfrm_8195 subfrms[IMG_MAX_SUBFRAMES_8195];
258	u32 num_subfrms;
259	union {
260		struct mdp_rdma_data_8195 rdma;
261		struct mdp_fg_data_8195 fg;
262		struct mdp_hdr_data_8195 hdr;
263		struct mdp_aal_data_8195 aal;
264		struct mdp_rsz_data_8195 rsz;
265		struct mdp_tdshp_data_8195 tdshp;
266		struct mdp_color_data_8195 color;
267		struct mdp_ovl_data_8195 ovl;
268		struct mdp_pad_data_8195 pad;
269		struct mdp_tcc_data_8195 tcc;
270		struct mdp_wrot_data_8195 wrot;
271		struct mdp_wdma_data_8195 wdma;
272		struct isp_data_8195 isp;
273	};
274} __packed;
275
276struct img_config_8195 {
277	struct img_compparam_8195 components[IMG_MAX_COMPONENTS];
278	u32 num_components;
279	struct img_mmsys_ctrl ctrls[IMG_MAX_SUBFRAMES_8195];
280	u32 num_subfrms;
281} __packed;
282
283#endif  /* __MDP_SM_MT8195_H__ */
284