1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Zoran ZR36050 basic configuration functions - header file 4 * 5 * Copyright (C) 2001 Wolfgang Scherr <scherr@net4you.at> 6 */ 7 8#ifndef ZR36050_H 9#define ZR36050_H 10 11#include "videocodec.h" 12 13/* data stored for each zoran jpeg codec chip */ 14struct zr36050 { 15 char name[32]; 16 int num; 17 /* io datastructure */ 18 struct videocodec *codec; 19 // last coder status 20 __u8 status1; 21 // actual coder setup 22 int mode; 23 24 __u16 width; 25 __u16 height; 26 27 __u16 bitrate_ctrl; 28 29 __u32 total_code_vol; 30 __u32 real_code_vol; 31 __u16 max_block_vol; 32 33 __u8 h_samp_ratio[8]; 34 __u8 v_samp_ratio[8]; 35 __u16 scalefact; 36 __u16 dri; 37 38 /* com/app marker */ 39 struct jpeg_com_marker com; 40 struct jpeg_app_marker app; 41}; 42 43/* zr36050 register addresses */ 44#define ZR050_GO 0x000 45#define ZR050_HARDWARE 0x002 46#define ZR050_MODE 0x003 47#define ZR050_OPTIONS 0x004 48#define ZR050_MBCV 0x005 49#define ZR050_MARKERS_EN 0x006 50#define ZR050_INT_REQ_0 0x007 51#define ZR050_INT_REQ_1 0x008 52#define ZR050_TCV_NET_HI 0x009 53#define ZR050_TCV_NET_MH 0x00a 54#define ZR050_TCV_NET_ML 0x00b 55#define ZR050_TCV_NET_LO 0x00c 56#define ZR050_TCV_DATA_HI 0x00d 57#define ZR050_TCV_DATA_MH 0x00e 58#define ZR050_TCV_DATA_ML 0x00f 59#define ZR050_TCV_DATA_LO 0x010 60#define ZR050_SF_HI 0x011 61#define ZR050_SF_LO 0x012 62#define ZR050_AF_HI 0x013 63#define ZR050_AF_M 0x014 64#define ZR050_AF_LO 0x015 65#define ZR050_ACV_HI 0x016 66#define ZR050_ACV_MH 0x017 67#define ZR050_ACV_ML 0x018 68#define ZR050_ACV_LO 0x019 69#define ZR050_ACT_HI 0x01a 70#define ZR050_ACT_MH 0x01b 71#define ZR050_ACT_ML 0x01c 72#define ZR050_ACT_LO 0x01d 73#define ZR050_ACV_TURN_HI 0x01e 74#define ZR050_ACV_TURN_MH 0x01f 75#define ZR050_ACV_TURN_ML 0x020 76#define ZR050_ACV_TURN_LO 0x021 77#define ZR050_STATUS_0 0x02e 78#define ZR050_STATUS_1 0x02f 79 80#define ZR050_SOF_IDX 0x040 81#define ZR050_SOS1_IDX 0x07a 82#define ZR050_SOS2_IDX 0x08a 83#define ZR050_SOS3_IDX 0x09a 84#define ZR050_SOS4_IDX 0x0aa 85#define ZR050_DRI_IDX 0x0c0 86#define ZR050_DNL_IDX 0x0c6 87#define ZR050_DQT_IDX 0x0cc 88#define ZR050_DHT_IDX 0x1d4 89#define ZR050_APP_IDX 0x380 90#define ZR050_COM_IDX 0x3c0 91 92/* zr36050 hardware register bits */ 93 94#define ZR050_HW_BSWD 0x80 95#define ZR050_HW_MSTR 0x40 96#define ZR050_HW_DMA 0x20 97#define ZR050_HW_CFIS_1_CLK 0x00 98#define ZR050_HW_CFIS_2_CLK 0x04 99#define ZR050_HW_CFIS_3_CLK 0x08 100#define ZR050_HW_CFIS_4_CLK 0x0C 101#define ZR050_HW_CFIS_5_CLK 0x10 102#define ZR050_HW_CFIS_6_CLK 0x14 103#define ZR050_HW_CFIS_7_CLK 0x18 104#define ZR050_HW_CFIS_8_CLK 0x1C 105#define ZR050_HW_BELE 0x01 106 107/* zr36050 mode register bits */ 108 109#define ZR050_MO_COMP 0x80 110#define ZR050_MO_ATP 0x40 111#define ZR050_MO_PASS2 0x20 112#define ZR050_MO_TLM 0x10 113#define ZR050_MO_DCONLY 0x08 114#define ZR050_MO_BRC 0x04 115 116#define ZR050_MO_ATP 0x40 117#define ZR050_MO_PASS2 0x20 118#define ZR050_MO_TLM 0x10 119#define ZR050_MO_DCONLY 0x08 120 121/* zr36050 option register bits */ 122 123#define ZR050_OP_NSCN_1 0x00 124#define ZR050_OP_NSCN_2 0x20 125#define ZR050_OP_NSCN_3 0x40 126#define ZR050_OP_NSCN_4 0x60 127#define ZR050_OP_NSCN_5 0x80 128#define ZR050_OP_NSCN_6 0xA0 129#define ZR050_OP_NSCN_7 0xC0 130#define ZR050_OP_NSCN_8 0xE0 131#define ZR050_OP_OVF 0x10 132 133/* zr36050 markers-enable register bits */ 134 135#define ZR050_ME_APP 0x80 136#define ZR050_ME_COM 0x40 137#define ZR050_ME_DRI 0x20 138#define ZR050_ME_DQT 0x10 139#define ZR050_ME_DHT 0x08 140#define ZR050_ME_DNL 0x04 141#define ZR050_ME_DQTI 0x02 142#define ZR050_ME_DHTI 0x01 143 144/* zr36050 status0/1 register bit masks */ 145 146#define ZR050_ST_RST_MASK 0x20 147#define ZR050_ST_SOF_MASK 0x02 148#define ZR050_ST_SOS_MASK 0x02 149#define ZR050_ST_DATRDY_MASK 0x80 150#define ZR050_ST_MRKDET_MASK 0x40 151#define ZR050_ST_RFM_MASK 0x10 152#define ZR050_ST_RFD_MASK 0x08 153#define ZR050_ST_END_MASK 0x04 154#define ZR050_ST_TCVOVF_MASK 0x02 155#define ZR050_ST_DATOVF_MASK 0x01 156 157/* pixel component idx */ 158 159#define ZR050_Y_COMPONENT 0 160#define ZR050_U_COMPONENT 1 161#define ZR050_V_COMPONENT 2 162 163int zr36050_init_module(void); 164void zr36050_cleanup_module(void); 165#endif /*fndef ZR36050_H */ 166