1/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ 2/* Copyright (C) 2019--2020 Intel Corporation */ 3/* 4 * Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs; 5 * do not modify. 6 */ 7 8#ifndef __CCS_REGS_H__ 9#define __CCS_REGS_H__ 10 11#include <linux/bits.h> 12 13#include <media/v4l2-cci.h> 14 15#define CCS_FL_BASE CCI_REG_PRIVATE_SHIFT 16#define CCS_FL_FLOAT_IREAL BIT(CCS_FL_BASE) 17#define CCS_FL_IREAL BIT(CCS_FL_BASE + 1) 18#define CCS_BUILD_BUG \ 19 BUILD_BUG_ON(~CCI_REG_PRIVATE_MASK & (BIT(CCS_FL_BASE) | BIT(CCS_FL_BASE + 1))) 20#define CCS_R_MODULE_MODEL_ID CCI_REG16(0x0000) 21#define CCS_R_MODULE_REVISION_NUMBER_MAJOR CCI_REG8(0x0002) 22#define CCS_R_FRAME_COUNT CCI_REG8(0x0005) 23#define CCS_R_PIXEL_ORDER CCI_REG8(0x0006) 24#define CCS_PIXEL_ORDER_GRBG 0U 25#define CCS_PIXEL_ORDER_RGGB 1U 26#define CCS_PIXEL_ORDER_BGGR 2U 27#define CCS_PIXEL_ORDER_GBRG 3U 28#define CCS_R_MIPI_CCS_VERSION CCI_REG8(0x0007) 29#define CCS_MIPI_CCS_VERSION_V1_0 0x10 30#define CCS_MIPI_CCS_VERSION_V1_1 0x11 31#define CCS_MIPI_CCS_VERSION_MAJOR_SHIFT 4U 32#define CCS_MIPI_CCS_VERSION_MAJOR_MASK 0xf0 33#define CCS_MIPI_CCS_VERSION_MINOR_SHIFT 0U 34#define CCS_MIPI_CCS_VERSION_MINOR_MASK 0xf 35#define CCS_R_DATA_PEDESTAL CCI_REG16(0x0008) 36#define CCS_R_MODULE_MANUFACTURER_ID CCI_REG16(0x000e) 37#define CCS_R_MODULE_REVISION_NUMBER_MINOR CCI_REG8(0x0010) 38#define CCS_R_MODULE_DATE_YEAR CCI_REG8(0x0012) 39#define CCS_R_MODULE_DATE_MONTH CCI_REG8(0x0013) 40#define CCS_R_MODULE_DATE_DAY CCI_REG8(0x0014) 41#define CCS_R_MODULE_DATE_PHASE CCI_REG8(0x0015) 42#define CCS_MODULE_DATE_PHASE_SHIFT 0U 43#define CCS_MODULE_DATE_PHASE_MASK 0x7 44#define CCS_MODULE_DATE_PHASE_TS 0U 45#define CCS_MODULE_DATE_PHASE_ES 1U 46#define CCS_MODULE_DATE_PHASE_CS 2U 47#define CCS_MODULE_DATE_PHASE_MP 3U 48#define CCS_R_SENSOR_MODEL_ID CCI_REG16(0x0016) 49#define CCS_R_SENSOR_REVISION_NUMBER CCI_REG8(0x0018) 50#define CCS_R_SENSOR_FIRMWARE_VERSION CCI_REG8(0x001a) 51#define CCS_R_SERIAL_NUMBER CCI_REG32(0x001c) 52#define CCS_R_SENSOR_MANUFACTURER_ID CCI_REG16(0x0020) 53#define CCS_R_SENSOR_REVISION_NUMBER_16 CCI_REG16(0x0022) 54#define CCS_R_FRAME_FORMAT_MODEL_TYPE CCI_REG8(0x0040) 55#define CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE 1U 56#define CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE 2U 57#define CCS_R_FRAME_FORMAT_MODEL_SUBTYPE CCI_REG8(0x0041) 58#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U 59#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf 60#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U 61#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0 62#define CCS_R_FRAME_FORMAT_DESCRIPTOR(n) CCI_REG16(0x0042 + (n) * 2) 63#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MIN_N 0U 64#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MAX_N 14U 65#define CCS_R_FRAME_FORMAT_DESCRIPTOR_4(n) CCI_REG32(0x0060 + (n) * 4) 66#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_SHIFT 0U 67#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK 0xfff 68#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT 12U 69#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK 0xf000 70#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED 1U 71#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL 2U 72#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL 3U 73#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL 4U 74#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL 5U 75#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_0 8U 76#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_1 9U 77#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_2 10U 78#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_3 11U 79#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_4 12U 80#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_5 13U 81#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_6 14U 82#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MIN_N 0U 83#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MAX_N 7U 84#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_SHIFT 0U 85#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK 0xffff 86#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT 28U 87#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK 0xf0000000 88#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_EMBEDDED 1U 89#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DUMMY_PIXEL 2U 90#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_BLACK_PIXEL 3U 91#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DARK_PIXEL 4U 92#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_VISIBLE_PIXEL 5U 93#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_0 8U 94#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_1 9U 95#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_2 10U 96#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_3 11U 97#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_4 12U 98#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_5 13U 99#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_6 14U 100#define CCS_R_ANALOG_GAIN_CAPABILITY CCI_REG16(0x0080) 101#define CCS_ANALOG_GAIN_CAPABILITY_GLOBAL 0U 102#define CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL 2U 103#define CCS_R_ANALOG_GAIN_CODE_MIN CCI_REG16(0x0084) 104#define CCS_R_ANALOG_GAIN_CODE_MAX CCI_REG16(0x0086) 105#define CCS_R_ANALOG_GAIN_CODE_STEP CCI_REG16(0x0088) 106#define CCS_R_ANALOG_GAIN_TYPE CCI_REG16(0x008a) 107#define CCS_R_ANALOG_GAIN_M0 CCI_REG16(0x008c) 108#define CCS_R_ANALOG_GAIN_C0 CCI_REG16(0x008e) 109#define CCS_R_ANALOG_GAIN_M1 CCI_REG16(0x0090) 110#define CCS_R_ANALOG_GAIN_C1 CCI_REG16(0x0092) 111#define CCS_R_ANALOG_LINEAR_GAIN_MIN CCI_REG16(0x0094) 112#define CCS_R_ANALOG_LINEAR_GAIN_MAX CCI_REG16(0x0096) 113#define CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE CCI_REG16(0x0098) 114#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN CCI_REG16(0x009a) 115#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX CCI_REG16(0x009c) 116#define CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE CCI_REG16(0x009e) 117#define CCS_R_DATA_FORMAT_MODEL_TYPE CCI_REG8(0x00c0) 118#define CCS_DATA_FORMAT_MODEL_TYPE_NORMAL 1U 119#define CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED 2U 120#define CCS_R_DATA_FORMAT_MODEL_SUBTYPE CCI_REG8(0x00c1) 121#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U 122#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf 123#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U 124#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0 125#define CCS_R_DATA_FORMAT_DESCRIPTOR(n) CCI_REG16(0x00c2 + (n) * 2) 126#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MIN_N 0U 127#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N 15U 128#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_SHIFT 0U 129#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK 0xff 130#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT 8U 131#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_MASK 0xff00 132#define CCS_R_MODE_SELECT CCI_REG8(0x0100) 133#define CCS_MODE_SELECT_SOFTWARE_STANDBY 0U 134#define CCS_MODE_SELECT_STREAMING 1U 135#define CCS_R_IMAGE_ORIENTATION CCI_REG8(0x0101) 136#define CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR BIT(0) 137#define CCS_IMAGE_ORIENTATION_VERTICAL_FLIP BIT(1) 138#define CCS_R_SOFTWARE_RESET CCI_REG8(0x0103) 139#define CCS_SOFTWARE_RESET_OFF 0U 140#define CCS_SOFTWARE_RESET_ON 1U 141#define CCS_R_GROUPED_PARAMETER_HOLD CCI_REG8(0x0104) 142#define CCS_R_MASK_CORRUPTED_FRAMES CCI_REG8(0x0105) 143#define CCS_MASK_CORRUPTED_FRAMES_ALLOW 0U 144#define CCS_MASK_CORRUPTED_FRAMES_MASK 1U 145#define CCS_R_FAST_STANDBY_CTRL CCI_REG8(0x0106) 146#define CCS_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0U 147#define CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION 1U 148#define CCS_R_CCI_ADDRESS_CTRL CCI_REG8(0x0107) 149#define CCS_R_2ND_CCI_IF_CTRL CCI_REG8(0x0108) 150#define CCS_2ND_CCI_IF_CTRL_ENABLE BIT(0) 151#define CCS_2ND_CCI_IF_CTRL_ACK BIT(1) 152#define CCS_R_2ND_CCI_ADDRESS_CTRL CCI_REG8(0x0109) 153#define CCS_R_CSI_CHANNEL_IDENTIFIER CCI_REG8(0x0110) 154#define CCS_R_CSI_SIGNALING_MODE CCI_REG8(0x0111) 155#define CCS_CSI_SIGNALING_MODE_CSI_2_DPHY 2U 156#define CCS_CSI_SIGNALING_MODE_CSI_2_CPHY 3U 157#define CCS_R_CSI_DATA_FORMAT CCI_REG16(0x0112) 158#define CCS_R_CSI_LANE_MODE CCI_REG8(0x0114) 159#define CCS_R_DPCM_FRAME_DT CCI_REG8(0x011d) 160#define CCS_R_BOTTOM_EMBEDDED_DATA_DT CCI_REG8(0x011e) 161#define CCS_R_BOTTOM_EMBEDDED_DATA_VC CCI_REG8(0x011f) 162#define CCS_R_GAIN_MODE CCI_REG8(0x0120) 163#define CCS_GAIN_MODE_GLOBAL 0U 164#define CCS_GAIN_MODE_ALTERNATE 1U 165#define CCS_R_ADC_BIT_DEPTH CCI_REG8(0x0121) 166#define CCS_R_EMB_DATA_CTRL CCI_REG8(0x0122) 167#define CCS_EMB_DATA_CTRL_RAW8_PACKING_FOR_RAW16 BIT(0) 168#define CCS_EMB_DATA_CTRL_RAW10_PACKING_FOR_RAW20 BIT(1) 169#define CCS_EMB_DATA_CTRL_RAW12_PACKING_FOR_RAW24 BIT(2) 170#define CCS_R_GPIO_TRIG_MODE CCI_REG8(0x0130) 171#define CCS_R_EXTCLK_FREQUENCY_MHZ (CCI_REG16(0x0136) | CCS_FL_IREAL) 172#define CCS_R_TEMP_SENSOR_CTRL CCI_REG8(0x0138) 173#define CCS_TEMP_SENSOR_CTRL_ENABLE BIT(0) 174#define CCS_R_TEMP_SENSOR_MODE CCI_REG8(0x0139) 175#define CCS_R_TEMP_SENSOR_OUTPUT CCI_REG8(0x013a) 176#define CCS_R_FINE_INTEGRATION_TIME CCI_REG16(0x0200) 177#define CCS_R_COARSE_INTEGRATION_TIME CCI_REG16(0x0202) 178#define CCS_R_ANALOG_GAIN_CODE_GLOBAL CCI_REG16(0x0204) 179#define CCS_R_ANALOG_LINEAR_GAIN_GLOBAL CCI_REG16(0x0206) 180#define CCS_R_ANALOG_EXPONENTIAL_GAIN_GLOBAL CCI_REG16(0x0208) 181#define CCS_R_DIGITAL_GAIN_GLOBAL CCI_REG16(0x020e) 182#define CCS_R_SHORT_ANALOG_GAIN_GLOBAL CCI_REG16(0x0216) 183#define CCS_R_SHORT_DIGITAL_GAIN_GLOBAL CCI_REG16(0x0218) 184#define CCS_R_HDR_MODE CCI_REG8(0x0220) 185#define CCS_HDR_MODE_ENABLED BIT(0) 186#define CCS_HDR_MODE_SEPARATE_ANALOG_GAIN BIT(1) 187#define CCS_HDR_MODE_UPSCALING BIT(2) 188#define CCS_HDR_MODE_RESET_SYNC BIT(3) 189#define CCS_HDR_MODE_TIMING_MODE BIT(4) 190#define CCS_HDR_MODE_EXPOSURE_CTRL_DIRECT BIT(5) 191#define CCS_HDR_MODE_SEPARATE_DIGITAL_GAIN BIT(6) 192#define CCS_R_HDR_RESOLUTION_REDUCTION CCI_REG8(0x0221) 193#define CCS_HDR_RESOLUTION_REDUCTION_ROW_SHIFT 0U 194#define CCS_HDR_RESOLUTION_REDUCTION_ROW_MASK 0xf 195#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_SHIFT 4U 196#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_MASK 0xf0 197#define CCS_R_EXPOSURE_RATIO CCI_REG8(0x0222) 198#define CCS_R_HDR_INTERNAL_BIT_DEPTH CCI_REG8(0x0223) 199#define CCS_R_DIRECT_SHORT_INTEGRATION_TIME CCI_REG16(0x0224) 200#define CCS_R_SHORT_ANALOG_LINEAR_GAIN_GLOBAL CCI_REG16(0x0226) 201#define CCS_R_SHORT_ANALOG_EXPONENTIAL_GAIN_GLOBAL CCI_REG16(0x0228) 202#define CCS_R_VT_PIX_CLK_DIV CCI_REG16(0x0300) 203#define CCS_R_VT_SYS_CLK_DIV CCI_REG16(0x0302) 204#define CCS_R_PRE_PLL_CLK_DIV CCI_REG16(0x0304) 205#define CCS_R_PLL_MULTIPLIER CCI_REG16(0x0306) 206#define CCS_R_OP_PIX_CLK_DIV CCI_REG16(0x0308) 207#define CCS_R_OP_SYS_CLK_DIV CCI_REG16(0x030a) 208#define CCS_R_OP_PRE_PLL_CLK_DIV CCI_REG16(0x030c) 209#define CCS_R_OP_PLL_MULTIPLIER CCI_REG16(0x030e) 210#define CCS_R_PLL_MODE CCI_REG8(0x0310) 211#define CCS_PLL_MODE_SHIFT 0U 212#define CCS_PLL_MODE_MASK 0x1 213#define CCS_PLL_MODE_SINGLE 0U 214#define CCS_PLL_MODE_DUAL 1U 215#define CCS_R_OP_PIX_CLK_DIV_REV CCI_REG16(0x0312) 216#define CCS_R_OP_SYS_CLK_DIV_REV CCI_REG16(0x0314) 217#define CCS_R_FRAME_LENGTH_LINES CCI_REG16(0x0340) 218#define CCS_R_LINE_LENGTH_PCK CCI_REG16(0x0342) 219#define CCS_R_X_ADDR_START CCI_REG16(0x0344) 220#define CCS_R_Y_ADDR_START CCI_REG16(0x0346) 221#define CCS_R_X_ADDR_END CCI_REG16(0x0348) 222#define CCS_R_Y_ADDR_END CCI_REG16(0x034a) 223#define CCS_R_X_OUTPUT_SIZE CCI_REG16(0x034c) 224#define CCS_R_Y_OUTPUT_SIZE CCI_REG16(0x034e) 225#define CCS_R_FRAME_LENGTH_CTRL CCI_REG8(0x0350) 226#define CCS_FRAME_LENGTH_CTRL_AUTOMATIC BIT(0) 227#define CCS_R_TIMING_MODE_CTRL CCI_REG8(0x0352) 228#define CCS_TIMING_MODE_CTRL_MANUAL_READOUT BIT(0) 229#define CCS_TIMING_MODE_CTRL_DELAYED_EXPOSURE BIT(1) 230#define CCS_R_START_READOUT_RS CCI_REG8(0x0353) 231#define CCS_START_READOUT_RS_MANUAL_READOUT_START BIT(0) 232#define CCS_R_FRAME_MARGIN CCI_REG16(0x0354) 233#define CCS_R_X_EVEN_INC CCI_REG16(0x0380) 234#define CCS_R_X_ODD_INC CCI_REG16(0x0382) 235#define CCS_R_Y_EVEN_INC CCI_REG16(0x0384) 236#define CCS_R_Y_ODD_INC CCI_REG16(0x0386) 237#define CCS_R_MONOCHROME_EN CCI_REG8(0x0390) 238#define CCS_MONOCHROME_EN_ENABLED 0U 239#define CCS_R_SCALING_MODE CCI_REG16(0x0400) 240#define CCS_SCALING_MODE_NO_SCALING 0U 241#define CCS_SCALING_MODE_HORIZONTAL 1U 242#define CCS_R_SCALE_M CCI_REG16(0x0404) 243#define CCS_R_SCALE_N CCI_REG16(0x0406) 244#define CCS_R_DIGITAL_CROP_X_OFFSET CCI_REG16(0x0408) 245#define CCS_R_DIGITAL_CROP_Y_OFFSET CCI_REG16(0x040a) 246#define CCS_R_DIGITAL_CROP_IMAGE_WIDTH CCI_REG16(0x040c) 247#define CCS_R_DIGITAL_CROP_IMAGE_HEIGHT CCI_REG16(0x040e) 248#define CCS_R_COMPRESSION_MODE CCI_REG16(0x0500) 249#define CCS_COMPRESSION_MODE_NONE 0U 250#define CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE 1U 251#define CCS_R_TEST_PATTERN_MODE CCI_REG16(0x0600) 252#define CCS_TEST_PATTERN_MODE_NONE 0U 253#define CCS_TEST_PATTERN_MODE_SOLID_COLOR 1U 254#define CCS_TEST_PATTERN_MODE_COLOR_BARS 2U 255#define CCS_TEST_PATTERN_MODE_FADE_TO_GREY 3U 256#define CCS_TEST_PATTERN_MODE_PN9 4U 257#define CCS_TEST_PATTERN_MODE_COLOR_TILE 5U 258#define CCS_R_TEST_DATA_RED CCI_REG16(0x0602) 259#define CCS_R_TEST_DATA_GREENR CCI_REG16(0x0604) 260#define CCS_R_TEST_DATA_BLUE CCI_REG16(0x0606) 261#define CCS_R_TEST_DATA_GREENB CCI_REG16(0x0608) 262#define CCS_R_VALUE_STEP_SIZE_SMOOTH CCI_REG8(0x060a) 263#define CCS_R_VALUE_STEP_SIZE_QUANTISED CCI_REG8(0x060b) 264#define CCS_R_TCLK_POST CCI_REG8(0x0800) 265#define CCS_R_THS_PREPARE CCI_REG8(0x0801) 266#define CCS_R_THS_ZERO_MIN CCI_REG8(0x0802) 267#define CCS_R_THS_TRAIL CCI_REG8(0x0803) 268#define CCS_R_TCLK_TRAIL_MIN CCI_REG8(0x0804) 269#define CCS_R_TCLK_PREPARE CCI_REG8(0x0805) 270#define CCS_R_TCLK_ZERO CCI_REG8(0x0806) 271#define CCS_R_TLPX CCI_REG8(0x0807) 272#define CCS_R_PHY_CTRL CCI_REG8(0x0808) 273#define CCS_PHY_CTRL_AUTO 0U 274#define CCS_PHY_CTRL_UI 1U 275#define CCS_PHY_CTRL_MANUAL 2U 276#define CCS_R_TCLK_POST_EX CCI_REG16(0x080a) 277#define CCS_R_THS_PREPARE_EX CCI_REG16(0x080c) 278#define CCS_R_THS_ZERO_MIN_EX CCI_REG16(0x080e) 279#define CCS_R_THS_TRAIL_EX CCI_REG16(0x0810) 280#define CCS_R_TCLK_TRAIL_MIN_EX CCI_REG16(0x0812) 281#define CCS_R_TCLK_PREPARE_EX CCI_REG16(0x0814) 282#define CCS_R_TCLK_ZERO_EX CCI_REG16(0x0816) 283#define CCS_R_TLPX_EX CCI_REG16(0x0818) 284#define CCS_R_REQUESTED_LINK_RATE CCI_REG32(0x0820) 285#define CCS_R_DPHY_EQUALIZATION_MODE CCI_REG8(0x0824) 286#define CCS_DPHY_EQUALIZATION_MODE_EQ2 BIT(0) 287#define CCS_R_PHY_EQUALIZATION_CTRL CCI_REG8(0x0825) 288#define CCS_PHY_EQUALIZATION_CTRL_ENABLE BIT(0) 289#define CCS_R_DPHY_PREAMBLE_CTRL CCI_REG8(0x0826) 290#define CCS_DPHY_PREAMBLE_CTRL_ENABLE BIT(0) 291#define CCS_R_DPHY_PREAMBLE_LENGTH CCI_REG8(0x0826) 292#define CCS_R_PHY_SSC_CTRL CCI_REG8(0x0828) 293#define CCS_PHY_SSC_CTRL_ENABLE BIT(0) 294#define CCS_R_MANUAL_LP_CTRL CCI_REG8(0x0829) 295#define CCS_MANUAL_LP_CTRL_ENABLE BIT(0) 296#define CCS_R_TWAKEUP CCI_REG8(0x082a) 297#define CCS_R_TINIT CCI_REG8(0x082b) 298#define CCS_R_THS_EXIT CCI_REG8(0x082c) 299#define CCS_R_THS_EXIT_EX CCI_REG16(0x082e) 300#define CCS_R_PHY_PERIODIC_CALIBRATION_CTRL CCI_REG8(0x0830) 301#define CCS_PHY_PERIODIC_CALIBRATION_CTRL_FRAME_BLANKING BIT(0) 302#define CCS_R_PHY_PERIODIC_CALIBRATION_INTERVAL CCI_REG8(0x0831) 303#define CCS_R_PHY_INIT_CALIBRATION_CTRL CCI_REG8(0x0832) 304#define CCS_PHY_INIT_CALIBRATION_CTRL_STREAM_START BIT(0) 305#define CCS_R_DPHY_CALIBRATION_MODE CCI_REG8(0x0833) 306#define CCS_DPHY_CALIBRATION_MODE_ALSO_ALTERNATE BIT(0) 307#define CCS_R_CPHY_CALIBRATION_MODE CCI_REG8(0x0834) 308#define CCS_CPHY_CALIBRATION_MODE_FORMAT_1 0U 309#define CCS_CPHY_CALIBRATION_MODE_FORMAT_2 1U 310#define CCS_CPHY_CALIBRATION_MODE_FORMAT_3 2U 311#define CCS_R_T3_CALPREAMBLE_LENGTH CCI_REG8(0x0835) 312#define CCS_R_T3_CALPREAMBLE_LENGTH_PER CCI_REG8(0x0836) 313#define CCS_R_T3_CALALTSEQ_LENGTH CCI_REG8(0x0837) 314#define CCS_R_T3_CALALTSEQ_LENGTH_PER CCI_REG8(0x0838) 315#define CCS_R_FM2_INIT_SEED CCI_REG16(0x083a) 316#define CCS_R_T3_CALUDEFSEQ_LENGTH CCI_REG16(0x083c) 317#define CCS_R_T3_CALUDEFSEQ_LENGTH_PER CCI_REG16(0x083e) 318#define CCS_R_TGR_PREAMBLE_LENGTH CCI_REG8(0x0841) 319#define CCS_TGR_PREAMBLE_LENGTH_PREAMABLE_PROG_SEQ BIT(7) 320#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_SHIFT 0U 321#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_MASK 0x3f 322#define CCS_R_TGR_POST_LENGTH CCI_REG8(0x0842) 323#define CCS_TGR_POST_LENGTH_POST_LENGTH_SHIFT 0U 324#define CCS_TGR_POST_LENGTH_POST_LENGTH_MASK 0x1f 325#define CCS_R_TGR_PREAMBLE_PROG_SEQUENCE(n2) CCI_REG8(0x0843 + (n2)) 326#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MIN_N2 0U 327#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MAX_N2 6U 328#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_SHIFT 3U 329#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_MASK 0x38 330#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_SHIFT 0U 331#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_MASK 0x7 332#define CCS_R_T3_PREPARE CCI_REG16(0x084e) 333#define CCS_R_T3_LPX CCI_REG16(0x0850) 334#define CCS_R_ALPS_CTRL CCI_REG8(0x085a) 335#define CCS_ALPS_CTRL_LVLP_DPHY BIT(0) 336#define CCS_ALPS_CTRL_LVLP_CPHY BIT(1) 337#define CCS_ALPS_CTRL_ALP_CPHY BIT(2) 338#define CCS_R_TX_REG_CSI_EPD_EN_SSP_CPHY CCI_REG16(0x0860) 339#define CCS_R_TX_REG_CSI_EPD_OP_SLP_CPHY CCI_REG16(0x0862) 340#define CCS_R_TX_REG_CSI_EPD_EN_SSP_DPHY CCI_REG16(0x0864) 341#define CCS_R_TX_REG_CSI_EPD_OP_SLP_DPHY CCI_REG16(0x0866) 342#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_CPHY CCI_REG8(0x0868) 343#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_DPHY CCI_REG8(0x0869) 344#define CCS_R_SCRAMBLING_CTRL CCI_REG8(0x0870) 345#define CCS_SCRAMBLING_CTRL_ENABLED BIT(0) 346#define CCS_SCRAMBLING_CTRL_SHIFT 2U 347#define CCS_SCRAMBLING_CTRL_MASK 0xc 348#define CCS_SCRAMBLING_CTRL_1_SEED_CPHY 0U 349#define CCS_SCRAMBLING_CTRL_4_SEED_CPHY 3U 350#define CCS_R_LANE_SEED_VALUE(seed, lane) CCI_REG16(0x0872 + (seed) * 16 + (lane) * 2) 351#define CCS_LIM_LANE_SEED_VALUE_MIN_SEED 0U 352#define CCS_LIM_LANE_SEED_VALUE_MAX_SEED 3U 353#define CCS_LIM_LANE_SEED_VALUE_MIN_LANE 0U 354#define CCS_LIM_LANE_SEED_VALUE_MAX_LANE 7U 355#define CCS_R_TX_USL_REV_ENTRY CCI_REG16(0x08c0) 356#define CCS_R_TX_USL_REV_CLOCK_COUNTER CCI_REG16(0x08c2) 357#define CCS_R_TX_USL_REV_LP_COUNTER CCI_REG16(0x08c4) 358#define CCS_R_TX_USL_REV_FRAME_COUNTER CCI_REG16(0x08c6) 359#define CCS_R_TX_USL_REV_CHRONOLOGICAL_TIMER CCI_REG16(0x08c8) 360#define CCS_R_TX_USL_FWD_ENTRY CCI_REG16(0x08ca) 361#define CCS_R_TX_USL_GPIO CCI_REG16(0x08cc) 362#define CCS_R_TX_USL_OPERATION CCI_REG16(0x08ce) 363#define CCS_TX_USL_OPERATION_RESET BIT(0) 364#define CCS_R_TX_USL_ALP_CTRL CCI_REG16(0x08d0) 365#define CCS_TX_USL_ALP_CTRL_CLOCK_PAUSE BIT(0) 366#define CCS_R_TX_USL_APP_BTA_ACK_TIMEOUT CCI_REG16(0x08d2) 367#define CCS_R_TX_USL_SNS_BTA_ACK_TIMEOUT CCI_REG16(0x08d2) 368#define CCS_R_USL_CLOCK_MODE_D_CTRL CCI_REG8(0x08d2) 369#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_STANDBY BIT(0) 370#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_VBLANK BIT(1) 371#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_HBLANK BIT(2) 372#define CCS_R_BINNING_MODE CCI_REG8(0x0900) 373#define CCS_R_BINNING_TYPE CCI_REG8(0x0901) 374#define CCS_R_BINNING_WEIGHTING CCI_REG8(0x0902) 375#define CCS_R_DATA_TRANSFER_IF_1_CTRL CCI_REG8(0x0a00) 376#define CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE BIT(0) 377#define CCS_DATA_TRANSFER_IF_1_CTRL_WRITE BIT(1) 378#define CCS_DATA_TRANSFER_IF_1_CTRL_CLEAR_ERROR BIT(2) 379#define CCS_R_DATA_TRANSFER_IF_1_STATUS CCI_REG8(0x0a01) 380#define CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY BIT(0) 381#define CCS_DATA_TRANSFER_IF_1_STATUS_WRITE_IF_READY BIT(1) 382#define CCS_DATA_TRANSFER_IF_1_STATUS_DATA_CORRUPTED BIT(2) 383#define CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE BIT(3) 384#define CCS_R_DATA_TRANSFER_IF_1_PAGE_SELECT CCI_REG8(0x0a02) 385#define CCS_R_DATA_TRANSFER_IF_1_DATA(p) CCI_REG8(0x0a04 + (p)) 386#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MIN_P 0U 387#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P 63U 388#define CCS_R_SHADING_CORRECTION_EN CCI_REG8(0x0b00) 389#define CCS_SHADING_CORRECTION_EN_ENABLE BIT(0) 390#define CCS_R_LUMINANCE_CORRECTION_LEVEL CCI_REG8(0x0b01) 391#define CCS_R_GREEN_IMBALANCE_FILTER_EN CCI_REG8(0x0b02) 392#define CCS_GREEN_IMBALANCE_FILTER_EN_ENABLE BIT(0) 393#define CCS_R_MAPPED_DEFECT_CORRECT_EN CCI_REG8(0x0b05) 394#define CCS_MAPPED_DEFECT_CORRECT_EN_ENABLE BIT(0) 395#define CCS_R_SINGLE_DEFECT_CORRECT_EN CCI_REG8(0x0b06) 396#define CCS_SINGLE_DEFECT_CORRECT_EN_ENABLE BIT(0) 397#define CCS_R_DYNAMIC_COUPLET_CORRECT_EN CCI_REG8(0x0b08) 398#define CCS_DYNAMIC_COUPLET_CORRECT_EN_ENABLE BIT(0) 399#define CCS_R_COMBINED_DEFECT_CORRECT_EN CCI_REG8(0x0b0a) 400#define CCS_COMBINED_DEFECT_CORRECT_EN_ENABLE BIT(0) 401#define CCS_R_MODULE_SPECIFIC_CORRECTION_EN CCI_REG8(0x0b0c) 402#define CCS_MODULE_SPECIFIC_CORRECTION_EN_ENABLE BIT(0) 403#define CCS_R_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN CCI_REG8(0x0b13) 404#define CCS_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN_ENABLE BIT(0) 405#define CCS_R_NF_CTRL CCI_REG8(0x0b15) 406#define CCS_NF_CTRL_LUMA BIT(0) 407#define CCS_NF_CTRL_CHROMA BIT(1) 408#define CCS_NF_CTRL_COMBINED BIT(2) 409#define CCS_R_OB_READOUT_CONTROL CCI_REG8(0x0b30) 410#define CCS_OB_READOUT_CONTROL_ENABLE BIT(0) 411#define CCS_OB_READOUT_CONTROL_INTERLEAVING BIT(1) 412#define CCS_R_OB_VIRTUAL_CHANNEL CCI_REG8(0x0b31) 413#define CCS_R_OB_DT CCI_REG8(0x0b32) 414#define CCS_R_OB_DATA_FORMAT CCI_REG8(0x0b33) 415#define CCS_R_COLOR_TEMPERATURE CCI_REG16(0x0b8c) 416#define CCS_R_ABSOLUTE_GAIN_GREENR CCI_REG16(0x0b8e) 417#define CCS_R_ABSOLUTE_GAIN_RED CCI_REG16(0x0b90) 418#define CCS_R_ABSOLUTE_GAIN_BLUE CCI_REG16(0x0b92) 419#define CCS_R_ABSOLUTE_GAIN_GREENB CCI_REG16(0x0b94) 420#define CCS_R_CFA_CONVERSION_CTRL CCI_REG8(0x0ba0) 421#define CCS_CFA_CONVERSION_CTRL_BAYER_CONVERSION_ENABLE BIT(0) 422#define CCS_R_FLASH_STROBE_ADJUSTMENT CCI_REG8(0x0c12) 423#define CCS_R_FLASH_STROBE_START_POINT CCI_REG16(0x0c14) 424#define CCS_R_TFLASH_STROBE_DELAY_RS_CTRL CCI_REG16(0x0c16) 425#define CCS_R_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL CCI_REG16(0x0c18) 426#define CCS_R_FLASH_MODE_RS CCI_REG8(0x0c1a) 427#define CCS_FLASH_MODE_RS_CONTINUOUS BIT(0) 428#define CCS_FLASH_MODE_RS_TRUNCATE BIT(1) 429#define CCS_FLASH_MODE_RS_ASYNC BIT(3) 430#define CCS_R_FLASH_TRIGGER_RS CCI_REG8(0x0c1b) 431#define CCS_R_FLASH_STATUS CCI_REG8(0x0c1c) 432#define CCS_FLASH_STATUS_RETIMED BIT(0) 433#define CCS_R_SA_STROBE_MODE CCI_REG8(0x0c1d) 434#define CCS_SA_STROBE_MODE_CONTINUOUS BIT(0) 435#define CCS_SA_STROBE_MODE_TRUNCATE BIT(1) 436#define CCS_SA_STROBE_MODE_ASYNC BIT(3) 437#define CCS_SA_STROBE_MODE_ADJUST_EDGE BIT(4) 438#define CCS_R_SA_STROBE_START_POINT CCI_REG16(0x0c1e) 439#define CCS_R_TSA_STROBE_DELAY_CTRL CCI_REG16(0x0c20) 440#define CCS_R_TSA_STROBE_WIDTH_CTRL CCI_REG16(0x0c22) 441#define CCS_R_SA_STROBE_TRIGGER CCI_REG8(0x0c24) 442#define CCS_R_SA_STROBE_STATUS CCI_REG8(0x0c25) 443#define CCS_SA_STROBE_STATUS_RETIMED BIT(0) 444#define CCS_R_TSA_STROBE_RE_DELAY_CTRL CCI_REG16(0x0c30) 445#define CCS_R_TSA_STROBE_FE_DELAY_CTRL CCI_REG16(0x0c32) 446#define CCS_R_PDAF_CTRL CCI_REG16(0x0d00) 447#define CCS_PDAF_CTRL_ENABLE BIT(0) 448#define CCS_PDAF_CTRL_PROCESSED BIT(1) 449#define CCS_PDAF_CTRL_INTERLEAVED BIT(2) 450#define CCS_PDAF_CTRL_VISIBLE_PDAF_CORRECTION BIT(3) 451#define CCS_R_PDAF_VC CCI_REG8(0x0d02) 452#define CCS_R_PDAF_DT CCI_REG8(0x0d03) 453#define CCS_R_PD_X_ADDR_START CCI_REG16(0x0d04) 454#define CCS_R_PD_Y_ADDR_START CCI_REG16(0x0d06) 455#define CCS_R_PD_X_ADDR_END CCI_REG16(0x0d08) 456#define CCS_R_PD_Y_ADDR_END CCI_REG16(0x0d0a) 457#define CCS_R_BRACKETING_LUT_CTRL CCI_REG8(0x0e00) 458#define CCS_R_BRACKETING_LUT_MODE CCI_REG8(0x0e01) 459#define CCS_BRACKETING_LUT_MODE_CONTINUE_STREAMING BIT(0) 460#define CCS_BRACKETING_LUT_MODE_LOOP_MODE BIT(1) 461#define CCS_R_BRACKETING_LUT_ENTRY_CTRL CCI_REG8(0x0e02) 462#define CCS_R_BRACKETING_LUT_FRAME(n) CCI_REG8(0x0e10 + (n)) 463#define CCS_LIM_BRACKETING_LUT_FRAME_MIN_N 0U 464#define CCS_LIM_BRACKETING_LUT_FRAME_MAX_N 239U 465#define CCS_R_INTEGRATION_TIME_CAPABILITY CCI_REG16(0x1000) 466#define CCS_INTEGRATION_TIME_CAPABILITY_FINE BIT(0) 467#define CCS_R_COARSE_INTEGRATION_TIME_MIN CCI_REG16(0x1004) 468#define CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN CCI_REG16(0x1006) 469#define CCS_R_FINE_INTEGRATION_TIME_MIN CCI_REG16(0x1008) 470#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN CCI_REG16(0x100a) 471#define CCS_R_DIGITAL_GAIN_CAPABILITY CCI_REG8(0x1081) 472#define CCS_DIGITAL_GAIN_CAPABILITY_NONE 0U 473#define CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL 2U 474#define CCS_R_DIGITAL_GAIN_MIN CCI_REG16(0x1084) 475#define CCS_R_DIGITAL_GAIN_MAX CCI_REG16(0x1086) 476#define CCS_R_DIGITAL_GAIN_STEP_SIZE CCI_REG16(0x1088) 477#define CCS_R_PEDESTAL_CAPABILITY CCI_REG8(0x10e0) 478#define CCS_R_ADC_CAPABILITY CCI_REG8(0x10f0) 479#define CCS_ADC_CAPABILITY_BIT_DEPTH_CTRL BIT(0) 480#define CCS_R_ADC_BIT_DEPTH_CAPABILITY CCI_REG32(0x10f4) 481#define CCS_R_MIN_EXT_CLK_FREQ_MHZ (CCI_REG32(0x1100) | CCS_FL_FLOAT_IREAL) 482#define CCS_R_MAX_EXT_CLK_FREQ_MHZ (CCI_REG32(0x1104) | CCS_FL_FLOAT_IREAL) 483#define CCS_R_MIN_PRE_PLL_CLK_DIV CCI_REG16(0x1108) 484#define CCS_R_MAX_PRE_PLL_CLK_DIV CCI_REG16(0x110a) 485#define CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x110c) | CCS_FL_FLOAT_IREAL) 486#define CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x1110) | CCS_FL_FLOAT_IREAL) 487#define CCS_R_MIN_PLL_MULTIPLIER CCI_REG16(0x1114) 488#define CCS_R_MAX_PLL_MULTIPLIER CCI_REG16(0x1116) 489#define CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x1118) | CCS_FL_FLOAT_IREAL) 490#define CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x111c) | CCS_FL_FLOAT_IREAL) 491#define CCS_R_MIN_VT_SYS_CLK_DIV CCI_REG16(0x1120) 492#define CCS_R_MAX_VT_SYS_CLK_DIV CCI_REG16(0x1122) 493#define CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ (CCI_REG32(0x1124) | CCS_FL_FLOAT_IREAL) 494#define CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ (CCI_REG32(0x1128) | CCS_FL_FLOAT_IREAL) 495#define CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ (CCI_REG32(0x112c) | CCS_FL_FLOAT_IREAL) 496#define CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ (CCI_REG32(0x1130) | CCS_FL_FLOAT_IREAL) 497#define CCS_R_MIN_VT_PIX_CLK_DIV CCI_REG16(0x1134) 498#define CCS_R_MAX_VT_PIX_CLK_DIV CCI_REG16(0x1136) 499#define CCS_R_CLOCK_CALCULATION CCI_REG8(0x1138) 500#define CCS_CLOCK_CALCULATION_LANE_SPEED BIT(0) 501#define CCS_CLOCK_CALCULATION_LINK_DECOUPLED BIT(1) 502#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR BIT(2) 503#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR BIT(3) 504#define CCS_R_NUM_OF_VT_LANES CCI_REG8(0x1139) 505#define CCS_R_NUM_OF_OP_LANES CCI_REG8(0x113a) 506#define CCS_R_OP_BITS_PER_LANE CCI_REG8(0x113b) 507#define CCS_R_MIN_FRAME_LENGTH_LINES CCI_REG16(0x1140) 508#define CCS_R_MAX_FRAME_LENGTH_LINES CCI_REG16(0x1142) 509#define CCS_R_MIN_LINE_LENGTH_PCK CCI_REG16(0x1144) 510#define CCS_R_MAX_LINE_LENGTH_PCK CCI_REG16(0x1146) 511#define CCS_R_MIN_LINE_BLANKING_PCK CCI_REG16(0x1148) 512#define CCS_R_MIN_FRAME_BLANKING_LINES CCI_REG16(0x114a) 513#define CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE CCI_REG8(0x114c) 514#define CCS_R_TIMING_MODE_CAPABILITY CCI_REG8(0x114d) 515#define CCS_TIMING_MODE_CAPABILITY_AUTO_FRAME_LENGTH BIT(0) 516#define CCS_TIMING_MODE_CAPABILITY_ROLLING_SHUTTER_MANUAL_READOUT BIT(2) 517#define CCS_TIMING_MODE_CAPABILITY_DELAYED_EXPOSURE_START BIT(3) 518#define CCS_TIMING_MODE_CAPABILITY_MANUAL_EXPOSURE_EMBEDDED_DATA BIT(4) 519#define CCS_R_FRAME_MARGIN_MAX_VALUE CCI_REG16(0x114e) 520#define CCS_R_FRAME_MARGIN_MIN_VALUE CCI_REG8(0x1150) 521#define CCS_R_GAIN_DELAY_TYPE CCI_REG8(0x1151) 522#define CCS_GAIN_DELAY_TYPE_FIXED 0U 523#define CCS_GAIN_DELAY_TYPE_VARIABLE 1U 524#define CCS_R_MIN_OP_SYS_CLK_DIV CCI_REG16(0x1160) 525#define CCS_R_MAX_OP_SYS_CLK_DIV CCI_REG16(0x1162) 526#define CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ (CCI_REG32(0x1164) | CCS_FL_FLOAT_IREAL) 527#define CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ (CCI_REG32(0x1168) | CCS_FL_FLOAT_IREAL) 528#define CCS_R_MIN_OP_PIX_CLK_DIV CCI_REG16(0x116c) 529#define CCS_R_MAX_OP_PIX_CLK_DIV CCI_REG16(0x116e) 530#define CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ (CCI_REG32(0x1170) | CCS_FL_FLOAT_IREAL) 531#define CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ (CCI_REG32(0x1174) | CCS_FL_FLOAT_IREAL) 532#define CCS_R_X_ADDR_MIN CCI_REG16(0x1180) 533#define CCS_R_Y_ADDR_MIN CCI_REG16(0x1182) 534#define CCS_R_X_ADDR_MAX CCI_REG16(0x1184) 535#define CCS_R_Y_ADDR_MAX CCI_REG16(0x1186) 536#define CCS_R_MIN_X_OUTPUT_SIZE CCI_REG16(0x1188) 537#define CCS_R_MIN_Y_OUTPUT_SIZE CCI_REG16(0x118a) 538#define CCS_R_MAX_X_OUTPUT_SIZE CCI_REG16(0x118c) 539#define CCS_R_MAX_Y_OUTPUT_SIZE CCI_REG16(0x118e) 540#define CCS_R_X_ADDR_START_DIV_CONSTANT CCI_REG8(0x1190) 541#define CCS_R_Y_ADDR_START_DIV_CONSTANT CCI_REG8(0x1191) 542#define CCS_R_X_ADDR_END_DIV_CONSTANT CCI_REG8(0x1192) 543#define CCS_R_Y_ADDR_END_DIV_CONSTANT CCI_REG8(0x1193) 544#define CCS_R_X_SIZE_DIV CCI_REG8(0x1194) 545#define CCS_R_Y_SIZE_DIV CCI_REG8(0x1195) 546#define CCS_R_X_OUTPUT_DIV CCI_REG8(0x1196) 547#define CCS_R_Y_OUTPUT_DIV CCI_REG8(0x1197) 548#define CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT CCI_REG8(0x1198) 549#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_PIX_ADDR BIT(0) 550#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_OUTPUT_RES BIT(1) 551#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_CROP_NO_PAD BIT(2) 552#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_SIZE_LANE_DEP BIT(3) 553#define CCS_R_MIN_OP_PRE_PLL_CLK_DIV CCI_REG16(0x11a0) 554#define CCS_R_MAX_OP_PRE_PLL_CLK_DIV CCI_REG16(0x11a2) 555#define CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x11a4) | CCS_FL_FLOAT_IREAL) 556#define CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x11a8) | CCS_FL_FLOAT_IREAL) 557#define CCS_R_MIN_OP_PLL_MULTIPLIER CCI_REG16(0x11ac) 558#define CCS_R_MAX_OP_PLL_MULTIPLIER CCI_REG16(0x11ae) 559#define CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x11b0) | CCS_FL_FLOAT_IREAL) 560#define CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x11b4) | CCS_FL_FLOAT_IREAL) 561#define CCS_R_CLOCK_TREE_PLL_CAPABILITY CCI_REG8(0x11b8) 562#define CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL BIT(0) 563#define CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL BIT(1) 564#define CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER BIT(2) 565#define CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV BIT(3) 566#define CCS_R_CLOCK_CAPA_TYPE_CAPABILITY CCI_REG8(0x11b9) 567#define CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL BIT(0) 568#define CCS_R_MIN_EVEN_INC CCI_REG16(0x11c0) 569#define CCS_R_MIN_ODD_INC CCI_REG16(0x11c2) 570#define CCS_R_MAX_EVEN_INC CCI_REG16(0x11c4) 571#define CCS_R_MAX_ODD_INC CCI_REG16(0x11c6) 572#define CCS_R_AUX_SUBSAMP_CAPABILITY CCI_REG8(0x11c8) 573#define CCS_AUX_SUBSAMP_CAPABILITY_FACTOR_POWER_OF_2 BIT(1) 574#define CCS_R_AUX_SUBSAMP_MONO_CAPABILITY CCI_REG8(0x11c9) 575#define CCS_AUX_SUBSAMP_MONO_CAPABILITY_FACTOR_POWER_OF_2 BIT(1) 576#define CCS_R_MONOCHROME_CAPABILITY CCI_REG8(0x11ca) 577#define CCS_MONOCHROME_CAPABILITY_INC_ODD 0U 578#define CCS_MONOCHROME_CAPABILITY_INC_EVEN 1U 579#define CCS_R_PIXEL_READOUT_CAPABILITY CCI_REG8(0x11cb) 580#define CCS_PIXEL_READOUT_CAPABILITY_BAYER 0U 581#define CCS_PIXEL_READOUT_CAPABILITY_MONOCHROME 1U 582#define CCS_PIXEL_READOUT_CAPABILITY_BAYER_AND_MONO 2U 583#define CCS_R_MIN_EVEN_INC_MONO CCI_REG16(0x11cc) 584#define CCS_R_MAX_EVEN_INC_MONO CCI_REG16(0x11ce) 585#define CCS_R_MIN_ODD_INC_MONO CCI_REG16(0x11d0) 586#define CCS_R_MAX_ODD_INC_MONO CCI_REG16(0x11d2) 587#define CCS_R_MIN_EVEN_INC_BC2 CCI_REG16(0x11d4) 588#define CCS_R_MAX_EVEN_INC_BC2 CCI_REG16(0x11d6) 589#define CCS_R_MIN_ODD_INC_BC2 CCI_REG16(0x11d8) 590#define CCS_R_MAX_ODD_INC_BC2 CCI_REG16(0x11da) 591#define CCS_R_MIN_EVEN_INC_MONO_BC2 CCI_REG16(0x11dc) 592#define CCS_R_MAX_EVEN_INC_MONO_BC2 CCI_REG16(0x11de) 593#define CCS_R_MIN_ODD_INC_MONO_BC2 CCI_REG16(0x11f0) 594#define CCS_R_MAX_ODD_INC_MONO_BC2 CCI_REG16(0x11f2) 595#define CCS_R_SCALING_CAPABILITY CCI_REG16(0x1200) 596#define CCS_SCALING_CAPABILITY_NONE 0U 597#define CCS_SCALING_CAPABILITY_HORIZONTAL 1U 598#define CCS_SCALING_CAPABILITY_RESERVED 2U 599#define CCS_R_SCALER_M_MIN CCI_REG16(0x1204) 600#define CCS_R_SCALER_M_MAX CCI_REG16(0x1206) 601#define CCS_R_SCALER_N_MIN CCI_REG16(0x1208) 602#define CCS_R_SCALER_N_MAX CCI_REG16(0x120a) 603#define CCS_R_DIGITAL_CROP_CAPABILITY CCI_REG8(0x120e) 604#define CCS_DIGITAL_CROP_CAPABILITY_NONE 0U 605#define CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1U 606#define CCS_R_HDR_CAPABILITY_1 CCI_REG8(0x1210) 607#define CCS_HDR_CAPABILITY_1_2X2_BINNING BIT(0) 608#define CCS_HDR_CAPABILITY_1_COMBINED_ANALOG_GAIN BIT(1) 609#define CCS_HDR_CAPABILITY_1_SEPARATE_ANALOG_GAIN BIT(2) 610#define CCS_HDR_CAPABILITY_1_UPSCALING BIT(3) 611#define CCS_HDR_CAPABILITY_1_RESET_SYNC BIT(4) 612#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_TIMING BIT(5) 613#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_SYNTHESIS BIT(6) 614#define CCS_R_MIN_HDR_BIT_DEPTH CCI_REG8(0x1211) 615#define CCS_R_HDR_RESOLUTION_SUB_TYPES CCI_REG8(0x1212) 616#define CCS_R_HDR_RESOLUTION_SUB_TYPE(n) CCI_REG8(0x1213 + (n)) 617#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MIN_N 0U 618#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MAX_N 1U 619#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_SHIFT 0U 620#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_MASK 0xf 621#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_SHIFT 4U 622#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_MASK 0xf0 623#define CCS_R_HDR_CAPABILITY_2 CCI_REG8(0x121b) 624#define CCS_HDR_CAPABILITY_2_COMBINED_DIGITAL_GAIN BIT(0) 625#define CCS_HDR_CAPABILITY_2_SEPARATE_DIGITAL_GAIN BIT(1) 626#define CCS_HDR_CAPABILITY_2_TIMING_MODE BIT(3) 627#define CCS_HDR_CAPABILITY_2_SYNTHESIS_MODE BIT(4) 628#define CCS_R_MAX_HDR_BIT_DEPTH CCI_REG8(0x121c) 629#define CCS_R_USL_SUPPORT_CAPABILITY CCI_REG8(0x1230) 630#define CCS_USL_SUPPORT_CAPABILITY_CLOCK_TREE BIT(0) 631#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_TREE BIT(1) 632#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_CALC BIT(2) 633#define CCS_R_USL_CLOCK_MODE_D_CAPABILITY CCI_REG8(0x1231) 634#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_STANDBY BIT(0) 635#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_VBLANK BIT(1) 636#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_HBLANK BIT(2) 637#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_STANDBY BIT(3) 638#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_VBLANK BIT(4) 639#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_HBLANK BIT(5) 640#define CCS_R_MIN_OP_SYS_CLK_DIV_REV CCI_REG8(0x1234) 641#define CCS_R_MAX_OP_SYS_CLK_DIV_REV CCI_REG8(0x1236) 642#define CCS_R_MIN_OP_PIX_CLK_DIV_REV CCI_REG8(0x1238) 643#define CCS_R_MAX_OP_PIX_CLK_DIV_REV CCI_REG8(0x123a) 644#define CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ (CCI_REG32(0x123c) | CCS_FL_FLOAT_IREAL) 645#define CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ (CCI_REG32(0x1240) | CCS_FL_FLOAT_IREAL) 646#define CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ (CCI_REG32(0x1244) | CCS_FL_FLOAT_IREAL) 647#define CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ (CCI_REG32(0x1248) | CCS_FL_FLOAT_IREAL) 648#define CCS_R_MAX_BITRATE_REV_D_MODE_MBPS (CCI_REG32(0x124c) | CCS_FL_IREAL) 649#define CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS (CCI_REG32(0x1250) | CCS_FL_IREAL) 650#define CCS_R_COMPRESSION_CAPABILITY CCI_REG8(0x1300) 651#define CCS_COMPRESSION_CAPABILITY_DPCM_PCM_SIMPLE BIT(0) 652#define CCS_R_TEST_MODE_CAPABILITY CCI_REG16(0x1310) 653#define CCS_TEST_MODE_CAPABILITY_SOLID_COLOR BIT(0) 654#define CCS_TEST_MODE_CAPABILITY_COLOR_BARS BIT(1) 655#define CCS_TEST_MODE_CAPABILITY_FADE_TO_GREY BIT(2) 656#define CCS_TEST_MODE_CAPABILITY_PN9 BIT(3) 657#define CCS_TEST_MODE_CAPABILITY_COLOR_TILE BIT(5) 658#define CCS_R_PN9_DATA_FORMAT1 CCI_REG8(0x1312) 659#define CCS_R_PN9_DATA_FORMAT2 CCI_REG8(0x1313) 660#define CCS_R_PN9_DATA_FORMAT3 CCI_REG8(0x1314) 661#define CCS_R_PN9_DATA_FORMAT4 CCI_REG8(0x1315) 662#define CCS_R_PN9_MISC_CAPABILITY CCI_REG8(0x1316) 663#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_SHIFT 0U 664#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_MASK 0x7 665#define CCS_PN9_MISC_CAPABILITY_COMPRESSION BIT(3) 666#define CCS_R_TEST_PATTERN_CAPABILITY CCI_REG8(0x1317) 667#define CCS_TEST_PATTERN_CAPABILITY_NO_REPEAT BIT(1) 668#define CCS_R_PATTERN_SIZE_DIV_M1 CCI_REG8(0x1318) 669#define CCS_R_FIFO_SUPPORT_CAPABILITY CCI_REG8(0x1502) 670#define CCS_FIFO_SUPPORT_CAPABILITY_NONE 0U 671#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING 1U 672#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING 2U 673#define CCS_R_PHY_CTRL_CAPABILITY CCI_REG8(0x1600) 674#define CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL BIT(0) 675#define CCS_PHY_CTRL_CAPABILITY_UI_PHY_CTL BIT(1) 676#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_1_CTL BIT(2) 677#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_2_CTL BIT(3) 678#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_CTL BIT(4) 679#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_1_CTL BIT(5) 680#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_2_CTL BIT(6) 681#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_CTL BIT(7) 682#define CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY CCI_REG8(0x1601) 683#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0) 684#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1) 685#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2) 686#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3) 687#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4) 688#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5) 689#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6) 690#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7) 691#define CCS_R_CSI_SIGNALING_MODE_CAPABILITY CCI_REG8(0x1602) 692#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_DPHY BIT(2) 693#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_CPHY BIT(3) 694#define CCS_R_FAST_STANDBY_CAPABILITY CCI_REG8(0x1603) 695#define CCS_FAST_STANDBY_CAPABILITY_NO_FRAME_TRUNCATION 0U 696#define CCS_FAST_STANDBY_CAPABILITY_FRAME_TRUNCATION 1U 697#define CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY CCI_REG8(0x1604) 698#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_CCI_ADDR_CHANGE BIT(0) 699#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_2ND_CCI_ADDR BIT(1) 700#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_SW_CHANGEABLE_2ND_CCI_ADDR BIT(2) 701#define CCS_R_DATA_TYPE_CAPABILITY CCI_REG8(0x1605) 702#define CCS_DATA_TYPE_CAPABILITY_DPCM_PROGRAMMABLE BIT(0) 703#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_DT_PROGRAMMABLE BIT(1) 704#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_VC_PROGRAMMABLE BIT(2) 705#define CCS_DATA_TYPE_CAPABILITY_EXT_VC_RANGE BIT(3) 706#define CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY CCI_REG8(0x1606) 707#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0) 708#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1) 709#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2) 710#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3) 711#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4) 712#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5) 713#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6) 714#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7) 715#define CCS_R_EMB_DATA_CAPABILITY CCI_REG8(0x1607) 716#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW16 BIT(0) 717#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW20 BIT(1) 718#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW24 BIT(2) 719#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW16 BIT(3) 720#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW20 BIT(4) 721#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW24 BIT(5) 722#define CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(n) (CCI_REG32(0x1608 + ((n) < 4 ? (n) * 4 : 0x32 + ((n) - 4) * 4)) | CCS_FL_IREAL) 723#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MIN_N 0U 724#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MAX_N 7U 725#define CCS_R_TEMP_SENSOR_CAPABILITY CCI_REG8(0x1618) 726#define CCS_TEMP_SENSOR_CAPABILITY_SUPPORTED BIT(0) 727#define CCS_TEMP_SENSOR_CAPABILITY_CCS_FORMAT BIT(1) 728#define CCS_TEMP_SENSOR_CAPABILITY_RESET_0X80 BIT(2) 729#define CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(n) (CCI_REG32(0x161a + ((n) < 4 ? (n) * 4 : 0x30 + ((n) - 4) * 4)) | CCS_FL_IREAL) 730#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MIN_N 0U 731#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MAX_N 7U 732#define CCS_R_DPHY_EQUALIZATION_CAPABILITY CCI_REG8(0x162b) 733#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0) 734#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ1 BIT(1) 735#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ2 BIT(2) 736#define CCS_R_CPHY_EQUALIZATION_CAPABILITY CCI_REG8(0x162c) 737#define CCS_CPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0) 738#define CCS_R_DPHY_PREAMBLE_CAPABILITY CCI_REG8(0x162d) 739#define CCS_DPHY_PREAMBLE_CAPABILITY_PREAMBLE_SEQ_CTRL BIT(0) 740#define CCS_R_DPHY_SSC_CAPABILITY CCI_REG8(0x162e) 741#define CCS_DPHY_SSC_CAPABILITY_SUPPORTED BIT(0) 742#define CCS_R_CPHY_CALIBRATION_CAPABILITY CCI_REG8(0x162f) 743#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0) 744#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1) 745#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_1_CTRL BIT(2) 746#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_2_CTRL BIT(3) 747#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_3_CTRL BIT(4) 748#define CCS_R_DPHY_CALIBRATION_CAPABILITY CCI_REG8(0x1630) 749#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0) 750#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1) 751#define CCS_DPHY_CALIBRATION_CAPABILITY_ALTERNATE_SEQ BIT(2) 752#define CCS_R_PHY_CTRL_CAPABILITY_2 CCI_REG8(0x1631) 753#define CCS_PHY_CTRL_CAPABILITY_2_TGR_LENGTH BIT(0) 754#define CCS_PHY_CTRL_CAPABILITY_2_TGR_PREAMBLE_PROG_SEQ BIT(1) 755#define CCS_PHY_CTRL_CAPABILITY_2_EXTRA_CPHY_MANUAL_TIMING BIT(2) 756#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CDPHY BIT(3) 757#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_DPHY BIT(4) 758#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CPHY BIT(5) 759#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_DPHY BIT(6) 760#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_CPHY BIT(7) 761#define CCS_R_LRTE_CPHY_CAPABILITY CCI_REG8(0x1632) 762#define CCS_LRTE_CPHY_CAPABILITY_PDQ_SHORT BIT(0) 763#define CCS_LRTE_CPHY_CAPABILITY_SPACER_SHORT BIT(1) 764#define CCS_LRTE_CPHY_CAPABILITY_PDQ_LONG BIT(2) 765#define CCS_LRTE_CPHY_CAPABILITY_SPACER_LONG BIT(3) 766#define CCS_LRTE_CPHY_CAPABILITY_SPACER_NO_PDQ BIT(4) 767#define CCS_R_LRTE_DPHY_CAPABILITY CCI_REG8(0x1633) 768#define CCS_LRTE_DPHY_CAPABILITY_PDQ_SHORT_OPT1 BIT(0) 769#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT1 BIT(1) 770#define CCS_LRTE_DPHY_CAPABILITY_PDQ_LONG_OPT1 BIT(2) 771#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT1 BIT(3) 772#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT2 BIT(4) 773#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT2 BIT(5) 774#define CCS_LRTE_DPHY_CAPABILITY_SPACER_NO_PDQ_OPT1 BIT(6) 775#define CCS_LRTE_DPHY_CAPABILITY_SPACER_VARIABLE_OPT2 BIT(7) 776#define CCS_R_ALPS_CAPABILITY_DPHY CCI_REG8(0x1634) 777#define CCS_ALPS_CAPABILITY_DPHY_LVLP_NOT_SUPPORTED 0U 778#define CCS_ALPS_CAPABILITY_DPHY_LVLP_SUPPORTED 1U 779#define CCS_ALPS_CAPABILITY_DPHY_CONTROLLABLE_LVLP 2U 780#define CCS_R_ALPS_CAPABILITY_CPHY CCI_REG8(0x1635) 781#define CCS_ALPS_CAPABILITY_CPHY_LVLP_NOT_SUPPORTED 0U 782#define CCS_ALPS_CAPABILITY_CPHY_LVLP_SUPPORTED 1U 783#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_LVLP 2U 784#define CCS_ALPS_CAPABILITY_CPHY_ALP_NOT_SUPPORTED 0xc 785#define CCS_ALPS_CAPABILITY_CPHY_ALP_SUPPORTED 0xd 786#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_ALP 0xe 787#define CCS_R_SCRAMBLING_CAPABILITY CCI_REG8(0x1636) 788#define CCS_SCRAMBLING_CAPABILITY_SCRAMBLING_SUPPORTED BIT(0) 789#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_SHIFT 1U 790#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_MASK 0x6 791#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_1 0U 792#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_4 3U 793#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_SHIFT 3U 794#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_MASK 0x38 795#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_0 0U 796#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_1 1U 797#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_4 4U 798#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_PER_LANE BIT(6) 799#define CCS_R_DPHY_MANUAL_CONSTANT CCI_REG8(0x1637) 800#define CCS_R_CPHY_MANUAL_CONSTANT CCI_REG8(0x1638) 801#define CCS_R_CSI2_INTERFACE_CAPABILITY_MISC CCI_REG8(0x1639) 802#define CCS_CSI2_INTERFACE_CAPABILITY_MISC_EOTP_SHORT_PKT_OPT2 BIT(0) 803#define CCS_R_PHY_CTRL_CAPABILITY_3 CCI_REG8(0x165c) 804#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_TIMING_NOT_MULTIPLE BIT(0) 805#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_MIN_TIMING_VALUE_1 BIT(1) 806#define CCS_PHY_CTRL_CAPABILITY_3_TWAKEUP_SUPPORTED BIT(2) 807#define CCS_PHY_CTRL_CAPABILITY_3_TINIT_SUPPORTED BIT(3) 808#define CCS_PHY_CTRL_CAPABILITY_3_THS_EXIT_SUPPORTED BIT(4) 809#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_TIMING_NOT_MULTIPLE BIT(5) 810#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_MIN_TIMING_VALUE_1 BIT(6) 811#define CCS_R_DPHY_SF CCI_REG8(0x165d) 812#define CCS_R_CPHY_SF CCI_REG8(0x165e) 813#define CCS_CPHY_SF_TWAKEUP_SHIFT 0U 814#define CCS_CPHY_SF_TWAKEUP_MASK 0xf 815#define CCS_CPHY_SF_TINIT_SHIFT 4U 816#define CCS_CPHY_SF_TINIT_MASK 0xf0 817#define CCS_R_DPHY_LIMITS_1 CCI_REG8(0x165f) 818#define CCS_DPHY_LIMITS_1_THS_PREPARE_SHIFT 0U 819#define CCS_DPHY_LIMITS_1_THS_PREPARE_MASK 0xf 820#define CCS_DPHY_LIMITS_1_THS_ZERO_SHIFT 4U 821#define CCS_DPHY_LIMITS_1_THS_ZERO_MASK 0xf0 822#define CCS_R_DPHY_LIMITS_2 CCI_REG8(0x1660) 823#define CCS_DPHY_LIMITS_2_THS_TRAIL_SHIFT 0U 824#define CCS_DPHY_LIMITS_2_THS_TRAIL_MASK 0xf 825#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_SHIFT 4U 826#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_MASK 0xf0 827#define CCS_R_DPHY_LIMITS_3 CCI_REG8(0x1661) 828#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_SHIFT 0U 829#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_MASK 0xf 830#define CCS_DPHY_LIMITS_3_TCLK_ZERO_SHIFT 4U 831#define CCS_DPHY_LIMITS_3_TCLK_ZERO_MASK 0xf0 832#define CCS_R_DPHY_LIMITS_4 CCI_REG8(0x1662) 833#define CCS_DPHY_LIMITS_4_TCLK_POST_SHIFT 0U 834#define CCS_DPHY_LIMITS_4_TCLK_POST_MASK 0xf 835#define CCS_DPHY_LIMITS_4_TLPX_SHIFT 4U 836#define CCS_DPHY_LIMITS_4_TLPX_MASK 0xf0 837#define CCS_R_DPHY_LIMITS_5 CCI_REG8(0x1663) 838#define CCS_DPHY_LIMITS_5_THS_EXIT_SHIFT 0U 839#define CCS_DPHY_LIMITS_5_THS_EXIT_MASK 0xf 840#define CCS_DPHY_LIMITS_5_TWAKEUP_SHIFT 4U 841#define CCS_DPHY_LIMITS_5_TWAKEUP_MASK 0xf0 842#define CCS_R_DPHY_LIMITS_6 CCI_REG8(0x1664) 843#define CCS_DPHY_LIMITS_6_TINIT_SHIFT 0U 844#define CCS_DPHY_LIMITS_6_TINIT_MASK 0xf 845#define CCS_R_CPHY_LIMITS_1 CCI_REG8(0x1665) 846#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_SHIFT 0U 847#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_MASK 0xf 848#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_SHIFT 4U 849#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_MASK 0xf0 850#define CCS_R_CPHY_LIMITS_2 CCI_REG8(0x1666) 851#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_SHIFT 0U 852#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_MASK 0xf 853#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_SHIFT 4U 854#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_MASK 0xf0 855#define CCS_R_CPHY_LIMITS_3 CCI_REG8(0x1667) 856#define CCS_CPHY_LIMITS_3_TINIT_MAX_SHIFT 0U 857#define CCS_CPHY_LIMITS_3_TINIT_MAX_MASK 0xf 858#define CCS_R_MIN_FRAME_LENGTH_LINES_BIN CCI_REG16(0x1700) 859#define CCS_R_MAX_FRAME_LENGTH_LINES_BIN CCI_REG16(0x1702) 860#define CCS_R_MIN_LINE_LENGTH_PCK_BIN CCI_REG16(0x1704) 861#define CCS_R_MAX_LINE_LENGTH_PCK_BIN CCI_REG16(0x1706) 862#define CCS_R_MIN_LINE_BLANKING_PCK_BIN CCI_REG16(0x1708) 863#define CCS_R_FINE_INTEGRATION_TIME_MIN_BIN CCI_REG16(0x170a) 864#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN CCI_REG16(0x170c) 865#define CCS_R_BINNING_CAPABILITY CCI_REG8(0x1710) 866#define CCS_BINNING_CAPABILITY_UNSUPPORTED 0U 867#define CCS_BINNING_CAPABILITY_BINNING_THEN_SUBSAMPLING 1U 868#define CCS_BINNING_CAPABILITY_SUBSAMPLING_THEN_BINNING 2U 869#define CCS_R_BINNING_WEIGHTING_CAPABILITY CCI_REG8(0x1711) 870#define CCS_BINNING_WEIGHTING_CAPABILITY_AVERAGED BIT(0) 871#define CCS_BINNING_WEIGHTING_CAPABILITY_SUMMED BIT(1) 872#define CCS_BINNING_WEIGHTING_CAPABILITY_BAYER_CORRECTED BIT(2) 873#define CCS_BINNING_WEIGHTING_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3) 874#define CCS_R_BINNING_SUB_TYPES CCI_REG8(0x1712) 875#define CCS_R_BINNING_SUB_TYPE(n) CCI_REG8(0x1713 + (n)) 876#define CCS_LIM_BINNING_SUB_TYPE_MIN_N 0U 877#define CCS_LIM_BINNING_SUB_TYPE_MAX_N 63U 878#define CCS_BINNING_SUB_TYPE_ROW_SHIFT 0U 879#define CCS_BINNING_SUB_TYPE_ROW_MASK 0xf 880#define CCS_BINNING_SUB_TYPE_COLUMN_SHIFT 4U 881#define CCS_BINNING_SUB_TYPE_COLUMN_MASK 0xf0 882#define CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY CCI_REG8(0x1771) 883#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_AVERAGED BIT(0) 884#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_SUMMED BIT(1) 885#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_BAYER_CORRECTED BIT(2) 886#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3) 887#define CCS_R_BINNING_SUB_TYPES_MONO CCI_REG8(0x1772) 888#define CCS_R_BINNING_SUB_TYPE_MONO(n) CCI_REG8(0x1773 + (n)) 889#define CCS_LIM_BINNING_SUB_TYPE_MONO_MIN_N 0U 890#define CCS_LIM_BINNING_SUB_TYPE_MONO_MAX_N 63U 891#define CCS_R_DATA_TRANSFER_IF_CAPABILITY CCI_REG8(0x1800) 892#define CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0) 893#define CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING BIT(2) 894#define CCS_R_SHADING_CORRECTION_CAPABILITY CCI_REG8(0x1900) 895#define CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING BIT(0) 896#define CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION BIT(1) 897#define CCS_R_GREEN_IMBALANCE_CAPABILITY CCI_REG8(0x1901) 898#define CCS_GREEN_IMBALANCE_CAPABILITY_SUPPORTED BIT(0) 899#define CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY CCI_REG8(0x1903) 900#define CCS_R_DEFECT_CORRECTION_CAPABILITY CCI_REG16(0x1904) 901#define CCS_DEFECT_CORRECTION_CAPABILITY_MAPPED_DEFECT BIT(0) 902#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_COUPLET BIT(2) 903#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_SINGLE BIT(5) 904#define CCS_DEFECT_CORRECTION_CAPABILITY_COMBINED_DYNAMIC BIT(8) 905#define CCS_R_DEFECT_CORRECTION_CAPABILITY_2 CCI_REG16(0x1906) 906#define CCS_DEFECT_CORRECTION_CAPABILITY_2_DYNAMIC_TRIPLET BIT(3) 907#define CCS_R_NF_CAPABILITY CCI_REG8(0x1908) 908#define CCS_NF_CAPABILITY_LUMA BIT(0) 909#define CCS_NF_CAPABILITY_CHROMA BIT(1) 910#define CCS_NF_CAPABILITY_COMBINED BIT(2) 911#define CCS_R_OB_READOUT_CAPABILITY CCI_REG8(0x1980) 912#define CCS_OB_READOUT_CAPABILITY_CONTROLLABLE_READOUT BIT(0) 913#define CCS_OB_READOUT_CAPABILITY_VISIBLE_PIXEL_READOUT BIT(1) 914#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_VC_READOUT BIT(2) 915#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_DT_READOUT BIT(3) 916#define CCS_OB_READOUT_CAPABILITY_PROG_DATA_FORMAT BIT(4) 917#define CCS_R_COLOR_FEEDBACK_CAPABILITY CCI_REG8(0x1987) 918#define CCS_COLOR_FEEDBACK_CAPABILITY_KELVIN BIT(0) 919#define CCS_COLOR_FEEDBACK_CAPABILITY_AWB_GAIN BIT(1) 920#define CCS_R_CFA_PATTERN_CAPABILITY CCI_REG8(0x1990) 921#define CCS_CFA_PATTERN_CAPABILITY_BAYER 0U 922#define CCS_CFA_PATTERN_CAPABILITY_MONOCHROME 1U 923#define CCS_CFA_PATTERN_CAPABILITY_4X4_QUAD_BAYER 2U 924#define CCS_CFA_PATTERN_CAPABILITY_VENDOR_SPECIFIC 3U 925#define CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY CCI_REG8(0x1991) 926#define CCS_CFA_PATTERN_CONVERSION_CAPABILITY_BAYER BIT(0) 927#define CCS_R_FLASH_MODE_CAPABILITY CCI_REG8(0x1a02) 928#define CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0) 929#define CCS_R_SA_STROBE_MODE_CAPABILITY CCI_REG8(0x1a03) 930#define CCS_SA_STROBE_MODE_CAPABILITY_FIXED_WIDTH BIT(0) 931#define CCS_SA_STROBE_MODE_CAPABILITY_EDGE_CTRL BIT(1) 932#define CCS_R_RESET_MAX_DELAY CCI_REG8(0x1a10) 933#define CCS_R_RESET_MIN_TIME CCI_REG8(0x1a11) 934#define CCS_R_PDAF_CAPABILITY_1 CCI_REG8(0x1b80) 935#define CCS_PDAF_CAPABILITY_1_SUPPORTED BIT(0) 936#define CCS_PDAF_CAPABILITY_1_PROCESSED_BOTTOM_EMBEDDED BIT(1) 937#define CCS_PDAF_CAPABILITY_1_PROCESSED_INTERLEAVED BIT(2) 938#define CCS_PDAF_CAPABILITY_1_RAW_BOTTOM_EMBEDDED BIT(3) 939#define CCS_PDAF_CAPABILITY_1_RAW_INTERLEAVED BIT(4) 940#define CCS_PDAF_CAPABILITY_1_VISIBLE_PDAF_CORRECTION BIT(5) 941#define CCS_PDAF_CAPABILITY_1_VC_INTERLEAVING BIT(6) 942#define CCS_PDAF_CAPABILITY_1_DT_INTERLEAVING BIT(7) 943#define CCS_R_PDAF_CAPABILITY_2 CCI_REG8(0x1b81) 944#define CCS_PDAF_CAPABILITY_2_ROI BIT(0) 945#define CCS_PDAF_CAPABILITY_2_AFTER_DIGITAL_CROP BIT(1) 946#define CCS_PDAF_CAPABILITY_2_CTRL_RETIMED BIT(2) 947#define CCS_R_BRACKETING_LUT_CAPABILITY_1 CCI_REG8(0x1c00) 948#define CCS_BRACKETING_LUT_CAPABILITY_1_COARSE_INTEGRATION BIT(0) 949#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_ANALOG_GAIN BIT(1) 950#define CCS_BRACKETING_LUT_CAPABILITY_1_FLASH BIT(4) 951#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_DIGITAL_GAIN BIT(5) 952#define CCS_BRACKETING_LUT_CAPABILITY_1_ALTERNATE_GLOBAL_ANALOG_GAIN BIT(6) 953#define CCS_R_BRACKETING_LUT_CAPABILITY_2 CCI_REG8(0x1c01) 954#define CCS_BRACKETING_LUT_CAPABILITY_2_SINGLE_BRACKETING_MODE BIT(0) 955#define CCS_BRACKETING_LUT_CAPABILITY_2_LOOPED_BRACKETING_MODE BIT(1) 956#define CCS_R_BRACKETING_LUT_SIZE CCI_REG8(0x1c02) 957 958#endif /* __CCS_REGS_H__ */ 959