1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * ADV7393 encoder related structure and register definitions
4 *
5 * Copyright (C) 2010-2012 ADVANSEE - http://www.advansee.com/
6 * Beno��t Th��baudeau <benoit.thebaudeau@advansee.com>
7 *
8 * Based on ADV7343 driver,
9 *
10 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
11 */
12
13#ifndef ADV7393_REGS_H
14#define ADV7393_REGS_H
15
16struct adv7393_std_info {
17	u32 standard_val3;
18	u32 fsc_val;
19	v4l2_std_id stdid;
20};
21
22/* Register offset macros */
23#define ADV7393_POWER_MODE_REG		(0x00)
24#define ADV7393_MODE_SELECT_REG		(0x01)
25#define ADV7393_MODE_REG0		(0x02)
26
27#define ADV7393_DAC123_OUTPUT_LEVEL	(0x0B)
28
29#define ADV7393_SOFT_RESET		(0x17)
30
31#define ADV7393_HD_MODE_REG1		(0x30)
32#define ADV7393_HD_MODE_REG2		(0x31)
33#define ADV7393_HD_MODE_REG3		(0x32)
34#define ADV7393_HD_MODE_REG4		(0x33)
35#define ADV7393_HD_MODE_REG5		(0x34)
36#define ADV7393_HD_MODE_REG6		(0x35)
37
38#define ADV7393_HD_MODE_REG7		(0x39)
39
40#define ADV7393_SD_MODE_REG1		(0x80)
41#define ADV7393_SD_MODE_REG2		(0x82)
42#define ADV7393_SD_MODE_REG3		(0x83)
43#define ADV7393_SD_MODE_REG4		(0x84)
44#define ADV7393_SD_MODE_REG5		(0x86)
45#define ADV7393_SD_MODE_REG6		(0x87)
46#define ADV7393_SD_MODE_REG7		(0x88)
47#define ADV7393_SD_MODE_REG8		(0x89)
48
49#define ADV7393_SD_TIMING_REG0		(0x8A)
50
51#define ADV7393_FSC_REG0		(0x8C)
52#define ADV7393_FSC_REG1		(0x8D)
53#define ADV7393_FSC_REG2		(0x8E)
54#define ADV7393_FSC_REG3		(0x8F)
55
56#define ADV7393_SD_CGMS_WSS0		(0x99)
57
58#define ADV7393_SD_HUE_ADJUST		(0xA0)
59#define ADV7393_SD_BRIGHTNESS_WSS	(0xA1)
60
61/* Default values for the registers */
62#define ADV7393_POWER_MODE_REG_DEFAULT		(0x10)
63#define ADV7393_HD_MODE_REG1_DEFAULT		(0x3C)	/* Changed Default
64							   720p EAV/SAV code*/
65#define ADV7393_HD_MODE_REG2_DEFAULT		(0x01)	/* Changed Pixel data
66							   valid */
67#define ADV7393_HD_MODE_REG3_DEFAULT		(0x00)	/* Color delay 0 clks */
68#define ADV7393_HD_MODE_REG4_DEFAULT		(0xEC)	/* Changed */
69#define ADV7393_HD_MODE_REG5_DEFAULT		(0x08)
70#define ADV7393_HD_MODE_REG6_DEFAULT		(0x00)
71#define ADV7393_HD_MODE_REG7_DEFAULT		(0x00)
72#define ADV7393_SOFT_RESET_DEFAULT		(0x02)
73#define ADV7393_COMPOSITE_POWER_VALUE		(0x10)
74#define ADV7393_COMPONENT_POWER_VALUE		(0x1C)
75#define ADV7393_SVIDEO_POWER_VALUE		(0x0C)
76#define ADV7393_SD_HUE_ADJUST_DEFAULT		(0x80)
77#define ADV7393_SD_BRIGHTNESS_WSS_DEFAULT	(0x00)
78
79#define ADV7393_SD_CGMS_WSS0_DEFAULT		(0x10)
80
81#define ADV7393_SD_MODE_REG1_DEFAULT		(0x10)
82#define ADV7393_SD_MODE_REG2_DEFAULT		(0xC9)
83#define ADV7393_SD_MODE_REG3_DEFAULT		(0x00)
84#define ADV7393_SD_MODE_REG4_DEFAULT		(0x00)
85#define ADV7393_SD_MODE_REG5_DEFAULT		(0x02)
86#define ADV7393_SD_MODE_REG6_DEFAULT		(0x8C)
87#define ADV7393_SD_MODE_REG7_DEFAULT		(0x14)
88#define ADV7393_SD_MODE_REG8_DEFAULT		(0x00)
89
90#define ADV7393_SD_TIMING_REG0_DEFAULT		(0x0C)
91
92/* Bit masks for Mode Select Register */
93#define INPUT_MODE_MASK			(0x70)
94#define SD_INPUT_MODE			(0x00)
95#define HD_720P_INPUT_MODE		(0x10)
96#define HD_1080I_INPUT_MODE		(0x10)
97
98/* Bit masks for Mode Register 0 */
99#define TEST_PATTERN_BLACK_BAR_EN	(0x04)
100#define YUV_OUTPUT_SELECT		(0x20)
101#define RGB_OUTPUT_SELECT		(0xDF)
102
103/* Bit masks for SD brightness/WSS */
104#define SD_BRIGHTNESS_VALUE_MASK	(0x7F)
105#define SD_BLANK_WSS_DATA_MASK		(0x80)
106
107/* Bit masks for soft reset register */
108#define SOFT_RESET			(0x02)
109
110/* Bit masks for HD Mode Register 1 */
111#define OUTPUT_STD_MASK		(0x03)
112#define OUTPUT_STD_SHIFT	(0)
113#define OUTPUT_STD_EIA0_2	(0x00)
114#define OUTPUT_STD_EIA0_1	(0x01)
115#define OUTPUT_STD_FULL		(0x02)
116#define EMBEDDED_SYNC		(0x04)
117#define EXTERNAL_SYNC		(0xFB)
118#define STD_MODE_MASK		(0x1F)
119#define STD_MODE_SHIFT		(3)
120#define STD_MODE_720P		(0x05)
121#define STD_MODE_720P_25	(0x08)
122#define STD_MODE_720P_30	(0x07)
123#define STD_MODE_720P_50	(0x06)
124#define STD_MODE_1080I		(0x0D)
125#define STD_MODE_1080I_25	(0x0E)
126#define STD_MODE_1080P_24	(0x11)
127#define STD_MODE_1080P_25	(0x10)
128#define STD_MODE_1080P_30	(0x0F)
129#define STD_MODE_525P		(0x00)
130#define STD_MODE_625P		(0x03)
131
132/* Bit masks for SD Mode Register 1 */
133#define SD_STD_MASK		(0x03)
134#define SD_STD_NTSC		(0x00)
135#define SD_STD_PAL_BDGHI	(0x01)
136#define SD_STD_PAL_M		(0x02)
137#define SD_STD_PAL_N		(0x03)
138#define SD_LUMA_FLTR_MASK	(0x07)
139#define SD_LUMA_FLTR_SHIFT	(2)
140#define SD_CHROMA_FLTR_MASK	(0x07)
141#define SD_CHROMA_FLTR_SHIFT	(5)
142
143/* Bit masks for SD Mode Register 2 */
144#define SD_PRPB_SSAF_EN		(0x01)
145#define SD_PRPB_SSAF_DI		(0xFE)
146#define SD_DAC_OUT1_EN		(0x02)
147#define SD_DAC_OUT1_DI		(0xFD)
148#define SD_PEDESTAL_EN		(0x08)
149#define SD_PEDESTAL_DI		(0xF7)
150#define SD_SQUARE_PIXEL_EN	(0x10)
151#define SD_SQUARE_PIXEL_DI	(0xEF)
152#define SD_PIXEL_DATA_VALID	(0x40)
153#define SD_ACTIVE_EDGE_EN	(0x80)
154#define SD_ACTIVE_EDGE_DI	(0x7F)
155
156/* Bit masks for HD Mode Register 6 */
157#define HD_PRPB_SYNC_EN		(0x04)
158#define HD_PRPB_SYNC_DI		(0xFB)
159#define HD_DAC_SWAP_EN		(0x08)
160#define HD_DAC_SWAP_DI		(0xF7)
161#define HD_GAMMA_CURVE_A	(0xEF)
162#define HD_GAMMA_CURVE_B	(0x10)
163#define HD_GAMMA_EN		(0x20)
164#define HD_GAMMA_DI		(0xDF)
165#define HD_ADPT_FLTR_MODEA	(0xBF)
166#define HD_ADPT_FLTR_MODEB	(0x40)
167#define HD_ADPT_FLTR_EN		(0x80)
168#define HD_ADPT_FLTR_DI		(0x7F)
169
170#define ADV7393_BRIGHTNESS_MAX	(63)
171#define ADV7393_BRIGHTNESS_MIN	(-64)
172#define ADV7393_BRIGHTNESS_DEF	(0)
173#define ADV7393_HUE_MAX		(127)
174#define ADV7393_HUE_MIN		(-128)
175#define ADV7393_HUE_DEF		(0)
176#define ADV7393_GAIN_MAX	(64)
177#define ADV7393_GAIN_MIN	(-64)
178#define ADV7393_GAIN_DEF	(0)
179
180#endif
181