1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 NXP TDA10048HN DVB OFDM demodulator driver 4 5 Copyright (C) 2009 Steven Toth <stoth@kernellabs.com> 6 7 8*/ 9 10#include <linux/kernel.h> 11#include <linux/init.h> 12#include <linux/module.h> 13#include <linux/string.h> 14#include <linux/slab.h> 15#include <linux/delay.h> 16#include <linux/math64.h> 17#include <asm/div64.h> 18#include <media/dvb_frontend.h> 19#include <linux/int_log.h> 20#include "tda10048.h" 21 22#define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw" 23#define TDA10048_DEFAULT_FIRMWARE_SIZE 24878 24 25/* Register name definitions */ 26#define TDA10048_IDENTITY 0x00 27#define TDA10048_VERSION 0x01 28#define TDA10048_DSP_CODE_CPT 0x0C 29#define TDA10048_DSP_CODE_IN 0x0E 30#define TDA10048_IN_CONF1 0x10 31#define TDA10048_IN_CONF2 0x11 32#define TDA10048_IN_CONF3 0x12 33#define TDA10048_OUT_CONF1 0x14 34#define TDA10048_OUT_CONF2 0x15 35#define TDA10048_OUT_CONF3 0x16 36#define TDA10048_AUTO 0x18 37#define TDA10048_SYNC_STATUS 0x1A 38#define TDA10048_CONF_C4_1 0x1E 39#define TDA10048_CONF_C4_2 0x1F 40#define TDA10048_CODE_IN_RAM 0x20 41#define TDA10048_CHANNEL_INFO1_R 0x22 42#define TDA10048_CHANNEL_INFO2_R 0x23 43#define TDA10048_CHANNEL_INFO1 0x24 44#define TDA10048_CHANNEL_INFO2 0x25 45#define TDA10048_TIME_ERROR_R 0x26 46#define TDA10048_TIME_ERROR 0x27 47#define TDA10048_FREQ_ERROR_LSB_R 0x28 48#define TDA10048_FREQ_ERROR_MSB_R 0x29 49#define TDA10048_FREQ_ERROR_LSB 0x2A 50#define TDA10048_FREQ_ERROR_MSB 0x2B 51#define TDA10048_IT_SEL 0x30 52#define TDA10048_IT_STAT 0x32 53#define TDA10048_DSP_AD_LSB 0x3C 54#define TDA10048_DSP_AD_MSB 0x3D 55#define TDA10048_DSP_REG_LSB 0x3E 56#define TDA10048_DSP_REG_MSB 0x3F 57#define TDA10048_CONF_TRISTATE1 0x44 58#define TDA10048_CONF_TRISTATE2 0x45 59#define TDA10048_CONF_POLARITY 0x46 60#define TDA10048_GPIO_SP_DS0 0x48 61#define TDA10048_GPIO_SP_DS1 0x49 62#define TDA10048_GPIO_SP_DS2 0x4A 63#define TDA10048_GPIO_SP_DS3 0x4B 64#define TDA10048_GPIO_OUT_SEL 0x4C 65#define TDA10048_GPIO_SELECT 0x4D 66#define TDA10048_IC_MODE 0x4E 67#define TDA10048_CONF_XO 0x50 68#define TDA10048_CONF_PLL1 0x51 69#define TDA10048_CONF_PLL2 0x52 70#define TDA10048_CONF_PLL3 0x53 71#define TDA10048_CONF_ADC 0x54 72#define TDA10048_CONF_ADC_2 0x55 73#define TDA10048_CONF_C1_1 0x60 74#define TDA10048_CONF_C1_3 0x62 75#define TDA10048_AGC_CONF 0x70 76#define TDA10048_AGC_THRESHOLD_LSB 0x72 77#define TDA10048_AGC_THRESHOLD_MSB 0x73 78#define TDA10048_AGC_RENORM 0x74 79#define TDA10048_AGC_GAINS 0x76 80#define TDA10048_AGC_TUN_MIN 0x78 81#define TDA10048_AGC_TUN_MAX 0x79 82#define TDA10048_AGC_IF_MIN 0x7A 83#define TDA10048_AGC_IF_MAX 0x7B 84#define TDA10048_AGC_TUN_LEVEL 0x7E 85#define TDA10048_AGC_IF_LEVEL 0x7F 86#define TDA10048_DIG_AGC_LEVEL 0x81 87#define TDA10048_FREQ_PHY2_LSB 0x86 88#define TDA10048_FREQ_PHY2_MSB 0x87 89#define TDA10048_TIME_INVWREF_LSB 0x88 90#define TDA10048_TIME_INVWREF_MSB 0x89 91#define TDA10048_TIME_WREF_LSB 0x8A 92#define TDA10048_TIME_WREF_MID1 0x8B 93#define TDA10048_TIME_WREF_MID2 0x8C 94#define TDA10048_TIME_WREF_MSB 0x8D 95#define TDA10048_NP_OUT 0xA2 96#define TDA10048_CELL_ID_LSB 0xA4 97#define TDA10048_CELL_ID_MSB 0xA5 98#define TDA10048_EXTTPS_ODD 0xAA 99#define TDA10048_EXTTPS_EVEN 0xAB 100#define TDA10048_TPS_LENGTH 0xAC 101#define TDA10048_FREE_REG_1 0xB2 102#define TDA10048_FREE_REG_2 0xB3 103#define TDA10048_CONF_C3_1 0xC0 104#define TDA10048_CVBER_CTRL 0xC2 105#define TDA10048_CBER_NMAX_LSB 0xC4 106#define TDA10048_CBER_NMAX_MSB 0xC5 107#define TDA10048_CBER_LSB 0xC6 108#define TDA10048_CBER_MSB 0xC7 109#define TDA10048_VBER_LSB 0xC8 110#define TDA10048_VBER_MID 0xC9 111#define TDA10048_VBER_MSB 0xCA 112#define TDA10048_CVBER_LUT 0xCC 113#define TDA10048_UNCOR_CTRL 0xCD 114#define TDA10048_UNCOR_CPT_LSB 0xCE 115#define TDA10048_UNCOR_CPT_MSB 0xCF 116#define TDA10048_SOFT_IT_C3 0xD6 117#define TDA10048_CONF_TS2 0xE0 118#define TDA10048_CONF_TS1 0xE1 119 120static unsigned int debug; 121 122#define dprintk(level, fmt, arg...)\ 123 do { if (debug >= level)\ 124 printk(KERN_DEBUG "tda10048: " fmt, ## arg);\ 125 } while (0) 126 127struct tda10048_state { 128 129 struct i2c_adapter *i2c; 130 131 /* We'll cache and update the attach config settings */ 132 struct tda10048_config config; 133 struct dvb_frontend frontend; 134 135 int fwloaded; 136 137 u32 freq_if_hz; 138 u32 xtal_hz; 139 u32 pll_mfactor; 140 u32 pll_nfactor; 141 u32 pll_pfactor; 142 u32 sample_freq; 143 144 u32 bandwidth; 145}; 146 147static struct init_tab { 148 u8 reg; 149 u16 data; 150} init_tab[] = { 151 { TDA10048_CONF_PLL1, 0x08 }, 152 { TDA10048_CONF_ADC_2, 0x00 }, 153 { TDA10048_CONF_C4_1, 0x00 }, 154 { TDA10048_CONF_PLL1, 0x0f }, 155 { TDA10048_CONF_PLL2, 0x0a }, 156 { TDA10048_CONF_PLL3, 0x43 }, 157 { TDA10048_FREQ_PHY2_LSB, 0x02 }, 158 { TDA10048_FREQ_PHY2_MSB, 0x0a }, 159 { TDA10048_TIME_WREF_LSB, 0xbd }, 160 { TDA10048_TIME_WREF_MID1, 0xe4 }, 161 { TDA10048_TIME_WREF_MID2, 0xa8 }, 162 { TDA10048_TIME_WREF_MSB, 0x02 }, 163 { TDA10048_TIME_INVWREF_LSB, 0x04 }, 164 { TDA10048_TIME_INVWREF_MSB, 0x06 }, 165 { TDA10048_CONF_C4_1, 0x00 }, 166 { TDA10048_CONF_C1_1, 0xa8 }, 167 { TDA10048_AGC_CONF, 0x16 }, 168 { TDA10048_CONF_C1_3, 0x0b }, 169 { TDA10048_AGC_TUN_MIN, 0x00 }, 170 { TDA10048_AGC_TUN_MAX, 0xff }, 171 { TDA10048_AGC_IF_MIN, 0x00 }, 172 { TDA10048_AGC_IF_MAX, 0xff }, 173 { TDA10048_AGC_THRESHOLD_MSB, 0x00 }, 174 { TDA10048_AGC_THRESHOLD_LSB, 0x70 }, 175 { TDA10048_CVBER_CTRL, 0x38 }, 176 { TDA10048_AGC_GAINS, 0x12 }, 177 { TDA10048_CONF_XO, 0x00 }, 178 { TDA10048_CONF_TS1, 0x07 }, 179 { TDA10048_IC_MODE, 0x00 }, 180 { TDA10048_CONF_TS2, 0xc0 }, 181 { TDA10048_CONF_TRISTATE1, 0x21 }, 182 { TDA10048_CONF_TRISTATE2, 0x00 }, 183 { TDA10048_CONF_POLARITY, 0x00 }, 184 { TDA10048_CONF_C4_2, 0x04 }, 185 { TDA10048_CONF_ADC, 0x60 }, 186 { TDA10048_CONF_ADC_2, 0x10 }, 187 { TDA10048_CONF_ADC, 0x60 }, 188 { TDA10048_CONF_ADC_2, 0x00 }, 189 { TDA10048_CONF_C1_1, 0xa8 }, 190 { TDA10048_UNCOR_CTRL, 0x00 }, 191 { TDA10048_CONF_C4_2, 0x04 }, 192}; 193 194static struct pll_tab { 195 u32 clk_freq_khz; 196 u32 if_freq_khz; 197} pll_tab[] = { 198 { TDA10048_CLK_4000, TDA10048_IF_36130 }, 199 { TDA10048_CLK_16000, TDA10048_IF_3300 }, 200 { TDA10048_CLK_16000, TDA10048_IF_3500 }, 201 { TDA10048_CLK_16000, TDA10048_IF_3800 }, 202 { TDA10048_CLK_16000, TDA10048_IF_4000 }, 203 { TDA10048_CLK_16000, TDA10048_IF_4300 }, 204 { TDA10048_CLK_16000, TDA10048_IF_4500 }, 205 { TDA10048_CLK_16000, TDA10048_IF_5000 }, 206 { TDA10048_CLK_16000, TDA10048_IF_36130 }, 207}; 208 209static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data) 210{ 211 struct tda10048_config *config = &state->config; 212 int ret; 213 u8 buf[] = { reg, data }; 214 struct i2c_msg msg = { 215 .addr = config->demod_address, 216 .flags = 0, .buf = buf, .len = 2 }; 217 218 dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data); 219 220 ret = i2c_transfer(state->i2c, &msg, 1); 221 222 if (ret != 1) 223 printk("%s: writereg error (ret == %i)\n", __func__, ret); 224 225 return (ret != 1) ? -1 : 0; 226} 227 228static u8 tda10048_readreg(struct tda10048_state *state, u8 reg) 229{ 230 struct tda10048_config *config = &state->config; 231 int ret; 232 u8 b0[] = { reg }; 233 u8 b1[] = { 0 }; 234 struct i2c_msg msg[] = { 235 { .addr = config->demod_address, 236 .flags = 0, .buf = b0, .len = 1 }, 237 { .addr = config->demod_address, 238 .flags = I2C_M_RD, .buf = b1, .len = 1 } }; 239 240 dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg); 241 242 ret = i2c_transfer(state->i2c, msg, 2); 243 244 if (ret != 2) 245 printk(KERN_ERR "%s: readreg error (ret == %i)\n", 246 __func__, ret); 247 248 return b1[0]; 249} 250 251static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg, 252 const u8 *data, u16 len) 253{ 254 struct tda10048_config *config = &state->config; 255 int ret = -EREMOTEIO; 256 struct i2c_msg msg; 257 u8 *buf; 258 259 dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len); 260 261 buf = kmalloc(len + 1, GFP_KERNEL); 262 if (buf == NULL) { 263 ret = -ENOMEM; 264 goto error; 265 } 266 267 *buf = reg; 268 memcpy(buf + 1, data, len); 269 270 msg.addr = config->demod_address; 271 msg.flags = 0; 272 msg.buf = buf; 273 msg.len = len + 1; 274 275 dprintk(2, "%s(): write len = %d\n", 276 __func__, msg.len); 277 278 ret = i2c_transfer(state->i2c, &msg, 1); 279 if (ret != 1) { 280 printk(KERN_ERR "%s(): writereg error err %i\n", 281 __func__, ret); 282 ret = -EREMOTEIO; 283 } 284 285error: 286 kfree(buf); 287 288 return ret; 289} 290 291static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz, 292 u32 if_hz) 293{ 294 struct tda10048_state *state = fe->demodulator_priv; 295 u64 t; 296 297 dprintk(1, "%s()\n", __func__); 298 299 if (sample_freq_hz == 0) 300 return -EINVAL; 301 302 if (if_hz < (sample_freq_hz / 2)) { 303 /* PHY2 = (if2/fs) * 2^15 */ 304 t = if_hz; 305 t *= 10; 306 t *= 32768; 307 do_div(t, sample_freq_hz); 308 t += 5; 309 do_div(t, 10); 310 } else { 311 /* PHY2 = ((IF1-fs)/fs) * 2^15 */ 312 t = sample_freq_hz - if_hz; 313 t *= 10; 314 t *= 32768; 315 do_div(t, sample_freq_hz); 316 t += 5; 317 do_div(t, 10); 318 t = ~t + 1; 319 } 320 321 tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t); 322 tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8)); 323 324 return 0; 325} 326 327static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz, 328 u32 bw) 329{ 330 struct tda10048_state *state = fe->demodulator_priv; 331 u64 t, z; 332 333 dprintk(1, "%s()\n", __func__); 334 335 if (sample_freq_hz == 0) 336 return -EINVAL; 337 338 /* WREF = (B / (7 * fs)) * 2^31 */ 339 t = bw * 10; 340 /* avoid warning: this decimal constant is unsigned only in ISO C90 */ 341 /* t *= 2147483648 on 32bit platforms */ 342 t *= (2048 * 1024); 343 t *= 1024; 344 z = 7 * sample_freq_hz; 345 do_div(t, z); 346 t += 5; 347 do_div(t, 10); 348 349 tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t); 350 tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8)); 351 tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16)); 352 tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24)); 353 354 return 0; 355} 356 357static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz, 358 u32 bw) 359{ 360 struct tda10048_state *state = fe->demodulator_priv; 361 u64 t; 362 363 dprintk(1, "%s()\n", __func__); 364 365 if (sample_freq_hz == 0) 366 return -EINVAL; 367 368 /* INVWREF = ((7 * fs) / B) * 2^5 */ 369 t = sample_freq_hz; 370 t *= 7; 371 t *= 32; 372 t *= 10; 373 do_div(t, bw); 374 t += 5; 375 do_div(t, 10); 376 377 tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t); 378 tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8)); 379 380 return 0; 381} 382 383static int tda10048_set_bandwidth(struct dvb_frontend *fe, 384 u32 bw) 385{ 386 struct tda10048_state *state = fe->demodulator_priv; 387 dprintk(1, "%s(bw=%d)\n", __func__, bw); 388 389 /* Bandwidth setting may need to be adjusted */ 390 switch (bw) { 391 case 6000000: 392 case 7000000: 393 case 8000000: 394 tda10048_set_wref(fe, state->sample_freq, bw); 395 tda10048_set_invwref(fe, state->sample_freq, bw); 396 break; 397 default: 398 printk(KERN_ERR "%s() invalid bandwidth\n", __func__); 399 return -EINVAL; 400 } 401 402 state->bandwidth = bw; 403 404 return 0; 405} 406 407static int tda10048_set_if(struct dvb_frontend *fe, u32 bw) 408{ 409 struct tda10048_state *state = fe->demodulator_priv; 410 struct tda10048_config *config = &state->config; 411 int i; 412 u32 if_freq_khz; 413 u64 sample_freq; 414 415 dprintk(1, "%s(bw = %d)\n", __func__, bw); 416 417 /* based on target bandwidth and clk we calculate pll factors */ 418 switch (bw) { 419 case 6000000: 420 if_freq_khz = config->dtv6_if_freq_khz; 421 break; 422 case 7000000: 423 if_freq_khz = config->dtv7_if_freq_khz; 424 break; 425 case 8000000: 426 if_freq_khz = config->dtv8_if_freq_khz; 427 break; 428 default: 429 printk(KERN_ERR "%s() no default\n", __func__); 430 return -EINVAL; 431 } 432 433 for (i = 0; i < ARRAY_SIZE(pll_tab); i++) { 434 if ((pll_tab[i].clk_freq_khz == config->clk_freq_khz) && 435 (pll_tab[i].if_freq_khz == if_freq_khz)) { 436 437 state->freq_if_hz = pll_tab[i].if_freq_khz * 1000; 438 state->xtal_hz = pll_tab[i].clk_freq_khz * 1000; 439 break; 440 } 441 } 442 if (i == ARRAY_SIZE(pll_tab)) { 443 printk(KERN_ERR "%s() Incorrect attach settings\n", 444 __func__); 445 return -EINVAL; 446 } 447 448 dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz); 449 dprintk(1, "- xtal_hz = %d\n", state->xtal_hz); 450 dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor); 451 dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor); 452 dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor); 453 454 /* Calculate the sample frequency */ 455 sample_freq = state->xtal_hz; 456 sample_freq *= state->pll_mfactor + 45; 457 do_div(sample_freq, state->pll_nfactor + 1); 458 do_div(sample_freq, state->pll_pfactor + 4); 459 state->sample_freq = sample_freq; 460 dprintk(1, "- sample_freq = %d\n", state->sample_freq); 461 462 /* Update the I/F */ 463 tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz); 464 465 return 0; 466} 467 468static int tda10048_firmware_upload(struct dvb_frontend *fe) 469{ 470 struct tda10048_state *state = fe->demodulator_priv; 471 struct tda10048_config *config = &state->config; 472 const struct firmware *fw; 473 int ret; 474 int pos = 0; 475 int cnt; 476 u8 wlen = config->fwbulkwritelen; 477 478 if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50)) 479 wlen = TDA10048_BULKWRITE_200; 480 481 /* request the firmware, this will block and timeout */ 482 printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n", 483 __func__, 484 TDA10048_DEFAULT_FIRMWARE); 485 486 ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE, 487 state->i2c->dev.parent); 488 if (ret) { 489 printk(KERN_ERR "%s: Upload failed. (file not found?)\n", 490 __func__); 491 return -EIO; 492 } else { 493 printk(KERN_INFO "%s: firmware read %zu bytes.\n", 494 __func__, 495 fw->size); 496 ret = 0; 497 } 498 499 if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) { 500 printk(KERN_ERR "%s: firmware incorrect size\n", __func__); 501 ret = -EIO; 502 } else { 503 printk(KERN_INFO "%s: firmware uploading\n", __func__); 504 505 /* Soft reset */ 506 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 507 tda10048_readreg(state, TDA10048_CONF_TRISTATE1) 508 & 0xfe); 509 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 510 tda10048_readreg(state, TDA10048_CONF_TRISTATE1) 511 | 0x01); 512 513 /* Put the demod into host download mode */ 514 tda10048_writereg(state, TDA10048_CONF_C4_1, 515 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9); 516 517 /* Boot the DSP */ 518 tda10048_writereg(state, TDA10048_CONF_C4_1, 519 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08); 520 521 /* Prepare for download */ 522 tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0); 523 524 /* Download the firmware payload */ 525 while (pos < fw->size) { 526 527 if ((fw->size - pos) > wlen) 528 cnt = wlen; 529 else 530 cnt = fw->size - pos; 531 532 tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN, 533 &fw->data[pos], cnt); 534 535 pos += cnt; 536 } 537 538 ret = -EIO; 539 /* Wait up to 250ms for the DSP to boot */ 540 for (cnt = 0; cnt < 250 ; cnt += 10) { 541 542 msleep(10); 543 544 if (tda10048_readreg(state, TDA10048_SYNC_STATUS) 545 & 0x40) { 546 ret = 0; 547 break; 548 } 549 } 550 } 551 552 release_firmware(fw); 553 554 if (ret == 0) { 555 printk(KERN_INFO "%s: firmware uploaded\n", __func__); 556 state->fwloaded = 1; 557 } else 558 printk(KERN_ERR "%s: firmware upload failed\n", __func__); 559 560 return ret; 561} 562 563static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion) 564{ 565 struct tda10048_state *state = fe->demodulator_priv; 566 567 dprintk(1, "%s(%d)\n", __func__, inversion); 568 569 if (inversion == TDA10048_INVERSION_ON) 570 tda10048_writereg(state, TDA10048_CONF_C1_1, 571 tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20); 572 else 573 tda10048_writereg(state, TDA10048_CONF_C1_1, 574 tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf); 575 576 return 0; 577} 578 579/* Retrieve the demod settings */ 580static int tda10048_get_tps(struct tda10048_state *state, 581 struct dtv_frontend_properties *p) 582{ 583 u8 val; 584 585 /* Make sure the TPS regs are valid */ 586 if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01)) 587 return -EAGAIN; 588 589 val = tda10048_readreg(state, TDA10048_OUT_CONF2); 590 switch ((val & 0x60) >> 5) { 591 case 0: 592 p->modulation = QPSK; 593 break; 594 case 1: 595 p->modulation = QAM_16; 596 break; 597 case 2: 598 p->modulation = QAM_64; 599 break; 600 } 601 switch ((val & 0x18) >> 3) { 602 case 0: 603 p->hierarchy = HIERARCHY_NONE; 604 break; 605 case 1: 606 p->hierarchy = HIERARCHY_1; 607 break; 608 case 2: 609 p->hierarchy = HIERARCHY_2; 610 break; 611 case 3: 612 p->hierarchy = HIERARCHY_4; 613 break; 614 } 615 switch (val & 0x07) { 616 case 0: 617 p->code_rate_HP = FEC_1_2; 618 break; 619 case 1: 620 p->code_rate_HP = FEC_2_3; 621 break; 622 case 2: 623 p->code_rate_HP = FEC_3_4; 624 break; 625 case 3: 626 p->code_rate_HP = FEC_5_6; 627 break; 628 case 4: 629 p->code_rate_HP = FEC_7_8; 630 break; 631 } 632 633 val = tda10048_readreg(state, TDA10048_OUT_CONF3); 634 switch (val & 0x07) { 635 case 0: 636 p->code_rate_LP = FEC_1_2; 637 break; 638 case 1: 639 p->code_rate_LP = FEC_2_3; 640 break; 641 case 2: 642 p->code_rate_LP = FEC_3_4; 643 break; 644 case 3: 645 p->code_rate_LP = FEC_5_6; 646 break; 647 case 4: 648 p->code_rate_LP = FEC_7_8; 649 break; 650 } 651 652 val = tda10048_readreg(state, TDA10048_OUT_CONF1); 653 switch ((val & 0x0c) >> 2) { 654 case 0: 655 p->guard_interval = GUARD_INTERVAL_1_32; 656 break; 657 case 1: 658 p->guard_interval = GUARD_INTERVAL_1_16; 659 break; 660 case 2: 661 p->guard_interval = GUARD_INTERVAL_1_8; 662 break; 663 case 3: 664 p->guard_interval = GUARD_INTERVAL_1_4; 665 break; 666 } 667 switch (val & 0x03) { 668 case 0: 669 p->transmission_mode = TRANSMISSION_MODE_2K; 670 break; 671 case 1: 672 p->transmission_mode = TRANSMISSION_MODE_8K; 673 break; 674 } 675 676 return 0; 677} 678 679static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 680{ 681 struct tda10048_state *state = fe->demodulator_priv; 682 struct tda10048_config *config = &state->config; 683 dprintk(1, "%s(%d)\n", __func__, enable); 684 685 if (config->disable_gate_access) 686 return 0; 687 688 if (enable) 689 return tda10048_writereg(state, TDA10048_CONF_C4_1, 690 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02); 691 else 692 return tda10048_writereg(state, TDA10048_CONF_C4_1, 693 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd); 694} 695 696static int tda10048_output_mode(struct dvb_frontend *fe, int serial) 697{ 698 struct tda10048_state *state = fe->demodulator_priv; 699 dprintk(1, "%s(%d)\n", __func__, serial); 700 701 /* Ensure pins are out of tri-state */ 702 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21); 703 tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00); 704 705 if (serial) { 706 tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20); 707 tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0); 708 } else { 709 tda10048_writereg(state, TDA10048_IC_MODE, 0x00); 710 tda10048_writereg(state, TDA10048_CONF_TS2, 0x01); 711 } 712 713 return 0; 714} 715 716/* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 717/* TODO: Support manual tuning with specific params */ 718static int tda10048_set_frontend(struct dvb_frontend *fe) 719{ 720 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 721 struct tda10048_state *state = fe->demodulator_priv; 722 723 dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency); 724 725 /* Update the I/F pll's if the bandwidth changes */ 726 if (p->bandwidth_hz != state->bandwidth) { 727 tda10048_set_if(fe, p->bandwidth_hz); 728 tda10048_set_bandwidth(fe, p->bandwidth_hz); 729 } 730 731 if (fe->ops.tuner_ops.set_params) { 732 733 if (fe->ops.i2c_gate_ctrl) 734 fe->ops.i2c_gate_ctrl(fe, 1); 735 736 fe->ops.tuner_ops.set_params(fe); 737 738 if (fe->ops.i2c_gate_ctrl) 739 fe->ops.i2c_gate_ctrl(fe, 0); 740 } 741 742 /* Enable demod TPS auto detection and begin acquisition */ 743 tda10048_writereg(state, TDA10048_AUTO, 0x57); 744 /* trigger cber and vber acquisition */ 745 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x3B); 746 747 return 0; 748} 749 750/* Establish sane defaults and load firmware. */ 751static int tda10048_init(struct dvb_frontend *fe) 752{ 753 struct tda10048_state *state = fe->demodulator_priv; 754 struct tda10048_config *config = &state->config; 755 int ret = 0, i; 756 757 dprintk(1, "%s()\n", __func__); 758 759 /* PLL */ 760 init_tab[4].data = (u8)(state->pll_mfactor); 761 init_tab[5].data = (u8)(state->pll_nfactor) | 0x40; 762 763 /* Apply register defaults */ 764 for (i = 0; i < ARRAY_SIZE(init_tab); i++) 765 tda10048_writereg(state, init_tab[i].reg, init_tab[i].data); 766 767 if (state->fwloaded == 0) 768 ret = tda10048_firmware_upload(fe); 769 770 /* Set either serial or parallel */ 771 tda10048_output_mode(fe, config->output_mode); 772 773 /* Set inversion */ 774 tda10048_set_inversion(fe, config->inversion); 775 776 /* Establish default RF values */ 777 tda10048_set_if(fe, 8000000); 778 tda10048_set_bandwidth(fe, 8000000); 779 780 /* Ensure we leave the gate closed */ 781 tda10048_i2c_gate_ctrl(fe, 0); 782 783 return ret; 784} 785 786static int tda10048_read_status(struct dvb_frontend *fe, enum fe_status *status) 787{ 788 struct tda10048_state *state = fe->demodulator_priv; 789 u8 reg; 790 791 *status = 0; 792 793 reg = tda10048_readreg(state, TDA10048_SYNC_STATUS); 794 795 dprintk(1, "%s() status =0x%02x\n", __func__, reg); 796 797 if (reg & 0x02) 798 *status |= FE_HAS_CARRIER; 799 800 if (reg & 0x04) 801 *status |= FE_HAS_SIGNAL; 802 803 if (reg & 0x08) { 804 *status |= FE_HAS_LOCK; 805 *status |= FE_HAS_VITERBI; 806 *status |= FE_HAS_SYNC; 807 } 808 809 return 0; 810} 811 812static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber) 813{ 814 struct tda10048_state *state = fe->demodulator_priv; 815 static u32 cber_current; 816 u32 cber_nmax; 817 u64 cber_tmp; 818 819 dprintk(1, "%s()\n", __func__); 820 821 /* update cber on interrupt */ 822 if (tda10048_readreg(state, TDA10048_SOFT_IT_C3) & 0x01) { 823 cber_tmp = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 | 824 tda10048_readreg(state, TDA10048_CBER_LSB); 825 cber_nmax = tda10048_readreg(state, TDA10048_CBER_NMAX_MSB) << 8 | 826 tda10048_readreg(state, TDA10048_CBER_NMAX_LSB); 827 cber_tmp *= 100000000; 828 cber_tmp *= 2; 829 cber_tmp = div_u64(cber_tmp, (cber_nmax * 32) + 1); 830 cber_current = (u32)cber_tmp; 831 /* retrigger cber acquisition */ 832 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x39); 833 } 834 /* actual cber is (*ber)/1e8 */ 835 *ber = cber_current; 836 837 return 0; 838} 839 840static int tda10048_read_signal_strength(struct dvb_frontend *fe, 841 u16 *signal_strength) 842{ 843 struct tda10048_state *state = fe->demodulator_priv; 844 u8 v; 845 846 dprintk(1, "%s()\n", __func__); 847 848 *signal_strength = 65535; 849 850 v = tda10048_readreg(state, TDA10048_NP_OUT); 851 if (v > 0) 852 *signal_strength -= (v << 8) | v; 853 854 return 0; 855} 856 857/* SNR lookup table */ 858static struct snr_tab { 859 u8 val; 860 u8 data; 861} snr_tab[] = { 862 { 0, 0 }, 863 { 1, 246 }, 864 { 2, 215 }, 865 { 3, 198 }, 866 { 4, 185 }, 867 { 5, 176 }, 868 { 6, 168 }, 869 { 7, 161 }, 870 { 8, 155 }, 871 { 9, 150 }, 872 { 10, 146 }, 873 { 11, 141 }, 874 { 12, 138 }, 875 { 13, 134 }, 876 { 14, 131 }, 877 { 15, 128 }, 878 { 16, 125 }, 879 { 17, 122 }, 880 { 18, 120 }, 881 { 19, 118 }, 882 { 20, 115 }, 883 { 21, 113 }, 884 { 22, 111 }, 885 { 23, 109 }, 886 { 24, 107 }, 887 { 25, 106 }, 888 { 26, 104 }, 889 { 27, 102 }, 890 { 28, 101 }, 891 { 29, 99 }, 892 { 30, 98 }, 893 { 31, 96 }, 894 { 32, 95 }, 895 { 33, 94 }, 896 { 34, 92 }, 897 { 35, 91 }, 898 { 36, 90 }, 899 { 37, 89 }, 900 { 38, 88 }, 901 { 39, 86 }, 902 { 40, 85 }, 903 { 41, 84 }, 904 { 42, 83 }, 905 { 43, 82 }, 906 { 44, 81 }, 907 { 45, 80 }, 908 { 46, 79 }, 909 { 47, 78 }, 910 { 48, 77 }, 911 { 49, 76 }, 912 { 50, 76 }, 913 { 51, 75 }, 914 { 52, 74 }, 915 { 53, 73 }, 916 { 54, 72 }, 917 { 56, 71 }, 918 { 57, 70 }, 919 { 58, 69 }, 920 { 60, 68 }, 921 { 61, 67 }, 922 { 63, 66 }, 923 { 64, 65 }, 924 { 66, 64 }, 925 { 67, 63 }, 926 { 68, 62 }, 927 { 69, 62 }, 928 { 70, 61 }, 929 { 72, 60 }, 930 { 74, 59 }, 931 { 75, 58 }, 932 { 77, 57 }, 933 { 79, 56 }, 934 { 81, 55 }, 935 { 83, 54 }, 936 { 85, 53 }, 937 { 87, 52 }, 938 { 89, 51 }, 939 { 91, 50 }, 940 { 93, 49 }, 941 { 95, 48 }, 942 { 97, 47 }, 943 { 100, 46 }, 944 { 102, 45 }, 945 { 104, 44 }, 946 { 107, 43 }, 947 { 109, 42 }, 948 { 112, 41 }, 949 { 114, 40 }, 950 { 117, 39 }, 951 { 120, 38 }, 952 { 123, 37 }, 953 { 125, 36 }, 954 { 128, 35 }, 955 { 131, 34 }, 956 { 134, 33 }, 957 { 138, 32 }, 958 { 141, 31 }, 959 { 144, 30 }, 960 { 147, 29 }, 961 { 151, 28 }, 962 { 154, 27 }, 963 { 158, 26 }, 964 { 162, 25 }, 965 { 165, 24 }, 966 { 169, 23 }, 967 { 173, 22 }, 968 { 177, 21 }, 969 { 181, 20 }, 970 { 186, 19 }, 971 { 190, 18 }, 972 { 194, 17 }, 973 { 199, 16 }, 974 { 204, 15 }, 975 { 208, 14 }, 976 { 213, 13 }, 977 { 218, 12 }, 978 { 223, 11 }, 979 { 229, 10 }, 980 { 234, 9 }, 981 { 239, 8 }, 982 { 245, 7 }, 983 { 251, 6 }, 984 { 255, 5 }, 985}; 986 987static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr) 988{ 989 struct tda10048_state *state = fe->demodulator_priv; 990 u8 v; 991 int i, ret = -EINVAL; 992 993 dprintk(1, "%s()\n", __func__); 994 995 v = tda10048_readreg(state, TDA10048_NP_OUT); 996 for (i = 0; i < ARRAY_SIZE(snr_tab); i++) { 997 if (v <= snr_tab[i].val) { 998 *snr = snr_tab[i].data; 999 ret = 0; 1000 break; 1001 } 1002 } 1003 1004 return ret; 1005} 1006 1007static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1008{ 1009 struct tda10048_state *state = fe->demodulator_priv; 1010 1011 dprintk(1, "%s()\n", __func__); 1012 1013 *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 | 1014 tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB); 1015 /* clear the uncorrected TS packets counter when saturated */ 1016 if (*ucblocks == 0xFFFF) 1017 tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80); 1018 1019 return 0; 1020} 1021 1022static int tda10048_get_frontend(struct dvb_frontend *fe, 1023 struct dtv_frontend_properties *p) 1024{ 1025 struct tda10048_state *state = fe->demodulator_priv; 1026 1027 dprintk(1, "%s()\n", __func__); 1028 1029 p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1) 1030 & 0x20 ? INVERSION_ON : INVERSION_OFF; 1031 1032 return tda10048_get_tps(state, p); 1033} 1034 1035static int tda10048_get_tune_settings(struct dvb_frontend *fe, 1036 struct dvb_frontend_tune_settings *tune) 1037{ 1038 tune->min_delay_ms = 1000; 1039 return 0; 1040} 1041 1042static void tda10048_release(struct dvb_frontend *fe) 1043{ 1044 struct tda10048_state *state = fe->demodulator_priv; 1045 dprintk(1, "%s()\n", __func__); 1046 kfree(state); 1047} 1048 1049static void tda10048_establish_defaults(struct dvb_frontend *fe) 1050{ 1051 struct tda10048_state *state = fe->demodulator_priv; 1052 struct tda10048_config *config = &state->config; 1053 1054 /* Validate/default the config */ 1055 if (config->dtv6_if_freq_khz == 0) { 1056 config->dtv6_if_freq_khz = TDA10048_IF_4300; 1057 printk(KERN_WARNING "%s() tda10048_config.dtv6_if_freq_khz is not set (defaulting to %d)\n", 1058 __func__, 1059 config->dtv6_if_freq_khz); 1060 } 1061 1062 if (config->dtv7_if_freq_khz == 0) { 1063 config->dtv7_if_freq_khz = TDA10048_IF_4300; 1064 printk(KERN_WARNING "%s() tda10048_config.dtv7_if_freq_khz is not set (defaulting to %d)\n", 1065 __func__, 1066 config->dtv7_if_freq_khz); 1067 } 1068 1069 if (config->dtv8_if_freq_khz == 0) { 1070 config->dtv8_if_freq_khz = TDA10048_IF_4300; 1071 printk(KERN_WARNING "%s() tda10048_config.dtv8_if_freq_khz is not set (defaulting to %d)\n", 1072 __func__, 1073 config->dtv8_if_freq_khz); 1074 } 1075 1076 if (config->clk_freq_khz == 0) { 1077 config->clk_freq_khz = TDA10048_CLK_16000; 1078 printk(KERN_WARNING "%s() tda10048_config.clk_freq_khz is not set (defaulting to %d)\n", 1079 __func__, 1080 config->clk_freq_khz); 1081 } 1082} 1083 1084static const struct dvb_frontend_ops tda10048_ops; 1085 1086struct dvb_frontend *tda10048_attach(const struct tda10048_config *config, 1087 struct i2c_adapter *i2c) 1088{ 1089 struct tda10048_state *state = NULL; 1090 1091 dprintk(1, "%s()\n", __func__); 1092 1093 /* allocate memory for the internal state */ 1094 state = kzalloc(sizeof(struct tda10048_state), GFP_KERNEL); 1095 if (state == NULL) 1096 goto error; 1097 1098 /* setup the state and clone the config */ 1099 memcpy(&state->config, config, sizeof(*config)); 1100 state->i2c = i2c; 1101 state->fwloaded = config->no_firmware; 1102 state->bandwidth = 8000000; 1103 1104 /* check if the demod is present */ 1105 if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048) 1106 goto error; 1107 1108 /* create dvb_frontend */ 1109 memcpy(&state->frontend.ops, &tda10048_ops, 1110 sizeof(struct dvb_frontend_ops)); 1111 state->frontend.demodulator_priv = state; 1112 1113 /* set pll */ 1114 if (config->set_pll) { 1115 state->pll_mfactor = config->pll_m; 1116 state->pll_nfactor = config->pll_n; 1117 state->pll_pfactor = config->pll_p; 1118 } else { 1119 state->pll_mfactor = 10; 1120 state->pll_nfactor = 3; 1121 state->pll_pfactor = 0; 1122 } 1123 1124 /* Establish any defaults the user didn't pass */ 1125 tda10048_establish_defaults(&state->frontend); 1126 1127 /* Set the xtal and freq defaults */ 1128 if (tda10048_set_if(&state->frontend, 8000000) != 0) 1129 goto error; 1130 1131 /* Default bandwidth */ 1132 if (tda10048_set_bandwidth(&state->frontend, 8000000) != 0) 1133 goto error; 1134 1135 /* Leave the gate closed */ 1136 tda10048_i2c_gate_ctrl(&state->frontend, 0); 1137 1138 return &state->frontend; 1139 1140error: 1141 kfree(state); 1142 return NULL; 1143} 1144EXPORT_SYMBOL_GPL(tda10048_attach); 1145 1146static const struct dvb_frontend_ops tda10048_ops = { 1147 .delsys = { SYS_DVBT }, 1148 .info = { 1149 .name = "NXP TDA10048HN DVB-T", 1150 .frequency_min_hz = 177 * MHz, 1151 .frequency_max_hz = 858 * MHz, 1152 .frequency_stepsize_hz = 166666, 1153 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1154 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1155 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 1156 FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | 1157 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER 1158 }, 1159 1160 .release = tda10048_release, 1161 .init = tda10048_init, 1162 .i2c_gate_ctrl = tda10048_i2c_gate_ctrl, 1163 .set_frontend = tda10048_set_frontend, 1164 .get_frontend = tda10048_get_frontend, 1165 .get_tune_settings = tda10048_get_tune_settings, 1166 .read_status = tda10048_read_status, 1167 .read_ber = tda10048_read_ber, 1168 .read_signal_strength = tda10048_read_signal_strength, 1169 .read_snr = tda10048_read_snr, 1170 .read_ucblocks = tda10048_read_ucblocks, 1171}; 1172 1173module_param(debug, int, 0644); 1174MODULE_PARM_DESC(debug, "Enable verbose debug messages"); 1175 1176MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver"); 1177MODULE_AUTHOR("Steven Toth"); 1178MODULE_LICENSE("GPL"); 1179