1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Auvitek AU8522 QAM/8VSB demodulator driver and video decoder 4 * 5 * Copyright (C) 2009 Devin Heitmueller <dheitmueller@linuxtv.org> 6 * Copyright (C) 2005-2008 Auvitek International, Ltd. 7 */ 8 9/* Developer notes: 10 * 11 * Enough is implemented here for CVBS and S-Video inputs, but the actual 12 * analog demodulator code isn't implemented (not needed for xc5000 since it 13 * has its own demodulator and outputs CVBS) 14 * 15 */ 16 17#include <linux/kernel.h> 18#include <linux/slab.h> 19#include <linux/videodev2.h> 20#include <linux/i2c.h> 21#include <linux/delay.h> 22#include <media/v4l2-common.h> 23#include <media/v4l2-device.h> 24#include "au8522.h" 25#include "au8522_priv.h" 26 27MODULE_AUTHOR("Devin Heitmueller"); 28MODULE_LICENSE("GPL"); 29 30static int au8522_analog_debug; 31 32 33module_param_named(analog_debug, au8522_analog_debug, int, 0644); 34 35MODULE_PARM_DESC(analog_debug, 36 "Analog debugging messages [0=Off (default) 1=On]"); 37 38struct au8522_register_config { 39 u16 reg_name; 40 u8 reg_val[8]; 41}; 42 43 44/* Video Decoder Filter Coefficients 45 The values are as follows from left to right 46 0="ATV RF" 1="ATV RF13" 2="CVBS" 3="S-Video" 4="PAL" 5=CVBS13" 6="SVideo13" 47*/ 48static const struct au8522_register_config filter_coef[] = { 49 {AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} }, 50 {AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} }, 51 {AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} }, 52 {AU8522_FILTER_COEF_R413, {0xe6, 0x00, 0xe6, 0xe6, 0x00, 0x00, 0x00} }, 53 {AU8522_FILTER_COEF_R414, {0x40, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00} }, 54 {AU8522_FILTER_COEF_R415, {0x1b, 0x00, 0x1b, 0x1b, 0x00, 0x00, 0x00} }, 55 {AU8522_FILTER_COEF_R416, {0xc0, 0x00, 0xc0, 0x04, 0x00, 0x00, 0x00} }, 56 {AU8522_FILTER_COEF_R417, {0x04, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00} }, 57 {AU8522_FILTER_COEF_R418, {0x8c, 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x00} }, 58 {AU8522_FILTER_COEF_R419, {0xa0, 0x40, 0xa0, 0xa0, 0x40, 0x40, 0x40} }, 59 {AU8522_FILTER_COEF_R41A, {0x21, 0x09, 0x21, 0x21, 0x09, 0x09, 0x09} }, 60 {AU8522_FILTER_COEF_R41B, {0x6c, 0x38, 0x6c, 0x6c, 0x38, 0x38, 0x38} }, 61 {AU8522_FILTER_COEF_R41C, {0x03, 0xff, 0x03, 0x03, 0xff, 0xff, 0xff} }, 62 {AU8522_FILTER_COEF_R41D, {0xbf, 0xc7, 0xbf, 0xbf, 0xc7, 0xc7, 0xc7} }, 63 {AU8522_FILTER_COEF_R41E, {0xa0, 0xdf, 0xa0, 0xa0, 0xdf, 0xdf, 0xdf} }, 64 {AU8522_FILTER_COEF_R41F, {0x10, 0x06, 0x10, 0x10, 0x06, 0x06, 0x06} }, 65 {AU8522_FILTER_COEF_R420, {0xae, 0x30, 0xae, 0xae, 0x30, 0x30, 0x30} }, 66 {AU8522_FILTER_COEF_R421, {0xc4, 0x01, 0xc4, 0xc4, 0x01, 0x01, 0x01} }, 67 {AU8522_FILTER_COEF_R422, {0x54, 0xdd, 0x54, 0x54, 0xdd, 0xdd, 0xdd} }, 68 {AU8522_FILTER_COEF_R423, {0xd0, 0xaf, 0xd0, 0xd0, 0xaf, 0xaf, 0xaf} }, 69 {AU8522_FILTER_COEF_R424, {0x1c, 0xf7, 0x1c, 0x1c, 0xf7, 0xf7, 0xf7} }, 70 {AU8522_FILTER_COEF_R425, {0x76, 0xdb, 0x76, 0x76, 0xdb, 0xdb, 0xdb} }, 71 {AU8522_FILTER_COEF_R426, {0x61, 0xc0, 0x61, 0x61, 0xc0, 0xc0, 0xc0} }, 72 {AU8522_FILTER_COEF_R427, {0xd1, 0x2f, 0xd1, 0xd1, 0x2f, 0x2f, 0x2f} }, 73 {AU8522_FILTER_COEF_R428, {0x84, 0xd8, 0x84, 0x84, 0xd8, 0xd8, 0xd8} }, 74 {AU8522_FILTER_COEF_R429, {0x06, 0xfb, 0x06, 0x06, 0xfb, 0xfb, 0xfb} }, 75 {AU8522_FILTER_COEF_R42A, {0x21, 0xd5, 0x21, 0x21, 0xd5, 0xd5, 0xd5} }, 76 {AU8522_FILTER_COEF_R42B, {0x0a, 0x3e, 0x0a, 0x0a, 0x3e, 0x3e, 0x3e} }, 77 {AU8522_FILTER_COEF_R42C, {0xe6, 0x15, 0xe6, 0xe6, 0x15, 0x15, 0x15} }, 78 {AU8522_FILTER_COEF_R42D, {0x01, 0x34, 0x01, 0x01, 0x34, 0x34, 0x34} }, 79 80}; 81#define NUM_FILTER_COEF (sizeof(filter_coef)\ 82 / sizeof(struct au8522_register_config)) 83 84 85/* Registers 0x060b through 0x0652 are the LP Filter coefficients 86 The values are as follows from left to right 87 0="SIF" 1="ATVRF/ATVRF13" 88 Note: the "ATVRF/ATVRF13" mode has never been tested 89*/ 90static const struct au8522_register_config lpfilter_coef[] = { 91 {0x060b, {0x21, 0x0b} }, 92 {0x060c, {0xad, 0xad} }, 93 {0x060d, {0x70, 0xf0} }, 94 {0x060e, {0xea, 0xe9} }, 95 {0x060f, {0xdd, 0xdd} }, 96 {0x0610, {0x08, 0x64} }, 97 {0x0611, {0x60, 0x60} }, 98 {0x0612, {0xf8, 0xb2} }, 99 {0x0613, {0x01, 0x02} }, 100 {0x0614, {0xe4, 0xb4} }, 101 {0x0615, {0x19, 0x02} }, 102 {0x0616, {0xae, 0x2e} }, 103 {0x0617, {0xee, 0xc5} }, 104 {0x0618, {0x56, 0x56} }, 105 {0x0619, {0x30, 0x58} }, 106 {0x061a, {0xf9, 0xf8} }, 107 {0x061b, {0x24, 0x64} }, 108 {0x061c, {0x07, 0x07} }, 109 {0x061d, {0x30, 0x30} }, 110 {0x061e, {0xa9, 0xed} }, 111 {0x061f, {0x09, 0x0b} }, 112 {0x0620, {0x42, 0xc2} }, 113 {0x0621, {0x1d, 0x2a} }, 114 {0x0622, {0xd6, 0x56} }, 115 {0x0623, {0x95, 0x8b} }, 116 {0x0624, {0x2b, 0x2b} }, 117 {0x0625, {0x30, 0x24} }, 118 {0x0626, {0x3e, 0x3e} }, 119 {0x0627, {0x62, 0xe2} }, 120 {0x0628, {0xe9, 0xf5} }, 121 {0x0629, {0x99, 0x19} }, 122 {0x062a, {0xd4, 0x11} }, 123 {0x062b, {0x03, 0x04} }, 124 {0x062c, {0xb5, 0x85} }, 125 {0x062d, {0x1e, 0x20} }, 126 {0x062e, {0x2a, 0xea} }, 127 {0x062f, {0xd7, 0xd2} }, 128 {0x0630, {0x15, 0x15} }, 129 {0x0631, {0xa3, 0xa9} }, 130 {0x0632, {0x1f, 0x1f} }, 131 {0x0633, {0xf9, 0xd1} }, 132 {0x0634, {0xc0, 0xc3} }, 133 {0x0635, {0x4d, 0x8d} }, 134 {0x0636, {0x21, 0x31} }, 135 {0x0637, {0x83, 0x83} }, 136 {0x0638, {0x08, 0x8c} }, 137 {0x0639, {0x19, 0x19} }, 138 {0x063a, {0x45, 0xa5} }, 139 {0x063b, {0xef, 0xec} }, 140 {0x063c, {0x8a, 0x8a} }, 141 {0x063d, {0xf4, 0xf6} }, 142 {0x063e, {0x8f, 0x8f} }, 143 {0x063f, {0x44, 0x0c} }, 144 {0x0640, {0xef, 0xf0} }, 145 {0x0641, {0x66, 0x66} }, 146 {0x0642, {0xcc, 0xd2} }, 147 {0x0643, {0x41, 0x41} }, 148 {0x0644, {0x63, 0x93} }, 149 {0x0645, {0x8e, 0x8e} }, 150 {0x0646, {0xa2, 0x42} }, 151 {0x0647, {0x7b, 0x7b} }, 152 {0x0648, {0x04, 0x04} }, 153 {0x0649, {0x00, 0x00} }, 154 {0x064a, {0x40, 0x40} }, 155 {0x064b, {0x8c, 0x98} }, 156 {0x064c, {0x00, 0x00} }, 157 {0x064d, {0x63, 0xc3} }, 158 {0x064e, {0x04, 0x04} }, 159 {0x064f, {0x20, 0x20} }, 160 {0x0650, {0x00, 0x00} }, 161 {0x0651, {0x40, 0x40} }, 162 {0x0652, {0x01, 0x01} }, 163}; 164#define NUM_LPFILTER_COEF (sizeof(lpfilter_coef)\ 165 / sizeof(struct au8522_register_config)) 166 167static inline struct au8522_state *to_state(struct v4l2_subdev *sd) 168{ 169 return container_of(sd, struct au8522_state, sd); 170} 171 172static void setup_decoder_defaults(struct au8522_state *state, bool is_svideo) 173{ 174 int i; 175 int filter_coef_type; 176 177 /* Provide reasonable defaults for picture tuning values */ 178 au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07); 179 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed); 180 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79); 181 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80); 182 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80); 183 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00); 184 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00); 185 186 /* Other decoder registers */ 187 au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00); 188 189 if (is_svideo) 190 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04); 191 else 192 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00); 193 194 au8522_writereg(state, AU8522_TVDEC_PGA_REG012H, 195 AU8522_TVDEC_PGA_REG012H_CVBS); 196 au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H, 197 AU8522_TVDEC_COMB_MODE_REG015H_CVBS); 198 au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H, 199 AU8522_TVDED_DBG_MODE_REG060H_CVBS); 200 201 if (state->std == V4L2_STD_PAL_M) { 202 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H, 203 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 | 204 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 | 205 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO); 206 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H, 207 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M); 208 } else { 209 /* NTSC */ 210 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H, 211 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 | 212 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 | 213 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN); 214 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H, 215 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC); 216 } 217 au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H, 218 AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS); 219 au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H, 220 AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS); 221 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H, 222 AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS); 223 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H, 224 AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS); 225 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H, 226 AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS); 227 au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H, 228 AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS); 229 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H, 230 AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS); 231 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH, 232 AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS); 233 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH, 234 AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS); 235 if (is_svideo) { 236 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH, 237 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO); 238 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH, 239 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO); 240 } else { 241 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH, 242 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS); 243 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH, 244 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS); 245 } 246 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH, 247 AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS); 248 au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH, 249 AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS); 250 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H, 251 AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS); 252 au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS); 253 au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS); 254 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H, 255 AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS); 256 au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS); 257 au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS); 258 au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H, 259 AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS); 260 au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H, 261 AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS); 262 au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H, 263 AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS); 264 au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH, 265 AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS); 266 au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH, 267 AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS); 268 au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H, 269 AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS); 270 au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H, 271 AU8522_TOREGAAGC_REG0E5H_CVBS); 272 au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS); 273 274 /* 275 * Despite what the table says, for the HVR-950q we still need 276 * to be in CVBS mode for the S-Video input (reason unknown). 277 */ 278 /* filter_coef_type = 3; */ 279 filter_coef_type = 5; 280 281 /* Load the Video Decoder Filter Coefficients */ 282 for (i = 0; i < NUM_FILTER_COEF; i++) { 283 au8522_writereg(state, filter_coef[i].reg_name, 284 filter_coef[i].reg_val[filter_coef_type]); 285 } 286 287 /* It's not clear what these registers are for, but they are always 288 set to the same value regardless of what mode we're in */ 289 au8522_writereg(state, AU8522_REG42EH, 0x87); 290 au8522_writereg(state, AU8522_REG42FH, 0xa2); 291 au8522_writereg(state, AU8522_REG430H, 0xbf); 292 au8522_writereg(state, AU8522_REG431H, 0xcb); 293 au8522_writereg(state, AU8522_REG432H, 0xa1); 294 au8522_writereg(state, AU8522_REG433H, 0x41); 295 au8522_writereg(state, AU8522_REG434H, 0x88); 296 au8522_writereg(state, AU8522_REG435H, 0xc2); 297 au8522_writereg(state, AU8522_REG436H, 0x3c); 298} 299 300static void au8522_setup_cvbs_mode(struct au8522_state *state, u8 input_mode) 301{ 302 /* here we're going to try the pre-programmed route */ 303 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H, 304 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS); 305 306 /* PGA in automatic mode */ 307 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00); 308 309 /* Enable clamping control */ 310 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00); 311 312 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode); 313 314 setup_decoder_defaults(state, false); 315 316 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 317 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS); 318} 319 320static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state, 321 u8 input_mode) 322{ 323 /* here we're going to try the pre-programmed route */ 324 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H, 325 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS); 326 327 /* It's not clear why we have to have the PGA in automatic mode while 328 enabling clamp control, but it's what Windows does */ 329 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00); 330 331 /* Enable clamping control */ 332 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e); 333 334 /* Disable automatic PGA (since the CVBS is coming from the tuner) */ 335 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10); 336 337 /* Set input mode to CVBS on channel 4 with SIF audio input enabled */ 338 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode); 339 340 setup_decoder_defaults(state, false); 341 342 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 343 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS); 344} 345 346static void au8522_setup_svideo_mode(struct au8522_state *state, 347 u8 input_mode) 348{ 349 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H, 350 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO); 351 352 /* Set input to Y on Channe1, C on Channel 3 */ 353 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode); 354 355 /* PGA in automatic mode */ 356 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00); 357 358 /* Enable clamping control */ 359 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00); 360 361 setup_decoder_defaults(state, true); 362 363 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 364 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS); 365} 366 367/* ----------------------------------------------------------------------- */ 368 369static void disable_audio_input(struct au8522_state *state) 370{ 371 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00); 372 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00); 373 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00); 374 375 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04); 376 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02); 377 378 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 379 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO); 380} 381 382/* 0=disable, 1=SIF */ 383static void set_audio_input(struct au8522_state *state) 384{ 385 int aud_input = state->aud_input; 386 int i; 387 388 /* Note that this function needs to be used in conjunction with setting 389 the input routing via register 0x81 */ 390 391 if (aud_input == AU8522_AUDIO_NONE) { 392 disable_audio_input(state); 393 return; 394 } 395 396 if (aud_input != AU8522_AUDIO_SIF) { 397 /* The caller asked for a mode we don't currently support */ 398 printk(KERN_ERR "Unsupported audio mode requested! mode=%d\n", 399 aud_input); 400 return; 401 } 402 403 /* Load the Audio Decoder Filter Coefficients */ 404 for (i = 0; i < NUM_LPFILTER_COEF; i++) { 405 au8522_writereg(state, lpfilter_coef[i].reg_name, 406 lpfilter_coef[i].reg_val[0]); 407 } 408 409 /* Set the volume */ 410 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F); 411 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F); 412 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff); 413 414 /* Not sure what this does */ 415 au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO); 416 417 /* Setup the audio mode to stereo DBX */ 418 au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82); 419 msleep(70); 420 421 /* Start the audio processing module */ 422 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d); 423 424 /* Set the audio frequency to 48 KHz */ 425 au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03); 426 427 /* Set the I2S parameters (WS, LSB, mode, sample rate */ 428 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2); 429 430 /* Enable the I2S output */ 431 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09); 432} 433 434/* ----------------------------------------------------------------------- */ 435 436static int au8522_s_ctrl(struct v4l2_ctrl *ctrl) 437{ 438 struct au8522_state *state = 439 container_of(ctrl->handler, struct au8522_state, hdl); 440 441 switch (ctrl->id) { 442 case V4L2_CID_BRIGHTNESS: 443 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 444 ctrl->val - 128); 445 break; 446 case V4L2_CID_CONTRAST: 447 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 448 ctrl->val); 449 break; 450 case V4L2_CID_SATURATION: 451 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 452 ctrl->val); 453 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 454 ctrl->val); 455 break; 456 case V4L2_CID_HUE: 457 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 458 ctrl->val >> 8); 459 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 460 ctrl->val & 0xFF); 461 break; 462 default: 463 return -EINVAL; 464 } 465 466 return 0; 467} 468 469/* ----------------------------------------------------------------------- */ 470 471#ifdef CONFIG_VIDEO_ADV_DEBUG 472static int au8522_g_register(struct v4l2_subdev *sd, 473 struct v4l2_dbg_register *reg) 474{ 475 struct au8522_state *state = to_state(sd); 476 477 reg->val = au8522_readreg(state, reg->reg & 0xffff); 478 return 0; 479} 480 481static int au8522_s_register(struct v4l2_subdev *sd, 482 const struct v4l2_dbg_register *reg) 483{ 484 struct au8522_state *state = to_state(sd); 485 486 au8522_writereg(state, reg->reg, reg->val & 0xff); 487 return 0; 488} 489#endif 490 491static void au8522_video_set(struct au8522_state *state) 492{ 493 u8 input_mode; 494 495 au8522_writereg(state, 0xa4, 1 << 5); 496 497 switch (state->vid_input) { 498 case AU8522_COMPOSITE_CH1: 499 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH1; 500 au8522_setup_cvbs_mode(state, input_mode); 501 break; 502 case AU8522_COMPOSITE_CH2: 503 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH2; 504 au8522_setup_cvbs_mode(state, input_mode); 505 break; 506 case AU8522_COMPOSITE_CH3: 507 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH3; 508 au8522_setup_cvbs_mode(state, input_mode); 509 break; 510 case AU8522_COMPOSITE_CH4: 511 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4; 512 au8522_setup_cvbs_mode(state, input_mode); 513 break; 514 case AU8522_SVIDEO_CH13: 515 input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13; 516 au8522_setup_svideo_mode(state, input_mode); 517 break; 518 case AU8522_SVIDEO_CH24: 519 input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24; 520 au8522_setup_svideo_mode(state, input_mode); 521 break; 522 default: 523 case AU8522_COMPOSITE_CH4_SIF: 524 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF; 525 au8522_setup_cvbs_tuner_mode(state, input_mode); 526 break; 527 } 528} 529 530static int au8522_s_stream(struct v4l2_subdev *sd, int enable) 531{ 532 struct au8522_state *state = to_state(sd); 533 534 if (enable) { 535 /* 536 * Clear out any state associated with the digital side of the 537 * chip, so that when it gets powered back up it won't think 538 * that it is already tuned 539 */ 540 state->current_frequency = 0; 541 542 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 543 0x01); 544 msleep(10); 545 546 au8522_video_set(state); 547 set_audio_input(state); 548 549 state->operational_mode = AU8522_ANALOG_MODE; 550 } else { 551 /* This does not completely power down the device 552 (it only reduces it from around 140ma to 80ma) */ 553 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 554 1 << 5); 555 state->operational_mode = AU8522_SUSPEND_MODE; 556 } 557 return 0; 558} 559 560static int au8522_s_video_routing(struct v4l2_subdev *sd, 561 u32 input, u32 output, u32 config) 562{ 563 struct au8522_state *state = to_state(sd); 564 565 switch (input) { 566 case AU8522_COMPOSITE_CH1: 567 case AU8522_SVIDEO_CH13: 568 case AU8522_COMPOSITE_CH4_SIF: 569 state->vid_input = input; 570 break; 571 default: 572 printk(KERN_ERR "au8522 mode not currently supported\n"); 573 return -EINVAL; 574 } 575 576 if (state->operational_mode == AU8522_ANALOG_MODE) 577 au8522_video_set(state); 578 579 return 0; 580} 581 582static int au8522_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 583{ 584 struct au8522_state *state = to_state(sd); 585 586 if ((std & (V4L2_STD_PAL_M | V4L2_STD_NTSC_M)) == 0) 587 return -EINVAL; 588 589 state->std = std; 590 591 if (state->operational_mode == AU8522_ANALOG_MODE) 592 au8522_video_set(state); 593 594 return 0; 595} 596 597static int au8522_s_audio_routing(struct v4l2_subdev *sd, 598 u32 input, u32 output, u32 config) 599{ 600 struct au8522_state *state = to_state(sd); 601 602 state->aud_input = input; 603 604 if (state->operational_mode == AU8522_ANALOG_MODE) 605 set_audio_input(state); 606 607 return 0; 608} 609 610static int au8522_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt) 611{ 612 int val = 0; 613 struct au8522_state *state = to_state(sd); 614 u8 lock_status; 615 u8 pll_status; 616 617 /* Interrogate the decoder to see if we are getting a real signal */ 618 lock_status = au8522_readreg(state, 0x00); 619 pll_status = au8522_readreg(state, 0x7e); 620 if ((lock_status == 0xa2) && (pll_status & 0x10)) 621 vt->signal = 0xffff; 622 else 623 vt->signal = 0x00; 624 625 vt->capability |= 626 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 | 627 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP; 628 629 val = V4L2_TUNER_SUB_MONO; 630 vt->rxsubchans = val; 631 vt->audmode = V4L2_TUNER_MODE_STEREO; 632 return 0; 633} 634 635/* ----------------------------------------------------------------------- */ 636 637static const struct v4l2_subdev_core_ops au8522_core_ops = { 638 .log_status = v4l2_ctrl_subdev_log_status, 639#ifdef CONFIG_VIDEO_ADV_DEBUG 640 .g_register = au8522_g_register, 641 .s_register = au8522_s_register, 642#endif 643}; 644 645static const struct v4l2_subdev_tuner_ops au8522_tuner_ops = { 646 .g_tuner = au8522_g_tuner, 647}; 648 649static const struct v4l2_subdev_audio_ops au8522_audio_ops = { 650 .s_routing = au8522_s_audio_routing, 651}; 652 653static const struct v4l2_subdev_video_ops au8522_video_ops = { 654 .s_routing = au8522_s_video_routing, 655 .s_stream = au8522_s_stream, 656 .s_std = au8522_s_std, 657}; 658 659static const struct v4l2_subdev_ops au8522_ops = { 660 .core = &au8522_core_ops, 661 .tuner = &au8522_tuner_ops, 662 .audio = &au8522_audio_ops, 663 .video = &au8522_video_ops, 664}; 665 666static const struct v4l2_ctrl_ops au8522_ctrl_ops = { 667 .s_ctrl = au8522_s_ctrl, 668}; 669 670/* ----------------------------------------------------------------------- */ 671 672static int au8522_probe(struct i2c_client *client) 673{ 674 struct au8522_state *state; 675 struct v4l2_ctrl_handler *hdl; 676 struct v4l2_subdev *sd; 677 int instance; 678#ifdef CONFIG_MEDIA_CONTROLLER 679 int ret; 680#endif 681 682 /* Check if the adapter supports the needed features */ 683 if (!i2c_check_functionality(client->adapter, 684 I2C_FUNC_SMBUS_BYTE_DATA)) { 685 return -EIO; 686 } 687 688 /* allocate memory for the internal state */ 689 instance = au8522_get_state(&state, client->adapter, client->addr); 690 switch (instance) { 691 case 0: 692 printk(KERN_ERR "au8522_decoder allocation failed\n"); 693 return -EIO; 694 case 1: 695 /* new demod instance */ 696 printk(KERN_INFO "au8522_decoder creating new instance...\n"); 697 break; 698 default: 699 /* existing demod instance */ 700 printk(KERN_INFO "au8522_decoder attach existing instance.\n"); 701 break; 702 } 703 704 state->config.demod_address = 0x8e >> 1; 705 state->i2c = client->adapter; 706 707 sd = &state->sd; 708 v4l2_i2c_subdev_init(sd, client, &au8522_ops); 709#if defined(CONFIG_MEDIA_CONTROLLER) 710 711 state->pads[AU8522_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK; 712 state->pads[AU8522_PAD_IF_INPUT].sig_type = PAD_SIGNAL_ANALOG; 713 state->pads[AU8522_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE; 714 state->pads[AU8522_PAD_VID_OUT].sig_type = PAD_SIGNAL_DV; 715 state->pads[AU8522_PAD_AUDIO_OUT].flags = MEDIA_PAD_FL_SOURCE; 716 state->pads[AU8522_PAD_AUDIO_OUT].sig_type = PAD_SIGNAL_AUDIO; 717 sd->entity.function = MEDIA_ENT_F_ATV_DECODER; 718 719 ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(state->pads), 720 state->pads); 721 if (ret < 0) { 722 v4l_info(client, "failed to initialize media entity!\n"); 723 return ret; 724 } 725#endif 726 727 hdl = &state->hdl; 728 v4l2_ctrl_handler_init(hdl, 4); 729 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops, 730 V4L2_CID_BRIGHTNESS, 0, 255, 1, 109); 731 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops, 732 V4L2_CID_CONTRAST, 0, 255, 1, 733 AU8522_TVDEC_CONTRAST_REG00BH_CVBS); 734 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops, 735 V4L2_CID_SATURATION, 0, 255, 1, 128); 736 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops, 737 V4L2_CID_HUE, -32768, 32767, 1, 0); 738 sd->ctrl_handler = hdl; 739 if (hdl->error) { 740 int err = hdl->error; 741 742 v4l2_ctrl_handler_free(hdl); 743 au8522_release_state(state); 744 return err; 745 } 746 747 state->c = client; 748 state->std = V4L2_STD_NTSC_M; 749 state->vid_input = AU8522_COMPOSITE_CH1; 750 state->aud_input = AU8522_AUDIO_NONE; 751 state->id = 8522; 752 state->rev = 0; 753 754 /* Jam open the i2c gate to the tuner */ 755 au8522_writereg(state, 0x106, 1); 756 757 return 0; 758} 759 760static void au8522_remove(struct i2c_client *client) 761{ 762 struct v4l2_subdev *sd = i2c_get_clientdata(client); 763 v4l2_device_unregister_subdev(sd); 764 v4l2_ctrl_handler_free(sd->ctrl_handler); 765 au8522_release_state(to_state(sd)); 766} 767 768static const struct i2c_device_id au8522_id[] = { 769 {"au8522", 0}, 770 {} 771}; 772 773MODULE_DEVICE_TABLE(i2c, au8522_id); 774 775static struct i2c_driver au8522_driver = { 776 .driver = { 777 .name = "au8522", 778 }, 779 .probe = au8522_probe, 780 .remove = au8522_remove, 781 .id_table = au8522_id, 782}; 783 784module_i2c_driver(au8522_driver); 785