1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Afatech AF9033 demodulator driver 4 * 5 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi> 6 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> 7 */ 8 9#include "af9033_priv.h" 10 11struct af9033_dev { 12 struct i2c_client *client; 13 struct regmap *regmap; 14 struct dvb_frontend fe; 15 struct af9033_config cfg; 16 bool is_af9035; 17 bool is_it9135; 18 19 u32 bandwidth_hz; 20 bool ts_mode_parallel; 21 bool ts_mode_serial; 22 23 enum fe_status fe_status; 24 u64 post_bit_error_prev; /* for old read_ber we return (curr - prev) */ 25 u64 post_bit_error; 26 u64 post_bit_count; 27 u64 error_block_count; 28 u64 total_block_count; 29}; 30 31/* Write reg val table using reg addr auto increment */ 32static int af9033_wr_reg_val_tab(struct af9033_dev *dev, 33 const struct reg_val *tab, int tab_len) 34{ 35 struct i2c_client *client = dev->client; 36#define MAX_TAB_LEN 212 37 int ret, i, j; 38 u8 buf[1 + MAX_TAB_LEN]; 39 40 dev_dbg(&client->dev, "tab_len=%d\n", tab_len); 41 42 if (tab_len > sizeof(buf)) { 43 dev_warn(&client->dev, "tab len %d is too big\n", tab_len); 44 return -EINVAL; 45 } 46 47 for (i = 0, j = 0; i < tab_len; i++) { 48 buf[j] = tab[i].val; 49 50 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) { 51 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, 52 buf, j + 1); 53 if (ret) 54 goto err; 55 56 j = 0; 57 } else { 58 j++; 59 } 60 } 61 62 return 0; 63err: 64 dev_dbg(&client->dev, "failed=%d\n", ret); 65 return ret; 66} 67 68static int af9033_init(struct dvb_frontend *fe) 69{ 70 struct af9033_dev *dev = fe->demodulator_priv; 71 struct i2c_client *client = dev->client; 72 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 73 int ret, i, len; 74 unsigned int utmp; 75 const struct reg_val *init; 76 u8 buf[4]; 77 struct reg_val_mask tab[] = { 78 { 0x80fb24, 0x00, 0x08 }, 79 { 0x80004c, 0x00, 0xff }, 80 { 0x00f641, dev->cfg.tuner, 0xff }, 81 { 0x80f5ca, 0x01, 0x01 }, 82 { 0x80f715, 0x01, 0x01 }, 83 { 0x00f41f, 0x04, 0x04 }, 84 { 0x00f41a, 0x01, 0x01 }, 85 { 0x80f731, 0x00, 0x01 }, 86 { 0x00d91e, 0x00, 0x01 }, 87 { 0x00d919, 0x00, 0x01 }, 88 { 0x80f732, 0x00, 0x01 }, 89 { 0x00d91f, 0x00, 0x01 }, 90 { 0x00d91a, 0x00, 0x01 }, 91 { 0x80f730, 0x00, 0x01 }, 92 { 0x80f778, 0x00, 0xff }, 93 { 0x80f73c, 0x01, 0x01 }, 94 { 0x80f776, 0x00, 0x01 }, 95 { 0x00d8fd, 0x01, 0xff }, 96 { 0x00d830, 0x01, 0xff }, 97 { 0x00d831, 0x00, 0xff }, 98 { 0x00d832, 0x00, 0xff }, 99 { 0x80f985, dev->ts_mode_serial, 0x01 }, 100 { 0x80f986, dev->ts_mode_parallel, 0x01 }, 101 { 0x00d827, 0x00, 0xff }, 102 { 0x00d829, 0x00, 0xff }, 103 { 0x800045, dev->cfg.adc_multiplier, 0xff }, 104 }; 105 106 dev_dbg(&client->dev, "\n"); 107 108 /* Main clk control */ 109 utmp = div_u64((u64)dev->cfg.clock * 0x80000, 1000000); 110 buf[0] = (utmp >> 0) & 0xff; 111 buf[1] = (utmp >> 8) & 0xff; 112 buf[2] = (utmp >> 16) & 0xff; 113 buf[3] = (utmp >> 24) & 0xff; 114 ret = regmap_bulk_write(dev->regmap, 0x800025, buf, 4); 115 if (ret) 116 goto err; 117 118 dev_dbg(&client->dev, "clk=%u clk_cw=%08x\n", dev->cfg.clock, utmp); 119 120 /* ADC clk control */ 121 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { 122 if (clock_adc_lut[i].clock == dev->cfg.clock) 123 break; 124 } 125 if (i == ARRAY_SIZE(clock_adc_lut)) { 126 dev_err(&client->dev, "Couldn't find ADC config for clock %d\n", 127 dev->cfg.clock); 128 ret = -ENODEV; 129 goto err; 130 } 131 132 utmp = div_u64((u64)clock_adc_lut[i].adc * 0x80000, 1000000); 133 buf[0] = (utmp >> 0) & 0xff; 134 buf[1] = (utmp >> 8) & 0xff; 135 buf[2] = (utmp >> 16) & 0xff; 136 ret = regmap_bulk_write(dev->regmap, 0x80f1cd, buf, 3); 137 if (ret) 138 goto err; 139 140 dev_dbg(&client->dev, "adc=%u adc_cw=%06x\n", 141 clock_adc_lut[i].adc, utmp); 142 143 /* Config register table */ 144 for (i = 0; i < ARRAY_SIZE(tab); i++) { 145 ret = regmap_update_bits(dev->regmap, tab[i].reg, tab[i].mask, 146 tab[i].val); 147 if (ret) 148 goto err; 149 } 150 151 /* Demod clk output */ 152 if (dev->cfg.dyn0_clk) { 153 ret = regmap_write(dev->regmap, 0x80fba8, 0x00); 154 if (ret) 155 goto err; 156 } 157 158 /* TS interface */ 159 if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) { 160 ret = regmap_update_bits(dev->regmap, 0x80f9a5, 0x01, 0x00); 161 if (ret) 162 goto err; 163 ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x01); 164 if (ret) 165 goto err; 166 } else { 167 ret = regmap_update_bits(dev->regmap, 0x80f990, 0x01, 0x00); 168 if (ret) 169 goto err; 170 ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x00); 171 if (ret) 172 goto err; 173 } 174 175 /* Demod core settings */ 176 dev_dbg(&client->dev, "load ofsm settings\n"); 177 switch (dev->cfg.tuner) { 178 case AF9033_TUNER_IT9135_38: 179 case AF9033_TUNER_IT9135_51: 180 case AF9033_TUNER_IT9135_52: 181 len = ARRAY_SIZE(ofsm_init_it9135_v1); 182 init = ofsm_init_it9135_v1; 183 break; 184 case AF9033_TUNER_IT9135_60: 185 case AF9033_TUNER_IT9135_61: 186 case AF9033_TUNER_IT9135_62: 187 len = ARRAY_SIZE(ofsm_init_it9135_v2); 188 init = ofsm_init_it9135_v2; 189 break; 190 default: 191 len = ARRAY_SIZE(ofsm_init); 192 init = ofsm_init; 193 break; 194 } 195 196 ret = af9033_wr_reg_val_tab(dev, init, len); 197 if (ret) 198 goto err; 199 200 /* Demod tuner specific settings */ 201 dev_dbg(&client->dev, "load tuner specific settings\n"); 202 switch (dev->cfg.tuner) { 203 case AF9033_TUNER_TUA9001: 204 len = ARRAY_SIZE(tuner_init_tua9001); 205 init = tuner_init_tua9001; 206 break; 207 case AF9033_TUNER_FC0011: 208 len = ARRAY_SIZE(tuner_init_fc0011); 209 init = tuner_init_fc0011; 210 break; 211 case AF9033_TUNER_MXL5007T: 212 len = ARRAY_SIZE(tuner_init_mxl5007t); 213 init = tuner_init_mxl5007t; 214 break; 215 case AF9033_TUNER_TDA18218: 216 len = ARRAY_SIZE(tuner_init_tda18218); 217 init = tuner_init_tda18218; 218 break; 219 case AF9033_TUNER_FC2580: 220 len = ARRAY_SIZE(tuner_init_fc2580); 221 init = tuner_init_fc2580; 222 break; 223 case AF9033_TUNER_FC0012: 224 len = ARRAY_SIZE(tuner_init_fc0012); 225 init = tuner_init_fc0012; 226 break; 227 case AF9033_TUNER_IT9135_38: 228 len = ARRAY_SIZE(tuner_init_it9135_38); 229 init = tuner_init_it9135_38; 230 break; 231 case AF9033_TUNER_IT9135_51: 232 len = ARRAY_SIZE(tuner_init_it9135_51); 233 init = tuner_init_it9135_51; 234 break; 235 case AF9033_TUNER_IT9135_52: 236 len = ARRAY_SIZE(tuner_init_it9135_52); 237 init = tuner_init_it9135_52; 238 break; 239 case AF9033_TUNER_IT9135_60: 240 len = ARRAY_SIZE(tuner_init_it9135_60); 241 init = tuner_init_it9135_60; 242 break; 243 case AF9033_TUNER_IT9135_61: 244 len = ARRAY_SIZE(tuner_init_it9135_61); 245 init = tuner_init_it9135_61; 246 break; 247 case AF9033_TUNER_IT9135_62: 248 len = ARRAY_SIZE(tuner_init_it9135_62); 249 init = tuner_init_it9135_62; 250 break; 251 default: 252 dev_dbg(&client->dev, "unsupported tuner ID=%d\n", 253 dev->cfg.tuner); 254 ret = -ENODEV; 255 goto err; 256 } 257 258 ret = af9033_wr_reg_val_tab(dev, init, len); 259 if (ret) 260 goto err; 261 262 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { 263 ret = regmap_update_bits(dev->regmap, 0x00d91c, 0x01, 0x01); 264 if (ret) 265 goto err; 266 ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00); 267 if (ret) 268 goto err; 269 ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x00); 270 if (ret) 271 goto err; 272 } 273 274 switch (dev->cfg.tuner) { 275 case AF9033_TUNER_IT9135_60: 276 case AF9033_TUNER_IT9135_61: 277 case AF9033_TUNER_IT9135_62: 278 ret = regmap_write(dev->regmap, 0x800000, 0x01); 279 if (ret) 280 goto err; 281 } 282 283 dev->bandwidth_hz = 0; /* Force to program all parameters */ 284 /* Init stats here in order signal app which stats are supported */ 285 c->strength.len = 1; 286 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 287 c->cnr.len = 1; 288 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 289 c->block_count.len = 1; 290 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 291 c->block_error.len = 1; 292 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 293 c->post_bit_count.len = 1; 294 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 295 c->post_bit_error.len = 1; 296 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 297 298 return 0; 299err: 300 dev_dbg(&client->dev, "failed=%d\n", ret); 301 return ret; 302} 303 304static int af9033_sleep(struct dvb_frontend *fe) 305{ 306 struct af9033_dev *dev = fe->demodulator_priv; 307 struct i2c_client *client = dev->client; 308 int ret; 309 unsigned int utmp; 310 311 dev_dbg(&client->dev, "\n"); 312 313 ret = regmap_write(dev->regmap, 0x80004c, 0x01); 314 if (ret) 315 goto err; 316 ret = regmap_write(dev->regmap, 0x800000, 0x00); 317 if (ret) 318 goto err; 319 ret = regmap_read_poll_timeout(dev->regmap, 0x80004c, utmp, utmp == 0, 320 5000, 1000000); 321 if (ret) 322 goto err; 323 ret = regmap_update_bits(dev->regmap, 0x80fb24, 0x08, 0x08); 324 if (ret) 325 goto err; 326 327 /* Prevent current leak by setting TS interface to parallel mode */ 328 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { 329 /* Enable parallel TS */ 330 ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00); 331 if (ret) 332 goto err; 333 ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x01); 334 if (ret) 335 goto err; 336 } 337 338 return 0; 339err: 340 dev_dbg(&client->dev, "failed=%d\n", ret); 341 return ret; 342} 343 344static int af9033_get_tune_settings(struct dvb_frontend *fe, 345 struct dvb_frontend_tune_settings *fesettings) 346{ 347 /* 800 => 2000 because IT9135 v2 is slow to gain lock */ 348 fesettings->min_delay_ms = 2000; 349 fesettings->step_size = 0; 350 fesettings->max_drift = 0; 351 352 return 0; 353} 354 355static int af9033_set_frontend(struct dvb_frontend *fe) 356{ 357 struct af9033_dev *dev = fe->demodulator_priv; 358 struct i2c_client *client = dev->client; 359 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 360 int ret, i; 361 unsigned int utmp, adc_freq; 362 u8 tmp, buf[3], bandwidth_reg_val; 363 u32 if_frequency; 364 365 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u\n", 366 c->frequency, c->bandwidth_hz); 367 368 /* Check bandwidth */ 369 switch (c->bandwidth_hz) { 370 case 6000000: 371 bandwidth_reg_val = 0x00; 372 break; 373 case 7000000: 374 bandwidth_reg_val = 0x01; 375 break; 376 case 8000000: 377 bandwidth_reg_val = 0x02; 378 break; 379 default: 380 dev_dbg(&client->dev, "invalid bandwidth_hz\n"); 381 ret = -EINVAL; 382 goto err; 383 } 384 385 /* Program tuner */ 386 if (fe->ops.tuner_ops.set_params) 387 fe->ops.tuner_ops.set_params(fe); 388 389 /* Coefficients */ 390 if (c->bandwidth_hz != dev->bandwidth_hz) { 391 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) { 392 if (coeff_lut[i].clock == dev->cfg.clock && 393 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) { 394 break; 395 } 396 } 397 if (i == ARRAY_SIZE(coeff_lut)) { 398 dev_err(&client->dev, 399 "Couldn't find config for clock %u\n", 400 dev->cfg.clock); 401 ret = -EINVAL; 402 goto err; 403 } 404 405 ret = regmap_bulk_write(dev->regmap, 0x800001, coeff_lut[i].val, 406 sizeof(coeff_lut[i].val)); 407 if (ret) 408 goto err; 409 } 410 411 /* IF frequency control */ 412 if (c->bandwidth_hz != dev->bandwidth_hz) { 413 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { 414 if (clock_adc_lut[i].clock == dev->cfg.clock) 415 break; 416 } 417 if (i == ARRAY_SIZE(clock_adc_lut)) { 418 dev_err(&client->dev, 419 "Couldn't find ADC clock for clock %u\n", 420 dev->cfg.clock); 421 ret = -EINVAL; 422 goto err; 423 } 424 adc_freq = clock_adc_lut[i].adc; 425 426 if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X) 427 adc_freq = 2 * adc_freq; 428 429 /* Get used IF frequency */ 430 if (fe->ops.tuner_ops.get_if_frequency) 431 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency); 432 else 433 if_frequency = 0; 434 435 utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x800000, 436 adc_freq); 437 438 if (!dev->cfg.spec_inv && if_frequency) 439 utmp = 0x800000 - utmp; 440 441 buf[0] = (utmp >> 0) & 0xff; 442 buf[1] = (utmp >> 8) & 0xff; 443 buf[2] = (utmp >> 16) & 0xff; 444 ret = regmap_bulk_write(dev->regmap, 0x800029, buf, 3); 445 if (ret) 446 goto err; 447 448 dev_dbg(&client->dev, "if_frequency_cw=%06x\n", utmp); 449 450 dev->bandwidth_hz = c->bandwidth_hz; 451 } 452 453 ret = regmap_update_bits(dev->regmap, 0x80f904, 0x03, 454 bandwidth_reg_val); 455 if (ret) 456 goto err; 457 ret = regmap_write(dev->regmap, 0x800040, 0x00); 458 if (ret) 459 goto err; 460 ret = regmap_write(dev->regmap, 0x800047, 0x00); 461 if (ret) 462 goto err; 463 ret = regmap_update_bits(dev->regmap, 0x80f999, 0x01, 0x00); 464 if (ret) 465 goto err; 466 467 if (c->frequency <= 230000000) 468 tmp = 0x00; /* VHF */ 469 else 470 tmp = 0x01; /* UHF */ 471 472 ret = regmap_write(dev->regmap, 0x80004b, tmp); 473 if (ret) 474 goto err; 475 /* Reset FSM */ 476 ret = regmap_write(dev->regmap, 0x800000, 0x00); 477 if (ret) 478 goto err; 479 480 return 0; 481err: 482 dev_dbg(&client->dev, "failed=%d\n", ret); 483 return ret; 484} 485 486static int af9033_get_frontend(struct dvb_frontend *fe, 487 struct dtv_frontend_properties *c) 488{ 489 struct af9033_dev *dev = fe->demodulator_priv; 490 struct i2c_client *client = dev->client; 491 int ret; 492 u8 buf[8]; 493 494 dev_dbg(&client->dev, "\n"); 495 496 /* Read all needed TPS registers */ 497 ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 8); 498 if (ret) 499 goto err; 500 501 switch ((buf[0] >> 0) & 3) { 502 case 0: 503 c->transmission_mode = TRANSMISSION_MODE_2K; 504 break; 505 case 1: 506 c->transmission_mode = TRANSMISSION_MODE_8K; 507 break; 508 } 509 510 switch ((buf[1] >> 0) & 3) { 511 case 0: 512 c->guard_interval = GUARD_INTERVAL_1_32; 513 break; 514 case 1: 515 c->guard_interval = GUARD_INTERVAL_1_16; 516 break; 517 case 2: 518 c->guard_interval = GUARD_INTERVAL_1_8; 519 break; 520 case 3: 521 c->guard_interval = GUARD_INTERVAL_1_4; 522 break; 523 } 524 525 switch ((buf[2] >> 0) & 7) { 526 case 0: 527 c->hierarchy = HIERARCHY_NONE; 528 break; 529 case 1: 530 c->hierarchy = HIERARCHY_1; 531 break; 532 case 2: 533 c->hierarchy = HIERARCHY_2; 534 break; 535 case 3: 536 c->hierarchy = HIERARCHY_4; 537 break; 538 } 539 540 switch ((buf[3] >> 0) & 3) { 541 case 0: 542 c->modulation = QPSK; 543 break; 544 case 1: 545 c->modulation = QAM_16; 546 break; 547 case 2: 548 c->modulation = QAM_64; 549 break; 550 } 551 552 switch ((buf[4] >> 0) & 3) { 553 case 0: 554 c->bandwidth_hz = 6000000; 555 break; 556 case 1: 557 c->bandwidth_hz = 7000000; 558 break; 559 case 2: 560 c->bandwidth_hz = 8000000; 561 break; 562 } 563 564 switch ((buf[6] >> 0) & 7) { 565 case 0: 566 c->code_rate_HP = FEC_1_2; 567 break; 568 case 1: 569 c->code_rate_HP = FEC_2_3; 570 break; 571 case 2: 572 c->code_rate_HP = FEC_3_4; 573 break; 574 case 3: 575 c->code_rate_HP = FEC_5_6; 576 break; 577 case 4: 578 c->code_rate_HP = FEC_7_8; 579 break; 580 case 5: 581 c->code_rate_HP = FEC_NONE; 582 break; 583 } 584 585 switch ((buf[7] >> 0) & 7) { 586 case 0: 587 c->code_rate_LP = FEC_1_2; 588 break; 589 case 1: 590 c->code_rate_LP = FEC_2_3; 591 break; 592 case 2: 593 c->code_rate_LP = FEC_3_4; 594 break; 595 case 3: 596 c->code_rate_LP = FEC_5_6; 597 break; 598 case 4: 599 c->code_rate_LP = FEC_7_8; 600 break; 601 case 5: 602 c->code_rate_LP = FEC_NONE; 603 break; 604 } 605 606 return 0; 607err: 608 dev_dbg(&client->dev, "failed=%d\n", ret); 609 return ret; 610} 611 612static int af9033_read_status(struct dvb_frontend *fe, enum fe_status *status) 613{ 614 struct af9033_dev *dev = fe->demodulator_priv; 615 struct i2c_client *client = dev->client; 616 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 617 int ret, tmp = 0; 618 u8 buf[7]; 619 unsigned int utmp, utmp1; 620 621 dev_dbg(&client->dev, "\n"); 622 623 *status = 0; 624 625 /* Radio channel status: 0=no result, 1=has signal, 2=no signal */ 626 ret = regmap_read(dev->regmap, 0x800047, &utmp); 627 if (ret) 628 goto err; 629 630 /* Has signal */ 631 if (utmp == 0x01) 632 *status |= FE_HAS_SIGNAL; 633 634 if (utmp != 0x02) { 635 /* TPS lock */ 636 ret = regmap_read(dev->regmap, 0x80f5a9, &utmp); 637 if (ret) 638 goto err; 639 640 if ((utmp >> 0) & 0x01) 641 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 642 FE_HAS_VITERBI; 643 644 /* Full lock */ 645 ret = regmap_read(dev->regmap, 0x80f999, &utmp); 646 if (ret) 647 goto err; 648 649 if ((utmp >> 0) & 0x01) 650 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | 651 FE_HAS_VITERBI | FE_HAS_SYNC | 652 FE_HAS_LOCK; 653 } 654 655 dev->fe_status = *status; 656 657 /* Signal strength */ 658 if (dev->fe_status & FE_HAS_SIGNAL) { 659 if (dev->is_af9035) { 660 ret = regmap_read(dev->regmap, 0x80004a, &utmp); 661 if (ret) 662 goto err; 663 tmp = -utmp * 1000; 664 } else { 665 ret = regmap_read(dev->regmap, 0x8000f7, &utmp); 666 if (ret) 667 goto err; 668 tmp = (utmp - 100) * 1000; 669 } 670 671 c->strength.len = 1; 672 c->strength.stat[0].scale = FE_SCALE_DECIBEL; 673 c->strength.stat[0].svalue = tmp; 674 } else { 675 c->strength.len = 1; 676 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 677 } 678 679 /* CNR */ 680 if (dev->fe_status & FE_HAS_VITERBI) { 681 /* Read raw SNR value */ 682 ret = regmap_bulk_read(dev->regmap, 0x80002c, buf, 3); 683 if (ret) 684 goto err; 685 686 utmp1 = buf[2] << 16 | buf[1] << 8 | buf[0] << 0; 687 688 /* Read superframe number */ 689 ret = regmap_read(dev->regmap, 0x80f78b, &utmp); 690 if (ret) 691 goto err; 692 693 if (utmp) 694 utmp1 /= utmp; 695 696 /* Read current transmission mode */ 697 ret = regmap_read(dev->regmap, 0x80f900, &utmp); 698 if (ret) 699 goto err; 700 701 switch ((utmp >> 0) & 3) { 702 case 0: 703 /* 2k */ 704 utmp1 *= 4; 705 break; 706 case 1: 707 /* 8k */ 708 utmp1 *= 1; 709 break; 710 case 2: 711 /* 4k */ 712 utmp1 *= 2; 713 break; 714 default: 715 utmp1 *= 0; 716 break; 717 } 718 719 /* Read current modulation */ 720 ret = regmap_read(dev->regmap, 0x80f903, &utmp); 721 if (ret) 722 goto err; 723 724 switch ((utmp >> 0) & 3) { 725 case 0: 726 /* 727 * QPSK 728 * CNR[dB] 13 * -log10((1690000 - value) / value) + 2.6 729 * value [653799, 1689999], 2.6 / 13 = 3355443 730 */ 731 utmp1 = clamp(utmp1, 653799U, 1689999U); 732 utmp1 = ((u64)(intlog10(utmp1) 733 - intlog10(1690000 - utmp1) 734 + 3355443) * 13 * 1000) >> 24; 735 break; 736 case 1: 737 /* 738 * QAM-16 739 * CNR[dB] 6 * log10((value - 370000) / (828000 - value)) + 15.7 740 * value [371105, 827999], 15.7 / 6 = 43900382 741 */ 742 utmp1 = clamp(utmp1, 371105U, 827999U); 743 utmp1 = ((u64)(intlog10(utmp1 - 370000) 744 - intlog10(828000 - utmp1) 745 + 43900382) * 6 * 1000) >> 24; 746 break; 747 case 2: 748 /* 749 * QAM-64 750 * CNR[dB] 8 * log10((value - 193000) / (425000 - value)) + 23.8 751 * value [193246, 424999], 23.8 / 8 = 49912218 752 */ 753 utmp1 = clamp(utmp1, 193246U, 424999U); 754 utmp1 = ((u64)(intlog10(utmp1 - 193000) 755 - intlog10(425000 - utmp1) 756 + 49912218) * 8 * 1000) >> 24; 757 break; 758 default: 759 utmp1 = 0; 760 break; 761 } 762 763 dev_dbg(&client->dev, "cnr=%u\n", utmp1); 764 765 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 766 c->cnr.stat[0].svalue = utmp1; 767 } else { 768 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 769 } 770 771 /* UCB/PER/BER */ 772 if (dev->fe_status & FE_HAS_LOCK) { 773 /* Outer FEC, 204 byte packets */ 774 u16 abort_packet_count, rsd_packet_count; 775 /* Inner FEC, bits */ 776 u32 rsd_bit_err_count; 777 778 /* 779 * Packet count used for measurement is 10000 780 * (rsd_packet_count). Maybe it should be increased? 781 */ 782 783 ret = regmap_bulk_read(dev->regmap, 0x800032, buf, 7); 784 if (ret) 785 goto err; 786 787 abort_packet_count = (buf[1] << 8) | (buf[0] << 0); 788 rsd_bit_err_count = (buf[4] << 16) | (buf[3] << 8) | buf[2]; 789 rsd_packet_count = (buf[6] << 8) | (buf[5] << 0); 790 791 dev->error_block_count += abort_packet_count; 792 dev->total_block_count += rsd_packet_count; 793 dev->post_bit_error += rsd_bit_err_count; 794 dev->post_bit_count += rsd_packet_count * 204 * 8; 795 796 c->block_count.len = 1; 797 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 798 c->block_count.stat[0].uvalue = dev->total_block_count; 799 800 c->block_error.len = 1; 801 c->block_error.stat[0].scale = FE_SCALE_COUNTER; 802 c->block_error.stat[0].uvalue = dev->error_block_count; 803 804 c->post_bit_count.len = 1; 805 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 806 c->post_bit_count.stat[0].uvalue = dev->post_bit_count; 807 808 c->post_bit_error.len = 1; 809 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 810 c->post_bit_error.stat[0].uvalue = dev->post_bit_error; 811 } 812 813 return 0; 814err: 815 dev_dbg(&client->dev, "failed=%d\n", ret); 816 return ret; 817} 818 819static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr) 820{ 821 struct af9033_dev *dev = fe->demodulator_priv; 822 struct i2c_client *client = dev->client; 823 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache; 824 int ret; 825 unsigned int utmp; 826 827 dev_dbg(&client->dev, "\n"); 828 829 /* Use DVBv5 CNR */ 830 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) { 831 /* Return 0.1 dB for AF9030 and 0-0xffff for IT9130. */ 832 if (dev->is_af9035) { 833 /* 1000x => 10x (0.1 dB) */ 834 *snr = div_s64(c->cnr.stat[0].svalue, 100); 835 } else { 836 /* 1000x => 1x (1 dB) */ 837 *snr = div_s64(c->cnr.stat[0].svalue, 1000); 838 839 /* Read current modulation */ 840 ret = regmap_read(dev->regmap, 0x80f903, &utmp); 841 if (ret) 842 goto err; 843 844 /* scale value to 0x0000-0xffff */ 845 switch ((utmp >> 0) & 3) { 846 case 0: 847 *snr = *snr * 0xffff / 23; 848 break; 849 case 1: 850 *snr = *snr * 0xffff / 26; 851 break; 852 case 2: 853 *snr = *snr * 0xffff / 32; 854 break; 855 default: 856 ret = -EINVAL; 857 goto err; 858 } 859 } 860 } else { 861 *snr = 0; 862 } 863 864 return 0; 865err: 866 dev_dbg(&client->dev, "failed=%d\n", ret); 867 return ret; 868} 869 870static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 871{ 872 struct af9033_dev *dev = fe->demodulator_priv; 873 struct i2c_client *client = dev->client; 874 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache; 875 int ret, tmp, power_real; 876 unsigned int utmp; 877 u8 gain_offset, buf[7]; 878 879 dev_dbg(&client->dev, "\n"); 880 881 if (dev->is_af9035) { 882 /* Read signal strength of 0-100 scale */ 883 ret = regmap_read(dev->regmap, 0x800048, &utmp); 884 if (ret) 885 goto err; 886 887 /* Scale value to 0x0000-0xffff */ 888 *strength = utmp * 0xffff / 100; 889 } else { 890 ret = regmap_read(dev->regmap, 0x8000f7, &utmp); 891 if (ret) 892 goto err; 893 894 ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 7); 895 if (ret) 896 goto err; 897 898 if (c->frequency <= 300000000) 899 gain_offset = 7; /* VHF */ 900 else 901 gain_offset = 4; /* UHF */ 902 903 power_real = (utmp - 100 - gain_offset) - 904 power_reference[((buf[3] >> 0) & 3)][((buf[6] >> 0) & 7)]; 905 906 if (power_real < -15) 907 tmp = 0; 908 else if ((power_real >= -15) && (power_real < 0)) 909 tmp = (2 * (power_real + 15)) / 3; 910 else if ((power_real >= 0) && (power_real < 20)) 911 tmp = 4 * power_real + 10; 912 else if ((power_real >= 20) && (power_real < 35)) 913 tmp = (2 * (power_real - 20)) / 3 + 90; 914 else 915 tmp = 100; 916 917 /* Scale value to 0x0000-0xffff */ 918 *strength = tmp * 0xffff / 100; 919 } 920 921 return 0; 922err: 923 dev_dbg(&client->dev, "failed=%d\n", ret); 924 return ret; 925} 926 927static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber) 928{ 929 struct af9033_dev *dev = fe->demodulator_priv; 930 931 *ber = (dev->post_bit_error - dev->post_bit_error_prev); 932 dev->post_bit_error_prev = dev->post_bit_error; 933 934 return 0; 935} 936 937static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 938{ 939 struct af9033_dev *dev = fe->demodulator_priv; 940 941 *ucblocks = dev->error_block_count; 942 943 return 0; 944} 945 946static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 947{ 948 struct af9033_dev *dev = fe->demodulator_priv; 949 struct i2c_client *client = dev->client; 950 int ret; 951 952 dev_dbg(&client->dev, "enable=%d\n", enable); 953 954 ret = regmap_update_bits(dev->regmap, 0x00fa04, 0x01, enable); 955 if (ret) 956 goto err; 957 958 return 0; 959err: 960 dev_dbg(&client->dev, "failed=%d\n", ret); 961 return ret; 962} 963 964static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff) 965{ 966 struct af9033_dev *dev = fe->demodulator_priv; 967 struct i2c_client *client = dev->client; 968 int ret; 969 970 dev_dbg(&client->dev, "onoff=%d\n", onoff); 971 972 ret = regmap_update_bits(dev->regmap, 0x80f993, 0x01, onoff); 973 if (ret) 974 goto err; 975 976 return 0; 977err: 978 dev_dbg(&client->dev, "failed=%d\n", ret); 979 return ret; 980} 981 982static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, 983 int onoff) 984{ 985 struct af9033_dev *dev = fe->demodulator_priv; 986 struct i2c_client *client = dev->client; 987 int ret; 988 u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff}; 989 990 dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n", 991 index, pid, onoff); 992 993 if (pid > 0x1fff) 994 return 0; 995 996 ret = regmap_bulk_write(dev->regmap, 0x80f996, wbuf, 2); 997 if (ret) 998 goto err; 999 ret = regmap_write(dev->regmap, 0x80f994, onoff); 1000 if (ret) 1001 goto err; 1002 ret = regmap_write(dev->regmap, 0x80f995, index); 1003 if (ret) 1004 goto err; 1005 1006 return 0; 1007err: 1008 dev_dbg(&client->dev, "failed=%d\n", ret); 1009 return ret; 1010} 1011 1012static const struct dvb_frontend_ops af9033_ops = { 1013 .delsys = {SYS_DVBT}, 1014 .info = { 1015 .name = "Afatech AF9033 (DVB-T)", 1016 .frequency_min_hz = 174 * MHz, 1017 .frequency_max_hz = 862 * MHz, 1018 .frequency_stepsize_hz = 250 * kHz, 1019 .caps = FE_CAN_FEC_1_2 | 1020 FE_CAN_FEC_2_3 | 1021 FE_CAN_FEC_3_4 | 1022 FE_CAN_FEC_5_6 | 1023 FE_CAN_FEC_7_8 | 1024 FE_CAN_FEC_AUTO | 1025 FE_CAN_QPSK | 1026 FE_CAN_QAM_16 | 1027 FE_CAN_QAM_64 | 1028 FE_CAN_QAM_AUTO | 1029 FE_CAN_TRANSMISSION_MODE_AUTO | 1030 FE_CAN_GUARD_INTERVAL_AUTO | 1031 FE_CAN_HIERARCHY_AUTO | 1032 FE_CAN_RECOVER | 1033 FE_CAN_MUTE_TS 1034 }, 1035 1036 .init = af9033_init, 1037 .sleep = af9033_sleep, 1038 1039 .get_tune_settings = af9033_get_tune_settings, 1040 .set_frontend = af9033_set_frontend, 1041 .get_frontend = af9033_get_frontend, 1042 1043 .read_status = af9033_read_status, 1044 .read_snr = af9033_read_snr, 1045 .read_signal_strength = af9033_read_signal_strength, 1046 .read_ber = af9033_read_ber, 1047 .read_ucblocks = af9033_read_ucblocks, 1048 1049 .i2c_gate_ctrl = af9033_i2c_gate_ctrl, 1050}; 1051 1052static int af9033_probe(struct i2c_client *client) 1053{ 1054 struct af9033_config *cfg = client->dev.platform_data; 1055 struct af9033_dev *dev; 1056 int ret; 1057 u8 buf[8]; 1058 u32 reg; 1059 static const struct regmap_config regmap_config = { 1060 .reg_bits = 24, 1061 .val_bits = 8, 1062 }; 1063 1064 /* Allocate memory for the internal state */ 1065 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1066 if (!dev) { 1067 ret = -ENOMEM; 1068 goto err; 1069 } 1070 1071 /* Setup the state */ 1072 dev->client = client; 1073 memcpy(&dev->cfg, cfg, sizeof(dev->cfg)); 1074 switch (dev->cfg.ts_mode) { 1075 case AF9033_TS_MODE_PARALLEL: 1076 dev->ts_mode_parallel = true; 1077 break; 1078 case AF9033_TS_MODE_SERIAL: 1079 dev->ts_mode_serial = true; 1080 break; 1081 case AF9033_TS_MODE_USB: 1082 /* USB mode for AF9035 */ 1083 default: 1084 break; 1085 } 1086 1087 if (dev->cfg.clock != 12000000) { 1088 ret = -ENODEV; 1089 dev_err(&client->dev, 1090 "Unsupported clock %u Hz. Only 12000000 Hz is supported currently\n", 1091 dev->cfg.clock); 1092 goto err_kfree; 1093 } 1094 1095 /* Create regmap */ 1096 dev->regmap = regmap_init_i2c(client, ®map_config); 1097 if (IS_ERR(dev->regmap)) { 1098 ret = PTR_ERR(dev->regmap); 1099 goto err_kfree; 1100 } 1101 1102 /* Firmware version */ 1103 switch (dev->cfg.tuner) { 1104 case AF9033_TUNER_IT9135_38: 1105 case AF9033_TUNER_IT9135_51: 1106 case AF9033_TUNER_IT9135_52: 1107 case AF9033_TUNER_IT9135_60: 1108 case AF9033_TUNER_IT9135_61: 1109 case AF9033_TUNER_IT9135_62: 1110 dev->is_it9135 = true; 1111 reg = 0x004bfc; 1112 break; 1113 default: 1114 dev->is_af9035 = true; 1115 reg = 0x0083e9; 1116 break; 1117 } 1118 1119 ret = regmap_bulk_read(dev->regmap, reg, &buf[0], 4); 1120 if (ret) 1121 goto err_regmap_exit; 1122 ret = regmap_bulk_read(dev->regmap, 0x804191, &buf[4], 4); 1123 if (ret) 1124 goto err_regmap_exit; 1125 1126 dev_info(&client->dev, 1127 "firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n", 1128 buf[0], buf[1], buf[2], buf[3], 1129 buf[4], buf[5], buf[6], buf[7]); 1130 1131 /* Sleep as chip seems to be partly active by default */ 1132 /* IT9135 did not like to sleep at that early */ 1133 if (dev->is_af9035) { 1134 ret = regmap_write(dev->regmap, 0x80004c, 0x01); 1135 if (ret) 1136 goto err_regmap_exit; 1137 ret = regmap_write(dev->regmap, 0x800000, 0x00); 1138 if (ret) 1139 goto err_regmap_exit; 1140 } 1141 1142 /* Create dvb frontend */ 1143 memcpy(&dev->fe.ops, &af9033_ops, sizeof(dev->fe.ops)); 1144 dev->fe.demodulator_priv = dev; 1145 *cfg->fe = &dev->fe; 1146 if (cfg->ops) { 1147 cfg->ops->pid_filter = af9033_pid_filter; 1148 cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl; 1149 } 1150 cfg->regmap = dev->regmap; 1151 i2c_set_clientdata(client, dev); 1152 1153 dev_info(&client->dev, "Afatech AF9033 successfully attached\n"); 1154 1155 return 0; 1156err_regmap_exit: 1157 regmap_exit(dev->regmap); 1158err_kfree: 1159 kfree(dev); 1160err: 1161 dev_dbg(&client->dev, "failed=%d\n", ret); 1162 return ret; 1163} 1164 1165static void af9033_remove(struct i2c_client *client) 1166{ 1167 struct af9033_dev *dev = i2c_get_clientdata(client); 1168 1169 dev_dbg(&client->dev, "\n"); 1170 1171 regmap_exit(dev->regmap); 1172 kfree(dev); 1173} 1174 1175static const struct i2c_device_id af9033_id_table[] = { 1176 {"af9033", 0}, 1177 {} 1178}; 1179MODULE_DEVICE_TABLE(i2c, af9033_id_table); 1180 1181static struct i2c_driver af9033_driver = { 1182 .driver = { 1183 .name = "af9033", 1184 .suppress_bind_attrs = true, 1185 }, 1186 .probe = af9033_probe, 1187 .remove = af9033_remove, 1188 .id_table = af9033_id_table, 1189}; 1190 1191module_i2c_driver(af9033_driver); 1192 1193MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 1194MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver"); 1195MODULE_LICENSE("GPL"); 1196