1109998Smarkm/* SPDX-License-Identifier: GPL-2.0-only */ 2109998Smarkm/* drivers/media/platform/s5p-cec/regs-cec.h 3109998Smarkm * 4109998Smarkm * Copyright (c) 2010 Samsung Electronics 5109998Smarkm * http://www.samsung.com/ 6109998Smarkm * 7109998Smarkm * register header file for Samsung TVOUT driver 8280297Sjkim */ 9109998Smarkm 10109998Smarkm#ifndef __EXYNOS_REGS__H 11109998Smarkm#define __EXYNOS_REGS__H 12109998Smarkm 13109998Smarkm/* 14109998Smarkm * Register part 15280297Sjkim */ 16109998Smarkm#define S5P_CEC_STATUS_0 (0x0000) 17109998Smarkm#define S5P_CEC_STATUS_1 (0x0004) 18109998Smarkm#define S5P_CEC_STATUS_2 (0x0008) 19109998Smarkm#define S5P_CEC_STATUS_3 (0x000C) 20109998Smarkm#define S5P_CEC_IRQ_MASK (0x0010) 21109998Smarkm#define S5P_CEC_IRQ_CLEAR (0x0014) 22280297Sjkim#define S5P_CEC_LOGIC_ADDR (0x0020) 23109998Smarkm#define S5P_CEC_DIVISOR_0 (0x0030) 24109998Smarkm#define S5P_CEC_DIVISOR_1 (0x0034) 25109998Smarkm#define S5P_CEC_DIVISOR_2 (0x0038) 26109998Smarkm#define S5P_CEC_DIVISOR_3 (0x003C) 27109998Smarkm 28109998Smarkm#define S5P_CEC_TX_CTRL (0x0040) 29109998Smarkm#define S5P_CEC_TX_BYTES (0x0044) 30109998Smarkm#define S5P_CEC_TX_STAT0 (0x0060) 31109998Smarkm#define S5P_CEC_TX_STAT1 (0x0064) 32109998Smarkm#define S5P_CEC_TX_BUFF0 (0x0080) 33109998Smarkm#define S5P_CEC_TX_BUFF1 (0x0084) 34109998Smarkm#define S5P_CEC_TX_BUFF2 (0x0088) 35109998Smarkm#define S5P_CEC_TX_BUFF3 (0x008C) 36109998Smarkm#define S5P_CEC_TX_BUFF4 (0x0090) 37280297Sjkim#define S5P_CEC_TX_BUFF5 (0x0094) 38109998Smarkm#define S5P_CEC_TX_BUFF6 (0x0098) 39109998Smarkm#define S5P_CEC_TX_BUFF7 (0x009C) 40280297Sjkim#define S5P_CEC_TX_BUFF8 (0x00A0) 41109998Smarkm#define S5P_CEC_TX_BUFF9 (0x00A4) 42109998Smarkm#define S5P_CEC_TX_BUFF10 (0x00A8) 43109998Smarkm#define S5P_CEC_TX_BUFF11 (0x00AC) 44109998Smarkm#define S5P_CEC_TX_BUFF12 (0x00B0) 45109998Smarkm#define S5P_CEC_TX_BUFF13 (0x00B4) 46109998Smarkm#define S5P_CEC_TX_BUFF14 (0x00B8) 47109998Smarkm#define S5P_CEC_TX_BUFF15 (0x00BC) 48109998Smarkm 49109998Smarkm#define S5P_CEC_RX_CTRL (0x00C0) 50109998Smarkm#define S5P_CEC_RX_STAT0 (0x00E0) 51109998Smarkm#define S5P_CEC_RX_STAT1 (0x00E4) 52280297Sjkim#define S5P_CEC_RX_BUFF0 (0x0100) 53109998Smarkm#define S5P_CEC_RX_BUFF1 (0x0104) 54109998Smarkm#define S5P_CEC_RX_BUFF2 (0x0108) 55109998Smarkm#define S5P_CEC_RX_BUFF3 (0x010C) 56109998Smarkm#define S5P_CEC_RX_BUFF4 (0x0110) 57109998Smarkm#define S5P_CEC_RX_BUFF5 (0x0114) 58109998Smarkm#define S5P_CEC_RX_BUFF6 (0x0118) 59109998Smarkm#define S5P_CEC_RX_BUFF7 (0x011C) 60109998Smarkm#define S5P_CEC_RX_BUFF8 (0x0120) 61109998Smarkm#define S5P_CEC_RX_BUFF9 (0x0124) 62109998Smarkm#define S5P_CEC_RX_BUFF10 (0x0128) 63109998Smarkm#define S5P_CEC_RX_BUFF11 (0x012C) 64109998Smarkm#define S5P_CEC_RX_BUFF12 (0x0130) 65109998Smarkm#define S5P_CEC_RX_BUFF13 (0x0134) 66109998Smarkm#define S5P_CEC_RX_BUFF14 (0x0138) 67109998Smarkm#define S5P_CEC_RX_BUFF15 (0x013C) 68238405Sjkim 69280297Sjkim#define S5P_CEC_RX_FILTER_CTRL (0x0180) 70238405Sjkim#define S5P_CEC_RX_FILTER_TH (0x0184) 71290207Sjkim 72290207Sjkim/* 73290207Sjkim * Bit definition part 74238405Sjkim */ 75109998Smarkm#define S5P_CEC_IRQ_TX_DONE (1<<0) 76238405Sjkim#define S5P_CEC_IRQ_TX_ERROR (1<<1) 77109998Smarkm#define S5P_CEC_IRQ_RX_DONE (1<<4) 78280297Sjkim#define S5P_CEC_IRQ_RX_ERROR (1<<5) 79280297Sjkim 80280297Sjkim#define S5P_CEC_TX_CTRL_START (1<<0) 81280297Sjkim#define S5P_CEC_TX_CTRL_BCAST (1<<1) 82280297Sjkim#define S5P_CEC_TX_CTRL_RETRY (0x04<<4) 83280297Sjkim#define S5P_CEC_TX_CTRL_RESET (1<<7) 84280297Sjkim 85280297Sjkim#define S5P_CEC_RX_CTRL_ENABLE (1<<0) 86280297Sjkim#define S5P_CEC_RX_CTRL_RESET (1<<7) 87109998Smarkm 88280297Sjkim#define S5P_CEC_LOGIC_ADDR_MASK (0xF) 89280297Sjkim 90280297Sjkim/* PMU Registers for PHY */ 91109998Smarkm#define EXYNOS_HDMI_PHY_CONTROL 0x700 92280297Sjkim 93280297Sjkim#endif /* __EXYNOS_REGS__H */ 94280297Sjkim