1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7#include <linux/device.h> 8#include <linux/interconnect.h> 9#include <linux/interconnect-provider.h> 10#include <linux/mod_devicetable.h> 11#include <linux/module.h> 12#include <linux/platform_device.h> 13#include <dt-bindings/interconnect/qcom,sm8150.h> 14 15#include "bcm-voter.h" 16#include "icc-rpmh.h" 17#include "sm8150.h" 18 19static struct qcom_icc_node qhm_a1noc_cfg = { 20 .name = "qhm_a1noc_cfg", 21 .id = SM8150_MASTER_A1NOC_CFG, 22 .channels = 1, 23 .buswidth = 4, 24 .num_links = 1, 25 .links = { SM8150_SLAVE_SERVICE_A1NOC }, 26}; 27 28static struct qcom_icc_node qhm_qup0 = { 29 .name = "qhm_qup0", 30 .id = SM8150_MASTER_QUP_0, 31 .channels = 1, 32 .buswidth = 4, 33 .num_links = 1, 34 .links = { SM8150_A1NOC_SNOC_SLV }, 35}; 36 37static struct qcom_icc_node xm_emac = { 38 .name = "xm_emac", 39 .id = SM8150_MASTER_EMAC, 40 .channels = 1, 41 .buswidth = 8, 42 .num_links = 1, 43 .links = { SM8150_A1NOC_SNOC_SLV }, 44}; 45 46static struct qcom_icc_node xm_ufs_mem = { 47 .name = "xm_ufs_mem", 48 .id = SM8150_MASTER_UFS_MEM, 49 .channels = 1, 50 .buswidth = 8, 51 .num_links = 1, 52 .links = { SM8150_A1NOC_SNOC_SLV }, 53}; 54 55static struct qcom_icc_node xm_usb3_0 = { 56 .name = "xm_usb3_0", 57 .id = SM8150_MASTER_USB3, 58 .channels = 1, 59 .buswidth = 8, 60 .num_links = 1, 61 .links = { SM8150_A1NOC_SNOC_SLV }, 62}; 63 64static struct qcom_icc_node xm_usb3_1 = { 65 .name = "xm_usb3_1", 66 .id = SM8150_MASTER_USB3_1, 67 .channels = 1, 68 .buswidth = 8, 69 .num_links = 1, 70 .links = { SM8150_A1NOC_SNOC_SLV }, 71}; 72 73static struct qcom_icc_node qhm_a2noc_cfg = { 74 .name = "qhm_a2noc_cfg", 75 .id = SM8150_MASTER_A2NOC_CFG, 76 .channels = 1, 77 .buswidth = 4, 78 .num_links = 1, 79 .links = { SM8150_SLAVE_SERVICE_A2NOC }, 80}; 81 82static struct qcom_icc_node qhm_qdss_bam = { 83 .name = "qhm_qdss_bam", 84 .id = SM8150_MASTER_QDSS_BAM, 85 .channels = 1, 86 .buswidth = 4, 87 .num_links = 1, 88 .links = { SM8150_A2NOC_SNOC_SLV }, 89}; 90 91static struct qcom_icc_node qhm_qspi = { 92 .name = "qhm_qspi", 93 .id = SM8150_MASTER_QSPI, 94 .channels = 1, 95 .buswidth = 4, 96 .num_links = 1, 97 .links = { SM8150_A2NOC_SNOC_SLV }, 98}; 99 100static struct qcom_icc_node qhm_qup1 = { 101 .name = "qhm_qup1", 102 .id = SM8150_MASTER_QUP_1, 103 .channels = 1, 104 .buswidth = 4, 105 .num_links = 1, 106 .links = { SM8150_A2NOC_SNOC_SLV }, 107}; 108 109static struct qcom_icc_node qhm_qup2 = { 110 .name = "qhm_qup2", 111 .id = SM8150_MASTER_QUP_2, 112 .channels = 1, 113 .buswidth = 4, 114 .num_links = 1, 115 .links = { SM8150_A2NOC_SNOC_SLV }, 116}; 117 118static struct qcom_icc_node qhm_sensorss_ahb = { 119 .name = "qhm_sensorss_ahb", 120 .id = SM8150_MASTER_SENSORS_AHB, 121 .channels = 1, 122 .buswidth = 4, 123 .num_links = 1, 124 .links = { SM8150_A2NOC_SNOC_SLV }, 125}; 126 127static struct qcom_icc_node qhm_tsif = { 128 .name = "qhm_tsif", 129 .id = SM8150_MASTER_TSIF, 130 .channels = 1, 131 .buswidth = 4, 132 .num_links = 1, 133 .links = { SM8150_A2NOC_SNOC_SLV }, 134}; 135 136static struct qcom_icc_node qnm_cnoc = { 137 .name = "qnm_cnoc", 138 .id = SM8150_MASTER_CNOC_A2NOC, 139 .channels = 1, 140 .buswidth = 8, 141 .num_links = 1, 142 .links = { SM8150_A2NOC_SNOC_SLV }, 143}; 144 145static struct qcom_icc_node qxm_crypto = { 146 .name = "qxm_crypto", 147 .id = SM8150_MASTER_CRYPTO_CORE_0, 148 .channels = 1, 149 .buswidth = 8, 150 .num_links = 1, 151 .links = { SM8150_A2NOC_SNOC_SLV }, 152}; 153 154static struct qcom_icc_node qxm_ipa = { 155 .name = "qxm_ipa", 156 .id = SM8150_MASTER_IPA, 157 .channels = 1, 158 .buswidth = 8, 159 .num_links = 1, 160 .links = { SM8150_A2NOC_SNOC_SLV }, 161}; 162 163static struct qcom_icc_node xm_pcie3_0 = { 164 .name = "xm_pcie3_0", 165 .id = SM8150_MASTER_PCIE, 166 .channels = 1, 167 .buswidth = 8, 168 .num_links = 1, 169 .links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, 170}; 171 172static struct qcom_icc_node xm_pcie3_1 = { 173 .name = "xm_pcie3_1", 174 .id = SM8150_MASTER_PCIE_1, 175 .channels = 1, 176 .buswidth = 8, 177 .num_links = 1, 178 .links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, 179}; 180 181static struct qcom_icc_node xm_qdss_etr = { 182 .name = "xm_qdss_etr", 183 .id = SM8150_MASTER_QDSS_ETR, 184 .channels = 1, 185 .buswidth = 8, 186 .num_links = 1, 187 .links = { SM8150_A2NOC_SNOC_SLV }, 188}; 189 190static struct qcom_icc_node xm_sdc2 = { 191 .name = "xm_sdc2", 192 .id = SM8150_MASTER_SDCC_2, 193 .channels = 1, 194 .buswidth = 8, 195 .num_links = 1, 196 .links = { SM8150_A2NOC_SNOC_SLV }, 197}; 198 199static struct qcom_icc_node xm_sdc4 = { 200 .name = "xm_sdc4", 201 .id = SM8150_MASTER_SDCC_4, 202 .channels = 1, 203 .buswidth = 8, 204 .num_links = 1, 205 .links = { SM8150_A2NOC_SNOC_SLV }, 206}; 207 208static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 209 .name = "qxm_camnoc_hf0_uncomp", 210 .id = SM8150_MASTER_CAMNOC_HF0_UNCOMP, 211 .channels = 1, 212 .buswidth = 32, 213 .num_links = 1, 214 .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, 215}; 216 217static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { 218 .name = "qxm_camnoc_hf1_uncomp", 219 .id = SM8150_MASTER_CAMNOC_HF1_UNCOMP, 220 .channels = 1, 221 .buswidth = 32, 222 .num_links = 1, 223 .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, 224}; 225 226static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 227 .name = "qxm_camnoc_sf_uncomp", 228 .id = SM8150_MASTER_CAMNOC_SF_UNCOMP, 229 .channels = 1, 230 .buswidth = 32, 231 .num_links = 1, 232 .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, 233}; 234 235static struct qcom_icc_node qnm_npu = { 236 .name = "qnm_npu", 237 .id = SM8150_MASTER_NPU, 238 .channels = 1, 239 .buswidth = 32, 240 .num_links = 1, 241 .links = { SM8150_SLAVE_CDSP_MEM_NOC }, 242}; 243 244static struct qcom_icc_node qhm_spdm = { 245 .name = "qhm_spdm", 246 .id = SM8150_MASTER_SPDM, 247 .channels = 1, 248 .buswidth = 4, 249 .num_links = 1, 250 .links = { SM8150_SLAVE_CNOC_A2NOC }, 251}; 252 253static struct qcom_icc_node qnm_snoc = { 254 .name = "qnm_snoc", 255 .id = SM8150_SNOC_CNOC_MAS, 256 .channels = 1, 257 .buswidth = 8, 258 .num_links = 50, 259 .links = { SM8150_SLAVE_TLMM_SOUTH, 260 SM8150_SLAVE_CDSP_CFG, 261 SM8150_SLAVE_SPSS_CFG, 262 SM8150_SLAVE_CAMERA_CFG, 263 SM8150_SLAVE_SDCC_4, 264 SM8150_SLAVE_SDCC_2, 265 SM8150_SLAVE_CNOC_MNOC_CFG, 266 SM8150_SLAVE_EMAC_CFG, 267 SM8150_SLAVE_UFS_MEM_CFG, 268 SM8150_SLAVE_TLMM_EAST, 269 SM8150_SLAVE_SSC_CFG, 270 SM8150_SLAVE_SNOC_CFG, 271 SM8150_SLAVE_NORTH_PHY_CFG, 272 SM8150_SLAVE_QUP_0, 273 SM8150_SLAVE_GLM, 274 SM8150_SLAVE_PCIE_1_CFG, 275 SM8150_SLAVE_A2NOC_CFG, 276 SM8150_SLAVE_QDSS_CFG, 277 SM8150_SLAVE_DISPLAY_CFG, 278 SM8150_SLAVE_TCSR, 279 SM8150_SLAVE_CNOC_DDRSS, 280 SM8150_SLAVE_RBCPR_MMCX_CFG, 281 SM8150_SLAVE_NPU_CFG, 282 SM8150_SLAVE_PCIE_0_CFG, 283 SM8150_SLAVE_GRAPHICS_3D_CFG, 284 SM8150_SLAVE_VENUS_CFG, 285 SM8150_SLAVE_TSIF, 286 SM8150_SLAVE_IPA_CFG, 287 SM8150_SLAVE_CLK_CTL, 288 SM8150_SLAVE_AOP, 289 SM8150_SLAVE_QUP_1, 290 SM8150_SLAVE_AHB2PHY_SOUTH, 291 SM8150_SLAVE_USB3_1, 292 SM8150_SLAVE_SERVICE_CNOC, 293 SM8150_SLAVE_UFS_CARD_CFG, 294 SM8150_SLAVE_QUP_2, 295 SM8150_SLAVE_RBCPR_CX_CFG, 296 SM8150_SLAVE_TLMM_WEST, 297 SM8150_SLAVE_A1NOC_CFG, 298 SM8150_SLAVE_AOSS, 299 SM8150_SLAVE_PRNG, 300 SM8150_SLAVE_VSENSE_CTRL_CFG, 301 SM8150_SLAVE_QSPI, 302 SM8150_SLAVE_USB3, 303 SM8150_SLAVE_SPDM_WRAPPER, 304 SM8150_SLAVE_CRYPTO_0_CFG, 305 SM8150_SLAVE_PIMEM_CFG, 306 SM8150_SLAVE_TLMM_NORTH, 307 SM8150_SLAVE_RBCPR_MX_CFG, 308 SM8150_SLAVE_IMEM_CFG 309 }, 310}; 311 312static struct qcom_icc_node xm_qdss_dap = { 313 .name = "xm_qdss_dap", 314 .id = SM8150_MASTER_QDSS_DAP, 315 .channels = 1, 316 .buswidth = 8, 317 .num_links = 51, 318 .links = { SM8150_SLAVE_TLMM_SOUTH, 319 SM8150_SLAVE_CDSP_CFG, 320 SM8150_SLAVE_SPSS_CFG, 321 SM8150_SLAVE_CAMERA_CFG, 322 SM8150_SLAVE_SDCC_4, 323 SM8150_SLAVE_SDCC_2, 324 SM8150_SLAVE_CNOC_MNOC_CFG, 325 SM8150_SLAVE_EMAC_CFG, 326 SM8150_SLAVE_UFS_MEM_CFG, 327 SM8150_SLAVE_TLMM_EAST, 328 SM8150_SLAVE_SSC_CFG, 329 SM8150_SLAVE_SNOC_CFG, 330 SM8150_SLAVE_NORTH_PHY_CFG, 331 SM8150_SLAVE_QUP_0, 332 SM8150_SLAVE_GLM, 333 SM8150_SLAVE_PCIE_1_CFG, 334 SM8150_SLAVE_A2NOC_CFG, 335 SM8150_SLAVE_QDSS_CFG, 336 SM8150_SLAVE_DISPLAY_CFG, 337 SM8150_SLAVE_TCSR, 338 SM8150_SLAVE_CNOC_DDRSS, 339 SM8150_SLAVE_CNOC_A2NOC, 340 SM8150_SLAVE_RBCPR_MMCX_CFG, 341 SM8150_SLAVE_NPU_CFG, 342 SM8150_SLAVE_PCIE_0_CFG, 343 SM8150_SLAVE_GRAPHICS_3D_CFG, 344 SM8150_SLAVE_VENUS_CFG, 345 SM8150_SLAVE_TSIF, 346 SM8150_SLAVE_IPA_CFG, 347 SM8150_SLAVE_CLK_CTL, 348 SM8150_SLAVE_AOP, 349 SM8150_SLAVE_QUP_1, 350 SM8150_SLAVE_AHB2PHY_SOUTH, 351 SM8150_SLAVE_USB3_1, 352 SM8150_SLAVE_SERVICE_CNOC, 353 SM8150_SLAVE_UFS_CARD_CFG, 354 SM8150_SLAVE_QUP_2, 355 SM8150_SLAVE_RBCPR_CX_CFG, 356 SM8150_SLAVE_TLMM_WEST, 357 SM8150_SLAVE_A1NOC_CFG, 358 SM8150_SLAVE_AOSS, 359 SM8150_SLAVE_PRNG, 360 SM8150_SLAVE_VSENSE_CTRL_CFG, 361 SM8150_SLAVE_QSPI, 362 SM8150_SLAVE_USB3, 363 SM8150_SLAVE_SPDM_WRAPPER, 364 SM8150_SLAVE_CRYPTO_0_CFG, 365 SM8150_SLAVE_PIMEM_CFG, 366 SM8150_SLAVE_TLMM_NORTH, 367 SM8150_SLAVE_RBCPR_MX_CFG, 368 SM8150_SLAVE_IMEM_CFG 369 }, 370}; 371 372static struct qcom_icc_node qhm_cnoc_dc_noc = { 373 .name = "qhm_cnoc_dc_noc", 374 .id = SM8150_MASTER_CNOC_DC_NOC, 375 .channels = 1, 376 .buswidth = 4, 377 .num_links = 2, 378 .links = { SM8150_SLAVE_GEM_NOC_CFG, 379 SM8150_SLAVE_LLCC_CFG 380 }, 381}; 382 383static struct qcom_icc_node acm_apps = { 384 .name = "acm_apps", 385 .id = SM8150_MASTER_AMPSS_M0, 386 .channels = 2, 387 .buswidth = 32, 388 .num_links = 3, 389 .links = { SM8150_SLAVE_ECC, 390 SM8150_SLAVE_LLCC, 391 SM8150_SLAVE_GEM_NOC_SNOC 392 }, 393}; 394 395static struct qcom_icc_node acm_gpu_tcu = { 396 .name = "acm_gpu_tcu", 397 .id = SM8150_MASTER_GPU_TCU, 398 .channels = 1, 399 .buswidth = 8, 400 .num_links = 2, 401 .links = { SM8150_SLAVE_LLCC, 402 SM8150_SLAVE_GEM_NOC_SNOC 403 }, 404}; 405 406static struct qcom_icc_node acm_sys_tcu = { 407 .name = "acm_sys_tcu", 408 .id = SM8150_MASTER_SYS_TCU, 409 .channels = 1, 410 .buswidth = 8, 411 .num_links = 2, 412 .links = { SM8150_SLAVE_LLCC, 413 SM8150_SLAVE_GEM_NOC_SNOC 414 }, 415}; 416 417static struct qcom_icc_node qhm_gemnoc_cfg = { 418 .name = "qhm_gemnoc_cfg", 419 .id = SM8150_MASTER_GEM_NOC_CFG, 420 .channels = 1, 421 .buswidth = 4, 422 .num_links = 2, 423 .links = { SM8150_SLAVE_SERVICE_GEM_NOC, 424 SM8150_SLAVE_MSS_PROC_MS_MPU_CFG 425 }, 426}; 427 428static struct qcom_icc_node qnm_cmpnoc = { 429 .name = "qnm_cmpnoc", 430 .id = SM8150_MASTER_COMPUTE_NOC, 431 .channels = 2, 432 .buswidth = 32, 433 .num_links = 3, 434 .links = { SM8150_SLAVE_ECC, 435 SM8150_SLAVE_LLCC, 436 SM8150_SLAVE_GEM_NOC_SNOC 437 }, 438}; 439 440static struct qcom_icc_node qnm_gpu = { 441 .name = "qnm_gpu", 442 .id = SM8150_MASTER_GRAPHICS_3D, 443 .channels = 2, 444 .buswidth = 32, 445 .num_links = 2, 446 .links = { SM8150_SLAVE_LLCC, 447 SM8150_SLAVE_GEM_NOC_SNOC 448 }, 449}; 450 451static struct qcom_icc_node qnm_mnoc_hf = { 452 .name = "qnm_mnoc_hf", 453 .id = SM8150_MASTER_MNOC_HF_MEM_NOC, 454 .channels = 2, 455 .buswidth = 32, 456 .num_links = 1, 457 .links = { SM8150_SLAVE_LLCC }, 458}; 459 460static struct qcom_icc_node qnm_mnoc_sf = { 461 .name = "qnm_mnoc_sf", 462 .id = SM8150_MASTER_MNOC_SF_MEM_NOC, 463 .channels = 1, 464 .buswidth = 32, 465 .num_links = 2, 466 .links = { SM8150_SLAVE_LLCC, 467 SM8150_SLAVE_GEM_NOC_SNOC 468 }, 469}; 470 471static struct qcom_icc_node qnm_pcie = { 472 .name = "qnm_pcie", 473 .id = SM8150_MASTER_GEM_NOC_PCIE_SNOC, 474 .channels = 1, 475 .buswidth = 16, 476 .num_links = 2, 477 .links = { SM8150_SLAVE_LLCC, 478 SM8150_SLAVE_GEM_NOC_SNOC 479 }, 480}; 481 482static struct qcom_icc_node qnm_snoc_gc = { 483 .name = "qnm_snoc_gc", 484 .id = SM8150_MASTER_SNOC_GC_MEM_NOC, 485 .channels = 1, 486 .buswidth = 8, 487 .num_links = 1, 488 .links = { SM8150_SLAVE_LLCC }, 489}; 490 491static struct qcom_icc_node qnm_snoc_sf = { 492 .name = "qnm_snoc_sf", 493 .id = SM8150_MASTER_SNOC_SF_MEM_NOC, 494 .channels = 1, 495 .buswidth = 16, 496 .num_links = 1, 497 .links = { SM8150_SLAVE_LLCC }, 498}; 499 500static struct qcom_icc_node qxm_ecc = { 501 .name = "qxm_ecc", 502 .id = SM8150_MASTER_ECC, 503 .channels = 2, 504 .buswidth = 32, 505 .num_links = 1, 506 .links = { SM8150_SLAVE_LLCC }, 507}; 508 509static struct qcom_icc_node llcc_mc = { 510 .name = "llcc_mc", 511 .id = SM8150_MASTER_LLCC, 512 .channels = 4, 513 .buswidth = 4, 514 .num_links = 1, 515 .links = { SM8150_SLAVE_EBI_CH0 }, 516}; 517 518static struct qcom_icc_node qhm_mnoc_cfg = { 519 .name = "qhm_mnoc_cfg", 520 .id = SM8150_MASTER_CNOC_MNOC_CFG, 521 .channels = 1, 522 .buswidth = 4, 523 .num_links = 1, 524 .links = { SM8150_SLAVE_SERVICE_MNOC }, 525}; 526 527static struct qcom_icc_node qxm_camnoc_hf0 = { 528 .name = "qxm_camnoc_hf0", 529 .id = SM8150_MASTER_CAMNOC_HF0, 530 .channels = 1, 531 .buswidth = 32, 532 .num_links = 1, 533 .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, 534}; 535 536static struct qcom_icc_node qxm_camnoc_hf1 = { 537 .name = "qxm_camnoc_hf1", 538 .id = SM8150_MASTER_CAMNOC_HF1, 539 .channels = 1, 540 .buswidth = 32, 541 .num_links = 1, 542 .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, 543}; 544 545static struct qcom_icc_node qxm_camnoc_sf = { 546 .name = "qxm_camnoc_sf", 547 .id = SM8150_MASTER_CAMNOC_SF, 548 .channels = 1, 549 .buswidth = 32, 550 .num_links = 1, 551 .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, 552}; 553 554static struct qcom_icc_node qxm_mdp0 = { 555 .name = "qxm_mdp0", 556 .id = SM8150_MASTER_MDP_PORT0, 557 .channels = 1, 558 .buswidth = 32, 559 .num_links = 1, 560 .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, 561}; 562 563static struct qcom_icc_node qxm_mdp1 = { 564 .name = "qxm_mdp1", 565 .id = SM8150_MASTER_MDP_PORT1, 566 .channels = 1, 567 .buswidth = 32, 568 .num_links = 1, 569 .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, 570}; 571 572static struct qcom_icc_node qxm_rot = { 573 .name = "qxm_rot", 574 .id = SM8150_MASTER_ROTATOR, 575 .channels = 1, 576 .buswidth = 32, 577 .num_links = 1, 578 .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, 579}; 580 581static struct qcom_icc_node qxm_venus0 = { 582 .name = "qxm_venus0", 583 .id = SM8150_MASTER_VIDEO_P0, 584 .channels = 1, 585 .buswidth = 32, 586 .num_links = 1, 587 .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, 588}; 589 590static struct qcom_icc_node qxm_venus1 = { 591 .name = "qxm_venus1", 592 .id = SM8150_MASTER_VIDEO_P1, 593 .channels = 1, 594 .buswidth = 32, 595 .num_links = 1, 596 .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, 597}; 598 599static struct qcom_icc_node qxm_venus_arm9 = { 600 .name = "qxm_venus_arm9", 601 .id = SM8150_MASTER_VIDEO_PROC, 602 .channels = 1, 603 .buswidth = 8, 604 .num_links = 1, 605 .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, 606}; 607 608static struct qcom_icc_node qhm_snoc_cfg = { 609 .name = "qhm_snoc_cfg", 610 .id = SM8150_MASTER_SNOC_CFG, 611 .channels = 1, 612 .buswidth = 4, 613 .num_links = 1, 614 .links = { SM8150_SLAVE_SERVICE_SNOC }, 615}; 616 617static struct qcom_icc_node qnm_aggre1_noc = { 618 .name = "qnm_aggre1_noc", 619 .id = SM8150_A1NOC_SNOC_MAS, 620 .channels = 1, 621 .buswidth = 16, 622 .num_links = 6, 623 .links = { SM8150_SLAVE_SNOC_GEM_NOC_SF, 624 SM8150_SLAVE_PIMEM, 625 SM8150_SLAVE_OCIMEM, 626 SM8150_SLAVE_APPSS, 627 SM8150_SNOC_CNOC_SLV, 628 SM8150_SLAVE_QDSS_STM 629 }, 630}; 631 632static struct qcom_icc_node qnm_aggre2_noc = { 633 .name = "qnm_aggre2_noc", 634 .id = SM8150_A2NOC_SNOC_MAS, 635 .channels = 1, 636 .buswidth = 16, 637 .num_links = 9, 638 .links = { SM8150_SLAVE_SNOC_GEM_NOC_SF, 639 SM8150_SLAVE_PIMEM, 640 SM8150_SLAVE_OCIMEM, 641 SM8150_SLAVE_APPSS, 642 SM8150_SNOC_CNOC_SLV, 643 SM8150_SLAVE_PCIE_0, 644 SM8150_SLAVE_PCIE_1, 645 SM8150_SLAVE_TCU, 646 SM8150_SLAVE_QDSS_STM 647 }, 648}; 649 650static struct qcom_icc_node qnm_gemnoc = { 651 .name = "qnm_gemnoc", 652 .id = SM8150_MASTER_GEM_NOC_SNOC, 653 .channels = 1, 654 .buswidth = 8, 655 .num_links = 6, 656 .links = { SM8150_SLAVE_PIMEM, 657 SM8150_SLAVE_OCIMEM, 658 SM8150_SLAVE_APPSS, 659 SM8150_SNOC_CNOC_SLV, 660 SM8150_SLAVE_TCU, 661 SM8150_SLAVE_QDSS_STM 662 }, 663}; 664 665static struct qcom_icc_node qxm_pimem = { 666 .name = "qxm_pimem", 667 .id = SM8150_MASTER_PIMEM, 668 .channels = 1, 669 .buswidth = 8, 670 .num_links = 2, 671 .links = { SM8150_SLAVE_SNOC_GEM_NOC_GC, 672 SM8150_SLAVE_OCIMEM 673 }, 674}; 675 676static struct qcom_icc_node xm_gic = { 677 .name = "xm_gic", 678 .id = SM8150_MASTER_GIC, 679 .channels = 1, 680 .buswidth = 8, 681 .num_links = 2, 682 .links = { SM8150_SLAVE_SNOC_GEM_NOC_GC, 683 SM8150_SLAVE_OCIMEM 684 }, 685}; 686 687static struct qcom_icc_node qns_a1noc_snoc = { 688 .name = "qns_a1noc_snoc", 689 .id = SM8150_A1NOC_SNOC_SLV, 690 .channels = 1, 691 .buswidth = 16, 692 .num_links = 1, 693 .links = { SM8150_A1NOC_SNOC_MAS }, 694}; 695 696static struct qcom_icc_node srvc_aggre1_noc = { 697 .name = "srvc_aggre1_noc", 698 .id = SM8150_SLAVE_SERVICE_A1NOC, 699 .channels = 1, 700 .buswidth = 4, 701}; 702 703static struct qcom_icc_node qns_a2noc_snoc = { 704 .name = "qns_a2noc_snoc", 705 .id = SM8150_A2NOC_SNOC_SLV, 706 .channels = 1, 707 .buswidth = 16, 708 .num_links = 1, 709 .links = { SM8150_A2NOC_SNOC_MAS }, 710}; 711 712static struct qcom_icc_node qns_pcie_mem_noc = { 713 .name = "qns_pcie_mem_noc", 714 .id = SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 715 .channels = 1, 716 .buswidth = 16, 717 .num_links = 1, 718 .links = { SM8150_MASTER_GEM_NOC_PCIE_SNOC }, 719}; 720 721static struct qcom_icc_node srvc_aggre2_noc = { 722 .name = "srvc_aggre2_noc", 723 .id = SM8150_SLAVE_SERVICE_A2NOC, 724 .channels = 1, 725 .buswidth = 4, 726}; 727 728static struct qcom_icc_node qns_camnoc_uncomp = { 729 .name = "qns_camnoc_uncomp", 730 .id = SM8150_SLAVE_CAMNOC_UNCOMP, 731 .channels = 1, 732 .buswidth = 32, 733}; 734 735static struct qcom_icc_node qns_cdsp_mem_noc = { 736 .name = "qns_cdsp_mem_noc", 737 .id = SM8150_SLAVE_CDSP_MEM_NOC, 738 .channels = 2, 739 .buswidth = 32, 740 .num_links = 1, 741 .links = { SM8150_MASTER_COMPUTE_NOC }, 742}; 743 744static struct qcom_icc_node qhs_a1_noc_cfg = { 745 .name = "qhs_a1_noc_cfg", 746 .id = SM8150_SLAVE_A1NOC_CFG, 747 .channels = 1, 748 .buswidth = 4, 749 .num_links = 1, 750 .links = { SM8150_MASTER_A1NOC_CFG }, 751}; 752 753static struct qcom_icc_node qhs_a2_noc_cfg = { 754 .name = "qhs_a2_noc_cfg", 755 .id = SM8150_SLAVE_A2NOC_CFG, 756 .channels = 1, 757 .buswidth = 4, 758 .num_links = 1, 759 .links = { SM8150_MASTER_A2NOC_CFG }, 760}; 761 762static struct qcom_icc_node qhs_ahb2phy_south = { 763 .name = "qhs_ahb2phy_south", 764 .id = SM8150_SLAVE_AHB2PHY_SOUTH, 765 .channels = 1, 766 .buswidth = 4, 767}; 768 769static struct qcom_icc_node qhs_aop = { 770 .name = "qhs_aop", 771 .id = SM8150_SLAVE_AOP, 772 .channels = 1, 773 .buswidth = 4, 774}; 775 776static struct qcom_icc_node qhs_aoss = { 777 .name = "qhs_aoss", 778 .id = SM8150_SLAVE_AOSS, 779 .channels = 1, 780 .buswidth = 4, 781}; 782 783static struct qcom_icc_node qhs_camera_cfg = { 784 .name = "qhs_camera_cfg", 785 .id = SM8150_SLAVE_CAMERA_CFG, 786 .channels = 1, 787 .buswidth = 4, 788}; 789 790static struct qcom_icc_node qhs_clk_ctl = { 791 .name = "qhs_clk_ctl", 792 .id = SM8150_SLAVE_CLK_CTL, 793 .channels = 1, 794 .buswidth = 4, 795}; 796 797static struct qcom_icc_node qhs_compute_dsp = { 798 .name = "qhs_compute_dsp", 799 .id = SM8150_SLAVE_CDSP_CFG, 800 .channels = 1, 801 .buswidth = 4, 802}; 803 804static struct qcom_icc_node qhs_cpr_cx = { 805 .name = "qhs_cpr_cx", 806 .id = SM8150_SLAVE_RBCPR_CX_CFG, 807 .channels = 1, 808 .buswidth = 4, 809}; 810 811static struct qcom_icc_node qhs_cpr_mmcx = { 812 .name = "qhs_cpr_mmcx", 813 .id = SM8150_SLAVE_RBCPR_MMCX_CFG, 814 .channels = 1, 815 .buswidth = 4, 816}; 817 818static struct qcom_icc_node qhs_cpr_mx = { 819 .name = "qhs_cpr_mx", 820 .id = SM8150_SLAVE_RBCPR_MX_CFG, 821 .channels = 1, 822 .buswidth = 4, 823}; 824 825static struct qcom_icc_node qhs_crypto0_cfg = { 826 .name = "qhs_crypto0_cfg", 827 .id = SM8150_SLAVE_CRYPTO_0_CFG, 828 .channels = 1, 829 .buswidth = 4, 830}; 831 832static struct qcom_icc_node qhs_ddrss_cfg = { 833 .name = "qhs_ddrss_cfg", 834 .id = SM8150_SLAVE_CNOC_DDRSS, 835 .channels = 1, 836 .buswidth = 4, 837 .num_links = 1, 838 .links = { SM8150_MASTER_CNOC_DC_NOC }, 839}; 840 841static struct qcom_icc_node qhs_display_cfg = { 842 .name = "qhs_display_cfg", 843 .id = SM8150_SLAVE_DISPLAY_CFG, 844 .channels = 1, 845 .buswidth = 4, 846}; 847 848static struct qcom_icc_node qhs_emac_cfg = { 849 .name = "qhs_emac_cfg", 850 .id = SM8150_SLAVE_EMAC_CFG, 851 .channels = 1, 852 .buswidth = 4, 853}; 854 855static struct qcom_icc_node qhs_glm = { 856 .name = "qhs_glm", 857 .id = SM8150_SLAVE_GLM, 858 .channels = 1, 859 .buswidth = 4, 860}; 861 862static struct qcom_icc_node qhs_gpuss_cfg = { 863 .name = "qhs_gpuss_cfg", 864 .id = SM8150_SLAVE_GRAPHICS_3D_CFG, 865 .channels = 1, 866 .buswidth = 8, 867}; 868 869static struct qcom_icc_node qhs_imem_cfg = { 870 .name = "qhs_imem_cfg", 871 .id = SM8150_SLAVE_IMEM_CFG, 872 .channels = 1, 873 .buswidth = 4, 874}; 875 876static struct qcom_icc_node qhs_ipa = { 877 .name = "qhs_ipa", 878 .id = SM8150_SLAVE_IPA_CFG, 879 .channels = 1, 880 .buswidth = 4, 881}; 882 883static struct qcom_icc_node qhs_mnoc_cfg = { 884 .name = "qhs_mnoc_cfg", 885 .id = SM8150_SLAVE_CNOC_MNOC_CFG, 886 .channels = 1, 887 .buswidth = 4, 888 .num_links = 1, 889 .links = { SM8150_MASTER_CNOC_MNOC_CFG }, 890}; 891 892static struct qcom_icc_node qhs_npu_cfg = { 893 .name = "qhs_npu_cfg", 894 .id = SM8150_SLAVE_NPU_CFG, 895 .channels = 1, 896 .buswidth = 4, 897}; 898 899static struct qcom_icc_node qhs_pcie0_cfg = { 900 .name = "qhs_pcie0_cfg", 901 .id = SM8150_SLAVE_PCIE_0_CFG, 902 .channels = 1, 903 .buswidth = 4, 904}; 905 906static struct qcom_icc_node qhs_pcie1_cfg = { 907 .name = "qhs_pcie1_cfg", 908 .id = SM8150_SLAVE_PCIE_1_CFG, 909 .channels = 1, 910 .buswidth = 4, 911}; 912 913static struct qcom_icc_node qhs_phy_refgen_north = { 914 .name = "qhs_phy_refgen_north", 915 .id = SM8150_SLAVE_NORTH_PHY_CFG, 916 .channels = 1, 917 .buswidth = 4, 918}; 919 920static struct qcom_icc_node qhs_pimem_cfg = { 921 .name = "qhs_pimem_cfg", 922 .id = SM8150_SLAVE_PIMEM_CFG, 923 .channels = 1, 924 .buswidth = 4, 925}; 926 927static struct qcom_icc_node qhs_prng = { 928 .name = "qhs_prng", 929 .id = SM8150_SLAVE_PRNG, 930 .channels = 1, 931 .buswidth = 4, 932}; 933 934static struct qcom_icc_node qhs_qdss_cfg = { 935 .name = "qhs_qdss_cfg", 936 .id = SM8150_SLAVE_QDSS_CFG, 937 .channels = 1, 938 .buswidth = 4, 939}; 940 941static struct qcom_icc_node qhs_qspi = { 942 .name = "qhs_qspi", 943 .id = SM8150_SLAVE_QSPI, 944 .channels = 1, 945 .buswidth = 4, 946}; 947 948static struct qcom_icc_node qhs_qupv3_east = { 949 .name = "qhs_qupv3_east", 950 .id = SM8150_SLAVE_QUP_2, 951 .channels = 1, 952 .buswidth = 4, 953}; 954 955static struct qcom_icc_node qhs_qupv3_north = { 956 .name = "qhs_qupv3_north", 957 .id = SM8150_SLAVE_QUP_1, 958 .channels = 1, 959 .buswidth = 4, 960}; 961 962static struct qcom_icc_node qhs_qupv3_south = { 963 .name = "qhs_qupv3_south", 964 .id = SM8150_SLAVE_QUP_0, 965 .channels = 1, 966 .buswidth = 4, 967}; 968 969static struct qcom_icc_node qhs_sdc2 = { 970 .name = "qhs_sdc2", 971 .id = SM8150_SLAVE_SDCC_2, 972 .channels = 1, 973 .buswidth = 4, 974}; 975 976static struct qcom_icc_node qhs_sdc4 = { 977 .name = "qhs_sdc4", 978 .id = SM8150_SLAVE_SDCC_4, 979 .channels = 1, 980 .buswidth = 4, 981}; 982 983static struct qcom_icc_node qhs_snoc_cfg = { 984 .name = "qhs_snoc_cfg", 985 .id = SM8150_SLAVE_SNOC_CFG, 986 .channels = 1, 987 .buswidth = 4, 988 .num_links = 1, 989 .links = { SM8150_MASTER_SNOC_CFG }, 990}; 991 992static struct qcom_icc_node qhs_spdm = { 993 .name = "qhs_spdm", 994 .id = SM8150_SLAVE_SPDM_WRAPPER, 995 .channels = 1, 996 .buswidth = 4, 997}; 998 999static struct qcom_icc_node qhs_spss_cfg = { 1000 .name = "qhs_spss_cfg", 1001 .id = SM8150_SLAVE_SPSS_CFG, 1002 .channels = 1, 1003 .buswidth = 4, 1004}; 1005 1006static struct qcom_icc_node qhs_ssc_cfg = { 1007 .name = "qhs_ssc_cfg", 1008 .id = SM8150_SLAVE_SSC_CFG, 1009 .channels = 1, 1010 .buswidth = 4, 1011}; 1012 1013static struct qcom_icc_node qhs_tcsr = { 1014 .name = "qhs_tcsr", 1015 .id = SM8150_SLAVE_TCSR, 1016 .channels = 1, 1017 .buswidth = 4, 1018}; 1019 1020static struct qcom_icc_node qhs_tlmm_east = { 1021 .name = "qhs_tlmm_east", 1022 .id = SM8150_SLAVE_TLMM_EAST, 1023 .channels = 1, 1024 .buswidth = 4, 1025}; 1026 1027static struct qcom_icc_node qhs_tlmm_north = { 1028 .name = "qhs_tlmm_north", 1029 .id = SM8150_SLAVE_TLMM_NORTH, 1030 .channels = 1, 1031 .buswidth = 4, 1032}; 1033 1034static struct qcom_icc_node qhs_tlmm_south = { 1035 .name = "qhs_tlmm_south", 1036 .id = SM8150_SLAVE_TLMM_SOUTH, 1037 .channels = 1, 1038 .buswidth = 4, 1039}; 1040 1041static struct qcom_icc_node qhs_tlmm_west = { 1042 .name = "qhs_tlmm_west", 1043 .id = SM8150_SLAVE_TLMM_WEST, 1044 .channels = 1, 1045 .buswidth = 4, 1046}; 1047 1048static struct qcom_icc_node qhs_tsif = { 1049 .name = "qhs_tsif", 1050 .id = SM8150_SLAVE_TSIF, 1051 .channels = 1, 1052 .buswidth = 4, 1053}; 1054 1055static struct qcom_icc_node qhs_ufs_card_cfg = { 1056 .name = "qhs_ufs_card_cfg", 1057 .id = SM8150_SLAVE_UFS_CARD_CFG, 1058 .channels = 1, 1059 .buswidth = 4, 1060}; 1061 1062static struct qcom_icc_node qhs_ufs_mem_cfg = { 1063 .name = "qhs_ufs_mem_cfg", 1064 .id = SM8150_SLAVE_UFS_MEM_CFG, 1065 .channels = 1, 1066 .buswidth = 4, 1067}; 1068 1069static struct qcom_icc_node qhs_usb3_0 = { 1070 .name = "qhs_usb3_0", 1071 .id = SM8150_SLAVE_USB3, 1072 .channels = 1, 1073 .buswidth = 4, 1074}; 1075 1076static struct qcom_icc_node qhs_usb3_1 = { 1077 .name = "qhs_usb3_1", 1078 .id = SM8150_SLAVE_USB3_1, 1079 .channels = 1, 1080 .buswidth = 4, 1081}; 1082 1083static struct qcom_icc_node qhs_venus_cfg = { 1084 .name = "qhs_venus_cfg", 1085 .id = SM8150_SLAVE_VENUS_CFG, 1086 .channels = 1, 1087 .buswidth = 4, 1088}; 1089 1090static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1091 .name = "qhs_vsense_ctrl_cfg", 1092 .id = SM8150_SLAVE_VSENSE_CTRL_CFG, 1093 .channels = 1, 1094 .buswidth = 4, 1095}; 1096 1097static struct qcom_icc_node qns_cnoc_a2noc = { 1098 .name = "qns_cnoc_a2noc", 1099 .id = SM8150_SLAVE_CNOC_A2NOC, 1100 .channels = 1, 1101 .buswidth = 8, 1102 .num_links = 1, 1103 .links = { SM8150_MASTER_CNOC_A2NOC }, 1104}; 1105 1106static struct qcom_icc_node srvc_cnoc = { 1107 .name = "srvc_cnoc", 1108 .id = SM8150_SLAVE_SERVICE_CNOC, 1109 .channels = 1, 1110 .buswidth = 4, 1111}; 1112 1113static struct qcom_icc_node qhs_llcc = { 1114 .name = "qhs_llcc", 1115 .id = SM8150_SLAVE_LLCC_CFG, 1116 .channels = 1, 1117 .buswidth = 4, 1118}; 1119 1120static struct qcom_icc_node qhs_memnoc = { 1121 .name = "qhs_memnoc", 1122 .id = SM8150_SLAVE_GEM_NOC_CFG, 1123 .channels = 1, 1124 .buswidth = 4, 1125 .num_links = 1, 1126 .links = { SM8150_MASTER_GEM_NOC_CFG }, 1127}; 1128 1129static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1130 .name = "qhs_mdsp_ms_mpu_cfg", 1131 .id = SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1132 .channels = 1, 1133 .buswidth = 4, 1134}; 1135 1136static struct qcom_icc_node qns_ecc = { 1137 .name = "qns_ecc", 1138 .id = SM8150_SLAVE_ECC, 1139 .channels = 1, 1140 .buswidth = 32, 1141}; 1142 1143static struct qcom_icc_node qns_gem_noc_snoc = { 1144 .name = "qns_gem_noc_snoc", 1145 .id = SM8150_SLAVE_GEM_NOC_SNOC, 1146 .channels = 1, 1147 .buswidth = 8, 1148 .num_links = 1, 1149 .links = { SM8150_MASTER_GEM_NOC_SNOC }, 1150}; 1151 1152static struct qcom_icc_node qns_llcc = { 1153 .name = "qns_llcc", 1154 .id = SM8150_SLAVE_LLCC, 1155 .channels = 4, 1156 .buswidth = 16, 1157 .num_links = 1, 1158 .links = { SM8150_MASTER_LLCC }, 1159}; 1160 1161static struct qcom_icc_node srvc_gemnoc = { 1162 .name = "srvc_gemnoc", 1163 .id = SM8150_SLAVE_SERVICE_GEM_NOC, 1164 .channels = 1, 1165 .buswidth = 4, 1166}; 1167 1168static struct qcom_icc_node ebi = { 1169 .name = "ebi", 1170 .id = SM8150_SLAVE_EBI_CH0, 1171 .channels = 4, 1172 .buswidth = 4, 1173}; 1174 1175static struct qcom_icc_node qns2_mem_noc = { 1176 .name = "qns2_mem_noc", 1177 .id = SM8150_SLAVE_MNOC_SF_MEM_NOC, 1178 .channels = 1, 1179 .buswidth = 32, 1180 .num_links = 1, 1181 .links = { SM8150_MASTER_MNOC_SF_MEM_NOC }, 1182}; 1183 1184static struct qcom_icc_node qns_mem_noc_hf = { 1185 .name = "qns_mem_noc_hf", 1186 .id = SM8150_SLAVE_MNOC_HF_MEM_NOC, 1187 .channels = 2, 1188 .buswidth = 32, 1189 .num_links = 1, 1190 .links = { SM8150_MASTER_MNOC_HF_MEM_NOC }, 1191}; 1192 1193static struct qcom_icc_node srvc_mnoc = { 1194 .name = "srvc_mnoc", 1195 .id = SM8150_SLAVE_SERVICE_MNOC, 1196 .channels = 1, 1197 .buswidth = 4, 1198}; 1199 1200static struct qcom_icc_node qhs_apss = { 1201 .name = "qhs_apss", 1202 .id = SM8150_SLAVE_APPSS, 1203 .channels = 1, 1204 .buswidth = 8, 1205}; 1206 1207static struct qcom_icc_node qns_cnoc = { 1208 .name = "qns_cnoc", 1209 .id = SM8150_SNOC_CNOC_SLV, 1210 .channels = 1, 1211 .buswidth = 8, 1212 .num_links = 1, 1213 .links = { SM8150_SNOC_CNOC_MAS }, 1214}; 1215 1216static struct qcom_icc_node qns_gemnoc_gc = { 1217 .name = "qns_gemnoc_gc", 1218 .id = SM8150_SLAVE_SNOC_GEM_NOC_GC, 1219 .channels = 1, 1220 .buswidth = 8, 1221 .num_links = 1, 1222 .links = { SM8150_MASTER_SNOC_GC_MEM_NOC }, 1223}; 1224 1225static struct qcom_icc_node qns_gemnoc_sf = { 1226 .name = "qns_gemnoc_sf", 1227 .id = SM8150_SLAVE_SNOC_GEM_NOC_SF, 1228 .channels = 1, 1229 .buswidth = 16, 1230 .num_links = 1, 1231 .links = { SM8150_MASTER_SNOC_SF_MEM_NOC }, 1232}; 1233 1234static struct qcom_icc_node qxs_imem = { 1235 .name = "qxs_imem", 1236 .id = SM8150_SLAVE_OCIMEM, 1237 .channels = 1, 1238 .buswidth = 8, 1239}; 1240 1241static struct qcom_icc_node qxs_pimem = { 1242 .name = "qxs_pimem", 1243 .id = SM8150_SLAVE_PIMEM, 1244 .channels = 1, 1245 .buswidth = 8, 1246}; 1247 1248static struct qcom_icc_node srvc_snoc = { 1249 .name = "srvc_snoc", 1250 .id = SM8150_SLAVE_SERVICE_SNOC, 1251 .channels = 1, 1252 .buswidth = 4, 1253}; 1254 1255static struct qcom_icc_node xs_pcie_0 = { 1256 .name = "xs_pcie_0", 1257 .id = SM8150_SLAVE_PCIE_0, 1258 .channels = 1, 1259 .buswidth = 8, 1260}; 1261 1262static struct qcom_icc_node xs_pcie_1 = { 1263 .name = "xs_pcie_1", 1264 .id = SM8150_SLAVE_PCIE_1, 1265 .channels = 1, 1266 .buswidth = 8, 1267}; 1268 1269static struct qcom_icc_node xs_qdss_stm = { 1270 .name = "xs_qdss_stm", 1271 .id = SM8150_SLAVE_QDSS_STM, 1272 .channels = 1, 1273 .buswidth = 4, 1274}; 1275 1276static struct qcom_icc_node xs_sys_tcu_cfg = { 1277 .name = "xs_sys_tcu_cfg", 1278 .id = SM8150_SLAVE_TCU, 1279 .channels = 1, 1280 .buswidth = 8, 1281}; 1282 1283static struct qcom_icc_bcm bcm_acv = { 1284 .name = "ACV", 1285 .enable_mask = BIT(3), 1286 .keepalive = false, 1287 .num_nodes = 1, 1288 .nodes = { &ebi }, 1289}; 1290 1291static struct qcom_icc_bcm bcm_mc0 = { 1292 .name = "MC0", 1293 .keepalive = true, 1294 .num_nodes = 1, 1295 .nodes = { &ebi }, 1296}; 1297 1298static struct qcom_icc_bcm bcm_sh0 = { 1299 .name = "SH0", 1300 .keepalive = true, 1301 .num_nodes = 1, 1302 .nodes = { &qns_llcc }, 1303}; 1304 1305static struct qcom_icc_bcm bcm_mm0 = { 1306 .name = "MM0", 1307 .keepalive = true, 1308 .num_nodes = 1, 1309 .nodes = { &qns_mem_noc_hf }, 1310}; 1311 1312static struct qcom_icc_bcm bcm_mm1 = { 1313 .name = "MM1", 1314 .keepalive = false, 1315 .num_nodes = 7, 1316 .nodes = { &qxm_camnoc_hf0_uncomp, 1317 &qxm_camnoc_hf1_uncomp, 1318 &qxm_camnoc_sf_uncomp, 1319 &qxm_camnoc_hf0, 1320 &qxm_camnoc_hf1, 1321 &qxm_mdp0, 1322 &qxm_mdp1 1323 }, 1324}; 1325 1326static struct qcom_icc_bcm bcm_sh2 = { 1327 .name = "SH2", 1328 .keepalive = false, 1329 .num_nodes = 1, 1330 .nodes = { &qns_gem_noc_snoc }, 1331}; 1332 1333static struct qcom_icc_bcm bcm_mm2 = { 1334 .name = "MM2", 1335 .keepalive = false, 1336 .num_nodes = 2, 1337 .nodes = { &qxm_camnoc_sf, &qns2_mem_noc }, 1338}; 1339 1340static struct qcom_icc_bcm bcm_sh3 = { 1341 .name = "SH3", 1342 .keepalive = false, 1343 .num_nodes = 2, 1344 .nodes = { &acm_gpu_tcu, &acm_sys_tcu }, 1345}; 1346 1347static struct qcom_icc_bcm bcm_mm3 = { 1348 .name = "MM3", 1349 .keepalive = false, 1350 .num_nodes = 4, 1351 .nodes = { &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, 1352}; 1353 1354static struct qcom_icc_bcm bcm_sh4 = { 1355 .name = "SH4", 1356 .keepalive = false, 1357 .num_nodes = 1, 1358 .nodes = { &qnm_cmpnoc }, 1359}; 1360 1361static struct qcom_icc_bcm bcm_sh5 = { 1362 .name = "SH5", 1363 .keepalive = false, 1364 .num_nodes = 1, 1365 .nodes = { &acm_apps }, 1366}; 1367 1368static struct qcom_icc_bcm bcm_sn0 = { 1369 .name = "SN0", 1370 .keepalive = true, 1371 .num_nodes = 1, 1372 .nodes = { &qns_gemnoc_sf }, 1373}; 1374 1375static struct qcom_icc_bcm bcm_co0 = { 1376 .name = "CO0", 1377 .keepalive = false, 1378 .num_nodes = 1, 1379 .nodes = { &qns_cdsp_mem_noc }, 1380}; 1381 1382static struct qcom_icc_bcm bcm_ce0 = { 1383 .name = "CE0", 1384 .keepalive = false, 1385 .num_nodes = 1, 1386 .nodes = { &qxm_crypto }, 1387}; 1388 1389static struct qcom_icc_bcm bcm_sn1 = { 1390 .name = "SN1", 1391 .keepalive = false, 1392 .num_nodes = 1, 1393 .nodes = { &qxs_imem }, 1394}; 1395 1396static struct qcom_icc_bcm bcm_co1 = { 1397 .name = "CO1", 1398 .keepalive = false, 1399 .num_nodes = 1, 1400 .nodes = { &qnm_npu }, 1401}; 1402 1403static struct qcom_icc_bcm bcm_cn0 = { 1404 .name = "CN0", 1405 .keepalive = true, 1406 .num_nodes = 53, 1407 .nodes = { &qhm_spdm, 1408 &qnm_snoc, 1409 &qhs_a1_noc_cfg, 1410 &qhs_a2_noc_cfg, 1411 &qhs_ahb2phy_south, 1412 &qhs_aop, 1413 &qhs_aoss, 1414 &qhs_camera_cfg, 1415 &qhs_clk_ctl, 1416 &qhs_compute_dsp, 1417 &qhs_cpr_cx, 1418 &qhs_cpr_mmcx, 1419 &qhs_cpr_mx, 1420 &qhs_crypto0_cfg, 1421 &qhs_ddrss_cfg, 1422 &qhs_display_cfg, 1423 &qhs_emac_cfg, 1424 &qhs_glm, 1425 &qhs_gpuss_cfg, 1426 &qhs_imem_cfg, 1427 &qhs_ipa, 1428 &qhs_mnoc_cfg, 1429 &qhs_npu_cfg, 1430 &qhs_pcie0_cfg, 1431 &qhs_pcie1_cfg, 1432 &qhs_phy_refgen_north, 1433 &qhs_pimem_cfg, 1434 &qhs_prng, 1435 &qhs_qdss_cfg, 1436 &qhs_qspi, 1437 &qhs_qupv3_east, 1438 &qhs_qupv3_north, 1439 &qhs_qupv3_south, 1440 &qhs_sdc2, 1441 &qhs_sdc4, 1442 &qhs_snoc_cfg, 1443 &qhs_spdm, 1444 &qhs_spss_cfg, 1445 &qhs_ssc_cfg, 1446 &qhs_tcsr, 1447 &qhs_tlmm_east, 1448 &qhs_tlmm_north, 1449 &qhs_tlmm_south, 1450 &qhs_tlmm_west, 1451 &qhs_tsif, 1452 &qhs_ufs_card_cfg, 1453 &qhs_ufs_mem_cfg, 1454 &qhs_usb3_0, 1455 &qhs_usb3_1, 1456 &qhs_venus_cfg, 1457 &qhs_vsense_ctrl_cfg, 1458 &qns_cnoc_a2noc, 1459 &srvc_cnoc 1460 }, 1461}; 1462 1463static struct qcom_icc_bcm bcm_qup0 = { 1464 .name = "QUP0", 1465 .keepalive = false, 1466 .num_nodes = 3, 1467 .nodes = { &qhm_qup0, &qhm_qup1, &qhm_qup2 }, 1468}; 1469 1470static struct qcom_icc_bcm bcm_sn2 = { 1471 .name = "SN2", 1472 .keepalive = false, 1473 .num_nodes = 1, 1474 .nodes = { &qns_gemnoc_gc }, 1475}; 1476 1477static struct qcom_icc_bcm bcm_sn3 = { 1478 .name = "SN3", 1479 .keepalive = false, 1480 .num_nodes = 3, 1481 .nodes = { &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc }, 1482}; 1483 1484static struct qcom_icc_bcm bcm_sn4 = { 1485 .name = "SN4", 1486 .keepalive = false, 1487 .num_nodes = 1, 1488 .nodes = { &qxs_pimem }, 1489}; 1490 1491static struct qcom_icc_bcm bcm_sn5 = { 1492 .name = "SN5", 1493 .keepalive = false, 1494 .num_nodes = 1, 1495 .nodes = { &xs_qdss_stm }, 1496}; 1497 1498static struct qcom_icc_bcm bcm_sn8 = { 1499 .name = "SN8", 1500 .keepalive = false, 1501 .num_nodes = 2, 1502 .nodes = { &xs_pcie_0, &xs_pcie_1 }, 1503}; 1504 1505static struct qcom_icc_bcm bcm_sn9 = { 1506 .name = "SN9", 1507 .keepalive = false, 1508 .num_nodes = 1, 1509 .nodes = { &qnm_aggre1_noc }, 1510}; 1511 1512static struct qcom_icc_bcm bcm_sn11 = { 1513 .name = "SN11", 1514 .keepalive = false, 1515 .num_nodes = 1, 1516 .nodes = { &qnm_aggre2_noc }, 1517}; 1518 1519static struct qcom_icc_bcm bcm_sn12 = { 1520 .name = "SN12", 1521 .keepalive = false, 1522 .num_nodes = 2, 1523 .nodes = { &qxm_pimem, &xm_gic }, 1524}; 1525 1526static struct qcom_icc_bcm bcm_sn14 = { 1527 .name = "SN14", 1528 .keepalive = false, 1529 .num_nodes = 1, 1530 .nodes = { &qns_pcie_mem_noc }, 1531}; 1532 1533static struct qcom_icc_bcm bcm_sn15 = { 1534 .name = "SN15", 1535 .keepalive = false, 1536 .num_nodes = 1, 1537 .nodes = { &qnm_gemnoc }, 1538}; 1539 1540static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1541 &bcm_qup0, 1542 &bcm_sn3, 1543}; 1544 1545static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1546 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1547 [MASTER_QUP_0] = &qhm_qup0, 1548 [MASTER_EMAC] = &xm_emac, 1549 [MASTER_UFS_MEM] = &xm_ufs_mem, 1550 [MASTER_USB3] = &xm_usb3_0, 1551 [MASTER_USB3_1] = &xm_usb3_1, 1552 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc, 1553 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1554}; 1555 1556static const struct qcom_icc_desc sm8150_aggre1_noc = { 1557 .nodes = aggre1_noc_nodes, 1558 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1559 .bcms = aggre1_noc_bcms, 1560 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1561}; 1562 1563static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1564 &bcm_ce0, 1565 &bcm_qup0, 1566 &bcm_sn14, 1567 &bcm_sn3, 1568}; 1569 1570static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1571 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1572 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1573 [MASTER_QSPI] = &qhm_qspi, 1574 [MASTER_QUP_1] = &qhm_qup1, 1575 [MASTER_QUP_2] = &qhm_qup2, 1576 [MASTER_SENSORS_AHB] = &qhm_sensorss_ahb, 1577 [MASTER_TSIF] = &qhm_tsif, 1578 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1579 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 1580 [MASTER_IPA] = &qxm_ipa, 1581 [MASTER_PCIE] = &xm_pcie3_0, 1582 [MASTER_PCIE_1] = &xm_pcie3_1, 1583 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1584 [MASTER_SDCC_2] = &xm_sdc2, 1585 [MASTER_SDCC_4] = &xm_sdc4, 1586 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc, 1587 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1588 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1589}; 1590 1591static const struct qcom_icc_desc sm8150_aggre2_noc = { 1592 .nodes = aggre2_noc_nodes, 1593 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1594 .bcms = aggre2_noc_bcms, 1595 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1596}; 1597 1598static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { 1599 &bcm_mm1, 1600}; 1601 1602static struct qcom_icc_node * const camnoc_virt_nodes[] = { 1603 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1604 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, 1605 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1606 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1607}; 1608 1609static const struct qcom_icc_desc sm8150_camnoc_virt = { 1610 .nodes = camnoc_virt_nodes, 1611 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), 1612 .bcms = camnoc_virt_bcms, 1613 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), 1614}; 1615 1616static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1617 &bcm_co0, 1618 &bcm_co1, 1619}; 1620 1621static struct qcom_icc_node * const compute_noc_nodes[] = { 1622 [MASTER_NPU] = &qnm_npu, 1623 [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc, 1624}; 1625 1626static const struct qcom_icc_desc sm8150_compute_noc = { 1627 .nodes = compute_noc_nodes, 1628 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1629 .bcms = compute_noc_bcms, 1630 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1631}; 1632 1633static struct qcom_icc_bcm * const config_noc_bcms[] = { 1634 &bcm_cn0, 1635}; 1636 1637static struct qcom_icc_node * const config_noc_nodes[] = { 1638 [MASTER_SPDM] = &qhm_spdm, 1639 [SNOC_CNOC_MAS] = &qnm_snoc, 1640 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1641 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1642 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1643 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south, 1644 [SLAVE_AOP] = &qhs_aop, 1645 [SLAVE_AOSS] = &qhs_aoss, 1646 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1647 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1648 [SLAVE_CDSP_CFG] = &qhs_compute_dsp, 1649 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1650 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1651 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1652 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1653 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1654 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1655 [SLAVE_EMAC_CFG] = &qhs_emac_cfg, 1656 [SLAVE_GLM] = &qhs_glm, 1657 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 1658 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1659 [SLAVE_IPA_CFG] = &qhs_ipa, 1660 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1661 [SLAVE_NPU_CFG] = &qhs_npu_cfg, 1662 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1663 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1664 [SLAVE_NORTH_PHY_CFG] = &qhs_phy_refgen_north, 1665 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1666 [SLAVE_PRNG] = &qhs_prng, 1667 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1668 [SLAVE_QSPI] = &qhs_qspi, 1669 [SLAVE_QUP_2] = &qhs_qupv3_east, 1670 [SLAVE_QUP_1] = &qhs_qupv3_north, 1671 [SLAVE_QUP_0] = &qhs_qupv3_south, 1672 [SLAVE_SDCC_2] = &qhs_sdc2, 1673 [SLAVE_SDCC_4] = &qhs_sdc4, 1674 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1675 [SLAVE_SPDM_WRAPPER] = &qhs_spdm, 1676 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 1677 [SLAVE_SSC_CFG] = &qhs_ssc_cfg, 1678 [SLAVE_TCSR] = &qhs_tcsr, 1679 [SLAVE_TLMM_EAST] = &qhs_tlmm_east, 1680 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north, 1681 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, 1682 [SLAVE_TLMM_WEST] = &qhs_tlmm_west, 1683 [SLAVE_TSIF] = &qhs_tsif, 1684 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 1685 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1686 [SLAVE_USB3] = &qhs_usb3_0, 1687 [SLAVE_USB3_1] = &qhs_usb3_1, 1688 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1689 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1690 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1691 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1692}; 1693 1694static const struct qcom_icc_desc sm8150_config_noc = { 1695 .nodes = config_noc_nodes, 1696 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1697 .bcms = config_noc_bcms, 1698 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1699}; 1700 1701static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1702}; 1703 1704static struct qcom_icc_node * const dc_noc_nodes[] = { 1705 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, 1706 [SLAVE_LLCC_CFG] = &qhs_llcc, 1707 [SLAVE_GEM_NOC_CFG] = &qhs_memnoc, 1708}; 1709 1710static const struct qcom_icc_desc sm8150_dc_noc = { 1711 .nodes = dc_noc_nodes, 1712 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1713 .bcms = dc_noc_bcms, 1714 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1715}; 1716 1717static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1718 &bcm_sh0, 1719 &bcm_sh2, 1720 &bcm_sh3, 1721 &bcm_sh4, 1722 &bcm_sh5, 1723}; 1724 1725static struct qcom_icc_node * const gem_noc_nodes[] = { 1726 [MASTER_AMPSS_M0] = &acm_apps, 1727 [MASTER_GPU_TCU] = &acm_gpu_tcu, 1728 [MASTER_SYS_TCU] = &acm_sys_tcu, 1729 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1730 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1731 [MASTER_GRAPHICS_3D] = &qnm_gpu, 1732 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1733 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1734 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie, 1735 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1736 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1737 [MASTER_ECC] = &qxm_ecc, 1738 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1739 [SLAVE_ECC] = &qns_ecc, 1740 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1741 [SLAVE_LLCC] = &qns_llcc, 1742 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 1743}; 1744 1745static const struct qcom_icc_desc sm8150_gem_noc = { 1746 .nodes = gem_noc_nodes, 1747 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1748 .bcms = gem_noc_bcms, 1749 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1750}; 1751 1752static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1753 &bcm_acv, 1754 &bcm_mc0, 1755}; 1756 1757static struct qcom_icc_node * const mc_virt_nodes[] = { 1758 [MASTER_LLCC] = &llcc_mc, 1759 [SLAVE_EBI_CH0] = &ebi, 1760}; 1761 1762static const struct qcom_icc_desc sm8150_mc_virt = { 1763 .nodes = mc_virt_nodes, 1764 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1765 .bcms = mc_virt_bcms, 1766 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1767}; 1768 1769static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1770 &bcm_mm0, 1771 &bcm_mm1, 1772 &bcm_mm2, 1773 &bcm_mm3, 1774}; 1775 1776static struct qcom_icc_node * const mmss_noc_nodes[] = { 1777 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1778 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, 1779 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, 1780 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1781 [MASTER_MDP_PORT0] = &qxm_mdp0, 1782 [MASTER_MDP_PORT1] = &qxm_mdp1, 1783 [MASTER_ROTATOR] = &qxm_rot, 1784 [MASTER_VIDEO_P0] = &qxm_venus0, 1785 [MASTER_VIDEO_P1] = &qxm_venus1, 1786 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1787 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, 1788 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1789 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1790}; 1791 1792static const struct qcom_icc_desc sm8150_mmss_noc = { 1793 .nodes = mmss_noc_nodes, 1794 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1795 .bcms = mmss_noc_bcms, 1796 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1797}; 1798 1799static struct qcom_icc_bcm * const system_noc_bcms[] = { 1800 &bcm_sn0, 1801 &bcm_sn1, 1802 &bcm_sn11, 1803 &bcm_sn12, 1804 &bcm_sn15, 1805 &bcm_sn2, 1806 &bcm_sn3, 1807 &bcm_sn4, 1808 &bcm_sn5, 1809 &bcm_sn8, 1810 &bcm_sn9, 1811}; 1812 1813static struct qcom_icc_node * const system_noc_nodes[] = { 1814 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1815 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, 1816 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, 1817 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1818 [MASTER_PIMEM] = &qxm_pimem, 1819 [MASTER_GIC] = &xm_gic, 1820 [SLAVE_APPSS] = &qhs_apss, 1821 [SNOC_CNOC_SLV] = &qns_cnoc, 1822 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1823 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1824 [SLAVE_OCIMEM] = &qxs_imem, 1825 [SLAVE_PIMEM] = &qxs_pimem, 1826 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1827 [SLAVE_PCIE_0] = &xs_pcie_0, 1828 [SLAVE_PCIE_1] = &xs_pcie_1, 1829 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1830 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1831}; 1832 1833static const struct qcom_icc_desc sm8150_system_noc = { 1834 .nodes = system_noc_nodes, 1835 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1836 .bcms = system_noc_bcms, 1837 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1838}; 1839 1840static const struct of_device_id qnoc_of_match[] = { 1841 { .compatible = "qcom,sm8150-aggre1-noc", 1842 .data = &sm8150_aggre1_noc}, 1843 { .compatible = "qcom,sm8150-aggre2-noc", 1844 .data = &sm8150_aggre2_noc}, 1845 { .compatible = "qcom,sm8150-camnoc-virt", 1846 .data = &sm8150_camnoc_virt}, 1847 { .compatible = "qcom,sm8150-compute-noc", 1848 .data = &sm8150_compute_noc}, 1849 { .compatible = "qcom,sm8150-config-noc", 1850 .data = &sm8150_config_noc}, 1851 { .compatible = "qcom,sm8150-dc-noc", 1852 .data = &sm8150_dc_noc}, 1853 { .compatible = "qcom,sm8150-gem-noc", 1854 .data = &sm8150_gem_noc}, 1855 { .compatible = "qcom,sm8150-mc-virt", 1856 .data = &sm8150_mc_virt}, 1857 { .compatible = "qcom,sm8150-mmss-noc", 1858 .data = &sm8150_mmss_noc}, 1859 { .compatible = "qcom,sm8150-system-noc", 1860 .data = &sm8150_system_noc}, 1861 { } 1862}; 1863MODULE_DEVICE_TABLE(of, qnoc_of_match); 1864 1865static struct platform_driver qnoc_driver = { 1866 .probe = qcom_icc_rpmh_probe, 1867 .remove_new = qcom_icc_rpmh_remove, 1868 .driver = { 1869 .name = "qnoc-sm8150", 1870 .of_match_table = qnoc_of_match, 1871 }, 1872}; 1873module_platform_driver(qnoc_driver); 1874 1875MODULE_DESCRIPTION("Qualcomm SM8150 NoC driver"); 1876MODULE_LICENSE("GPL v2"); 1877