1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Based on data from msm8909-bus.dtsi in Qualcomm's msm-3.18 release: 4 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. 5 */ 6 7#include <linux/device.h> 8#include <linux/interconnect-provider.h> 9#include <linux/mod_devicetable.h> 10#include <linux/module.h> 11#include <linux/platform_device.h> 12#include <linux/regmap.h> 13 14#include <dt-bindings/interconnect/qcom,msm8909.h> 15 16#include "icc-rpm.h" 17 18enum { 19 QNOC_MASTER_AMPSS_M0 = 1, 20 QNOC_MASTER_GRAPHICS_3D, 21 QNOC_SNOC_BIMC_0_MAS, 22 QNOC_SNOC_BIMC_1_MAS, 23 QNOC_MASTER_TCU_0, 24 QNOC_MASTER_TCU_1, 25 QNOC_MASTER_AUDIO, 26 QNOC_MASTER_SPDM, 27 QNOC_MASTER_DEHR, 28 QNOC_MASTER_QPIC, 29 QNOC_MASTER_BLSP_1, 30 QNOC_MASTER_USB_HS, 31 QNOC_MASTER_CRYPTO_CORE0, 32 QNOC_MASTER_SDCC_1, 33 QNOC_MASTER_SDCC_2, 34 QNOC_SNOC_PNOC_MAS, 35 QNOC_MASTER_QDSS_BAM, 36 QNOC_BIMC_SNOC_MAS, 37 QNOC_MASTER_MDP_PORT0, 38 QNOC_PNOC_SNOC_MAS, 39 QNOC_MASTER_VIDEO_P0, 40 QNOC_MASTER_VFE, 41 QNOC_MASTER_QDSS_ETR, 42 QNOC_PNOC_M_0, 43 QNOC_PNOC_M_1, 44 QNOC_PNOC_INT_0, 45 QNOC_PNOC_INT_1, 46 QNOC_PNOC_SLV_0, 47 QNOC_PNOC_SLV_1, 48 QNOC_PNOC_SLV_2, 49 QNOC_PNOC_SLV_3, 50 QNOC_PNOC_SLV_4, 51 QNOC_PNOC_SLV_5, 52 QNOC_PNOC_SLV_7, 53 QNOC_SNOC_MM_INT_0, 54 QNOC_SNOC_MM_INT_1, 55 QNOC_SNOC_MM_INT_2, 56 QNOC_SNOC_MM_INT_BIMC, 57 QNOC_SNOC_QDSS_INT, 58 QNOC_SNOC_INT_0, 59 QNOC_SNOC_INT_1, 60 QNOC_SNOC_INT_BIMC, 61 QNOC_SLAVE_EBI_CH0, 62 QNOC_BIMC_SNOC_SLV, 63 QNOC_SLAVE_TCSR, 64 QNOC_SLAVE_SDCC_1, 65 QNOC_SLAVE_BLSP_1, 66 QNOC_SLAVE_CRYPTO_0_CFG, 67 QNOC_SLAVE_MESSAGE_RAM, 68 QNOC_SLAVE_PDM, 69 QNOC_SLAVE_PRNG, 70 QNOC_SLAVE_USB_HS, 71 QNOC_SLAVE_QPIC, 72 QNOC_SLAVE_SPDM, 73 QNOC_SLAVE_SDCC_2, 74 QNOC_SLAVE_AUDIO, 75 QNOC_SLAVE_DEHR_CFG, 76 QNOC_SLAVE_SNOC_CFG, 77 QNOC_SLAVE_QDSS_CFG, 78 QNOC_SLAVE_USB_PHYS_CFG, 79 QNOC_SLAVE_CAMERA_CFG, 80 QNOC_SLAVE_DISPLAY_CFG, 81 QNOC_SLAVE_VENUS_CFG, 82 QNOC_SLAVE_TLMM, 83 QNOC_SLAVE_GRAPHICS_3D_CFG, 84 QNOC_SLAVE_IMEM_CFG, 85 QNOC_SLAVE_BIMC_CFG, 86 QNOC_SLAVE_PMIC_ARB, 87 QNOC_SLAVE_TCU, 88 QNOC_PNOC_SNOC_SLV, 89 QNOC_SLAVE_APPSS, 90 QNOC_SNOC_BIMC_0_SLV, 91 QNOC_SNOC_BIMC_1_SLV, 92 QNOC_SLAVE_SYSTEM_IMEM, 93 QNOC_SNOC_PNOC_SLV, 94 QNOC_SLAVE_QDSS_STM, 95 QNOC_SLAVE_CATS_128, 96 QNOC_SLAVE_OCMEM_64, 97}; 98 99static const u16 mas_apps_proc_links[] = { 100 QNOC_BIMC_SNOC_SLV, 101 QNOC_SLAVE_EBI_CH0 102}; 103 104static struct qcom_icc_node mas_apps_proc = { 105 .name = "mas_apps_proc", 106 .id = QNOC_MASTER_AMPSS_M0, 107 .buswidth = 8, 108 .mas_rpm_id = 0, 109 .slv_rpm_id = -1, 110 .qos.ap_owned = true, 111 .qos.qos_mode = NOC_QOS_MODE_FIXED, 112 .qos.areq_prio = 0, 113 .qos.prio_level = 0, 114 .qos.qos_port = 0, 115 .num_links = ARRAY_SIZE(mas_apps_proc_links), 116 .links = mas_apps_proc_links, 117}; 118 119static const u16 mas_oxili_links[] = { 120 QNOC_BIMC_SNOC_SLV, 121 QNOC_SLAVE_EBI_CH0 122}; 123 124static struct qcom_icc_node mas_oxili = { 125 .name = "mas_oxili", 126 .id = QNOC_MASTER_GRAPHICS_3D, 127 .buswidth = 8, 128 .mas_rpm_id = 6, 129 .slv_rpm_id = -1, 130 .qos.ap_owned = true, 131 .qos.qos_mode = NOC_QOS_MODE_FIXED, 132 .qos.areq_prio = 0, 133 .qos.prio_level = 0, 134 .qos.qos_port = 2, 135 .num_links = ARRAY_SIZE(mas_oxili_links), 136 .links = mas_oxili_links, 137}; 138 139static const u16 mas_snoc_bimc_0_links[] = { 140 QNOC_SLAVE_EBI_CH0 141}; 142 143static struct qcom_icc_node mas_snoc_bimc_0 = { 144 .name = "mas_snoc_bimc_0", 145 .id = QNOC_SNOC_BIMC_0_MAS, 146 .buswidth = 8, 147 .mas_rpm_id = 3, 148 .slv_rpm_id = -1, 149 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 150 .qos.areq_prio = 0, 151 .qos.prio_level = 0, 152 .qos.qos_port = 3, 153 .num_links = ARRAY_SIZE(mas_snoc_bimc_0_links), 154 .links = mas_snoc_bimc_0_links, 155}; 156 157static const u16 mas_snoc_bimc_1_links[] = { 158 QNOC_SLAVE_EBI_CH0 159}; 160 161static struct qcom_icc_node mas_snoc_bimc_1 = { 162 .name = "mas_snoc_bimc_1", 163 .id = QNOC_SNOC_BIMC_1_MAS, 164 .buswidth = 8, 165 .mas_rpm_id = 76, 166 .slv_rpm_id = -1, 167 .qos.ap_owned = true, 168 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 169 .qos.areq_prio = 0, 170 .qos.prio_level = 0, 171 .qos.qos_port = 4, 172 .num_links = ARRAY_SIZE(mas_snoc_bimc_1_links), 173 .links = mas_snoc_bimc_1_links, 174}; 175 176static const u16 mas_tcu_0_links[] = { 177 QNOC_BIMC_SNOC_SLV, 178 QNOC_SLAVE_EBI_CH0 179}; 180 181static struct qcom_icc_node mas_tcu_0 = { 182 .name = "mas_tcu_0", 183 .id = QNOC_MASTER_TCU_0, 184 .buswidth = 8, 185 .mas_rpm_id = 102, 186 .slv_rpm_id = -1, 187 .qos.ap_owned = true, 188 .qos.qos_mode = NOC_QOS_MODE_FIXED, 189 .qos.areq_prio = 0, 190 .qos.prio_level = 2, 191 .qos.qos_port = 5, 192 .num_links = ARRAY_SIZE(mas_tcu_0_links), 193 .links = mas_tcu_0_links, 194}; 195 196static const u16 mas_tcu_1_links[] = { 197 QNOC_BIMC_SNOC_SLV, 198 QNOC_SLAVE_EBI_CH0 199}; 200 201static struct qcom_icc_node mas_tcu_1 = { 202 .name = "mas_tcu_1", 203 .id = QNOC_MASTER_TCU_1, 204 .buswidth = 8, 205 .mas_rpm_id = 103, 206 .slv_rpm_id = -1, 207 .qos.ap_owned = true, 208 .qos.qos_mode = NOC_QOS_MODE_FIXED, 209 .qos.areq_prio = 0, 210 .qos.prio_level = 2, 211 .qos.qos_port = 6, 212 .num_links = ARRAY_SIZE(mas_tcu_1_links), 213 .links = mas_tcu_1_links, 214}; 215 216static const u16 mas_audio_links[] = { 217 QNOC_PNOC_M_0 218}; 219 220static struct qcom_icc_node mas_audio = { 221 .name = "mas_audio", 222 .id = QNOC_MASTER_AUDIO, 223 .buswidth = 4, 224 .mas_rpm_id = 78, 225 .slv_rpm_id = -1, 226 .num_links = ARRAY_SIZE(mas_audio_links), 227 .links = mas_audio_links, 228}; 229 230static const u16 mas_spdm_links[] = { 231 QNOC_PNOC_M_0 232}; 233 234static struct qcom_icc_node mas_spdm = { 235 .name = "mas_spdm", 236 .id = QNOC_MASTER_SPDM, 237 .buswidth = 4, 238 .mas_rpm_id = 50, 239 .slv_rpm_id = -1, 240 .num_links = ARRAY_SIZE(mas_spdm_links), 241 .links = mas_spdm_links, 242}; 243 244static const u16 mas_dehr_links[] = { 245 QNOC_PNOC_M_0 246}; 247 248static struct qcom_icc_node mas_dehr = { 249 .name = "mas_dehr", 250 .id = QNOC_MASTER_DEHR, 251 .buswidth = 4, 252 .mas_rpm_id = 48, 253 .slv_rpm_id = -1, 254 .num_links = ARRAY_SIZE(mas_dehr_links), 255 .links = mas_dehr_links, 256}; 257 258static const u16 mas_qpic_links[] = { 259 QNOC_PNOC_M_0 260}; 261 262static struct qcom_icc_node mas_qpic = { 263 .name = "mas_qpic", 264 .id = QNOC_MASTER_QPIC, 265 .buswidth = 4, 266 .mas_rpm_id = 58, 267 .slv_rpm_id = -1, 268 .num_links = ARRAY_SIZE(mas_qpic_links), 269 .links = mas_qpic_links, 270}; 271 272static const u16 mas_blsp_1_links[] = { 273 QNOC_PNOC_M_1 274}; 275 276static struct qcom_icc_node mas_blsp_1 = { 277 .name = "mas_blsp_1", 278 .id = QNOC_MASTER_BLSP_1, 279 .buswidth = 4, 280 .mas_rpm_id = 41, 281 .slv_rpm_id = -1, 282 .num_links = ARRAY_SIZE(mas_blsp_1_links), 283 .links = mas_blsp_1_links, 284}; 285 286static const u16 mas_usb_hs_links[] = { 287 QNOC_PNOC_M_1 288}; 289 290static struct qcom_icc_node mas_usb_hs = { 291 .name = "mas_usb_hs", 292 .id = QNOC_MASTER_USB_HS, 293 .buswidth = 4, 294 .mas_rpm_id = 42, 295 .slv_rpm_id = -1, 296 .num_links = ARRAY_SIZE(mas_usb_hs_links), 297 .links = mas_usb_hs_links, 298}; 299 300static const u16 mas_crypto_links[] = { 301 QNOC_PNOC_INT_1 302}; 303 304static struct qcom_icc_node mas_crypto = { 305 .name = "mas_crypto", 306 .id = QNOC_MASTER_CRYPTO_CORE0, 307 .buswidth = 8, 308 .mas_rpm_id = 23, 309 .slv_rpm_id = -1, 310 .qos.ap_owned = true, 311 .qos.qos_mode = NOC_QOS_MODE_FIXED, 312 .qos.areq_prio = 0, 313 .qos.prio_level = 0, 314 .qos.qos_port = 0, 315 .num_links = ARRAY_SIZE(mas_crypto_links), 316 .links = mas_crypto_links, 317}; 318 319static const u16 mas_sdcc_1_links[] = { 320 QNOC_PNOC_INT_1 321}; 322 323static struct qcom_icc_node mas_sdcc_1 = { 324 .name = "mas_sdcc_1", 325 .id = QNOC_MASTER_SDCC_1, 326 .buswidth = 8, 327 .mas_rpm_id = 33, 328 .slv_rpm_id = -1, 329 .qos.qos_mode = NOC_QOS_MODE_FIXED, 330 .qos.areq_prio = 0, 331 .qos.prio_level = 0, 332 .qos.qos_port = 7, 333 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 334 .links = mas_sdcc_1_links, 335}; 336 337static const u16 mas_sdcc_2_links[] = { 338 QNOC_PNOC_INT_1 339}; 340 341static struct qcom_icc_node mas_sdcc_2 = { 342 .name = "mas_sdcc_2", 343 .id = QNOC_MASTER_SDCC_2, 344 .buswidth = 8, 345 .mas_rpm_id = 35, 346 .slv_rpm_id = -1, 347 .qos.qos_mode = NOC_QOS_MODE_FIXED, 348 .qos.areq_prio = 0, 349 .qos.prio_level = 0, 350 .qos.qos_port = 8, 351 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 352 .links = mas_sdcc_2_links, 353}; 354 355static const u16 mas_snoc_pcnoc_links[] = { 356 QNOC_PNOC_INT_0 357}; 358 359static struct qcom_icc_node mas_snoc_pcnoc = { 360 .name = "mas_snoc_pcnoc", 361 .id = QNOC_SNOC_PNOC_MAS, 362 .buswidth = 8, 363 .mas_rpm_id = 77, 364 .slv_rpm_id = -1, 365 .qos.qos_mode = NOC_QOS_MODE_FIXED, 366 .qos.areq_prio = 0, 367 .qos.prio_level = 0, 368 .qos.qos_port = 9, 369 .num_links = ARRAY_SIZE(mas_snoc_pcnoc_links), 370 .links = mas_snoc_pcnoc_links, 371}; 372 373static const u16 mas_qdss_bam_links[] = { 374 QNOC_SNOC_QDSS_INT 375}; 376 377static struct qcom_icc_node mas_qdss_bam = { 378 .name = "mas_qdss_bam", 379 .id = QNOC_MASTER_QDSS_BAM, 380 .buswidth = 4, 381 .mas_rpm_id = 19, 382 .slv_rpm_id = -1, 383 .qos.ap_owned = true, 384 .qos.qos_mode = NOC_QOS_MODE_FIXED, 385 .qos.areq_prio = 1, 386 .qos.prio_level = 1, 387 .qos.qos_port = 11, 388 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 389 .links = mas_qdss_bam_links, 390}; 391 392static const u16 mas_bimc_snoc_links[] = { 393 QNOC_SNOC_INT_0, 394 QNOC_SNOC_INT_1 395}; 396 397static struct qcom_icc_node mas_bimc_snoc = { 398 .name = "mas_bimc_snoc", 399 .id = QNOC_BIMC_SNOC_MAS, 400 .buswidth = 8, 401 .mas_rpm_id = 21, 402 .slv_rpm_id = -1, 403 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 404 .links = mas_bimc_snoc_links, 405}; 406 407static const u16 mas_mdp_links[] = { 408 QNOC_SNOC_MM_INT_1, 409 QNOC_SNOC_MM_INT_2 410}; 411 412static struct qcom_icc_node mas_mdp = { 413 .name = "mas_mdp", 414 .id = QNOC_MASTER_MDP_PORT0, 415 .buswidth = 16, 416 .mas_rpm_id = 8, 417 .slv_rpm_id = -1, 418 .qos.ap_owned = true, 419 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 420 .qos.areq_prio = 0, 421 .qos.prio_level = 0, 422 .qos.qos_port = 7, 423 .num_links = ARRAY_SIZE(mas_mdp_links), 424 .links = mas_mdp_links, 425 .ab_coeff = 167, 426}; 427 428static const u16 mas_pcnoc_snoc_links[] = { 429 QNOC_SNOC_INT_0, 430 QNOC_SNOC_INT_1, 431 QNOC_SNOC_INT_BIMC 432}; 433 434static struct qcom_icc_node mas_pcnoc_snoc = { 435 .name = "mas_pcnoc_snoc", 436 .id = QNOC_PNOC_SNOC_MAS, 437 .buswidth = 8, 438 .mas_rpm_id = 29, 439 .slv_rpm_id = -1, 440 .qos.qos_mode = NOC_QOS_MODE_FIXED, 441 .qos.areq_prio = 0, 442 .qos.prio_level = 0, 443 .qos.qos_port = 5, 444 .num_links = ARRAY_SIZE(mas_pcnoc_snoc_links), 445 .links = mas_pcnoc_snoc_links, 446}; 447 448static const u16 mas_venus_links[] = { 449 QNOC_SNOC_MM_INT_0, 450 QNOC_SNOC_MM_INT_2 451}; 452 453static struct qcom_icc_node mas_venus = { 454 .name = "mas_venus", 455 .id = QNOC_MASTER_VIDEO_P0, 456 .buswidth = 16, 457 .mas_rpm_id = 9, 458 .slv_rpm_id = -1, 459 .qos.ap_owned = true, 460 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 461 .qos.areq_prio = 0, 462 .qos.prio_level = 0, 463 .qos.qos_port = 8, 464 .num_links = ARRAY_SIZE(mas_venus_links), 465 .links = mas_venus_links, 466 .ab_coeff = 167, 467}; 468 469static const u16 mas_vfe_links[] = { 470 QNOC_SNOC_MM_INT_1, 471 QNOC_SNOC_MM_INT_2 472}; 473 474static struct qcom_icc_node mas_vfe = { 475 .name = "mas_vfe", 476 .id = QNOC_MASTER_VFE, 477 .buswidth = 16, 478 .mas_rpm_id = 11, 479 .slv_rpm_id = -1, 480 .qos.ap_owned = true, 481 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 482 .qos.areq_prio = 0, 483 .qos.prio_level = 0, 484 .qos.qos_port = 9, 485 .num_links = ARRAY_SIZE(mas_vfe_links), 486 .links = mas_vfe_links, 487 .ab_coeff = 167, 488}; 489 490static const u16 mas_qdss_etr_links[] = { 491 QNOC_SNOC_QDSS_INT 492}; 493 494static struct qcom_icc_node mas_qdss_etr = { 495 .name = "mas_qdss_etr", 496 .id = QNOC_MASTER_QDSS_ETR, 497 .buswidth = 8, 498 .mas_rpm_id = 31, 499 .slv_rpm_id = -1, 500 .qos.ap_owned = true, 501 .qos.qos_mode = NOC_QOS_MODE_FIXED, 502 .qos.areq_prio = 1, 503 .qos.prio_level = 1, 504 .qos.qos_port = 10, 505 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 506 .links = mas_qdss_etr_links, 507}; 508 509static const u16 pcnoc_m_0_links[] = { 510 QNOC_PNOC_SNOC_SLV 511}; 512 513static struct qcom_icc_node pcnoc_m_0 = { 514 .name = "pcnoc_m_0", 515 .id = QNOC_PNOC_M_0, 516 .buswidth = 8, 517 .mas_rpm_id = 87, 518 .slv_rpm_id = 116, 519 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 520 .qos.areq_prio = 0, 521 .qos.prio_level = 0, 522 .qos.qos_port = 5, 523 .num_links = ARRAY_SIZE(pcnoc_m_0_links), 524 .links = pcnoc_m_0_links, 525}; 526 527static const u16 pcnoc_m_1_links[] = { 528 QNOC_PNOC_SNOC_SLV 529}; 530 531static struct qcom_icc_node pcnoc_m_1 = { 532 .name = "pcnoc_m_1", 533 .id = QNOC_PNOC_M_1, 534 .buswidth = 8, 535 .mas_rpm_id = 88, 536 .slv_rpm_id = 117, 537 .qos.qos_mode = NOC_QOS_MODE_FIXED, 538 .qos.areq_prio = 0, 539 .qos.prio_level = 0, 540 .qos.qos_port = 6, 541 .num_links = ARRAY_SIZE(pcnoc_m_1_links), 542 .links = pcnoc_m_1_links, 543}; 544 545static const u16 pcnoc_int_0_links[] = { 546 QNOC_PNOC_SLV_3, 547 QNOC_PNOC_SLV_2, 548 QNOC_PNOC_SLV_1, 549 QNOC_PNOC_SLV_0, 550 QNOC_PNOC_SLV_7, 551 QNOC_PNOC_SLV_5, 552 QNOC_PNOC_SLV_4, 553 QNOC_SLAVE_TCU 554}; 555 556static struct qcom_icc_node pcnoc_int_0 = { 557 .name = "pcnoc_int_0", 558 .id = QNOC_PNOC_INT_0, 559 .buswidth = 8, 560 .mas_rpm_id = 85, 561 .slv_rpm_id = 114, 562 .num_links = ARRAY_SIZE(pcnoc_int_0_links), 563 .links = pcnoc_int_0_links, 564}; 565 566static const u16 pcnoc_int_1_links[] = { 567 QNOC_PNOC_SNOC_SLV 568}; 569 570static struct qcom_icc_node pcnoc_int_1 = { 571 .name = "pcnoc_int_1", 572 .id = QNOC_PNOC_INT_1, 573 .buswidth = 8, 574 .mas_rpm_id = 86, 575 .slv_rpm_id = 115, 576 .num_links = ARRAY_SIZE(pcnoc_int_1_links), 577 .links = pcnoc_int_1_links, 578}; 579 580static const u16 pcnoc_s_0_links[] = { 581 QNOC_SLAVE_SDCC_1, 582 QNOC_SLAVE_TCSR, 583 QNOC_SLAVE_BLSP_1 584}; 585 586static struct qcom_icc_node pcnoc_s_0 = { 587 .name = "pcnoc_s_0", 588 .id = QNOC_PNOC_SLV_0, 589 .buswidth = 4, 590 .mas_rpm_id = 89, 591 .slv_rpm_id = 118, 592 .num_links = ARRAY_SIZE(pcnoc_s_0_links), 593 .links = pcnoc_s_0_links, 594}; 595 596static const u16 pcnoc_s_1_links[] = { 597 QNOC_SLAVE_MESSAGE_RAM, 598 QNOC_SLAVE_CRYPTO_0_CFG, 599 QNOC_SLAVE_USB_HS, 600 QNOC_SLAVE_PDM, 601 QNOC_SLAVE_PRNG, 602 QNOC_SLAVE_QPIC 603}; 604 605static struct qcom_icc_node pcnoc_s_1 = { 606 .name = "pcnoc_s_1", 607 .id = QNOC_PNOC_SLV_1, 608 .buswidth = 4, 609 .mas_rpm_id = 90, 610 .slv_rpm_id = 119, 611 .num_links = ARRAY_SIZE(pcnoc_s_1_links), 612 .links = pcnoc_s_1_links, 613}; 614 615static const u16 pcnoc_s_2_links[] = { 616 QNOC_SLAVE_SPDM, 617 QNOC_SLAVE_SDCC_2, 618 QNOC_SLAVE_AUDIO, 619 QNOC_SLAVE_DEHR_CFG 620}; 621 622static struct qcom_icc_node pcnoc_s_2 = { 623 .name = "pcnoc_s_2", 624 .id = QNOC_PNOC_SLV_2, 625 .buswidth = 4, 626 .mas_rpm_id = 91, 627 .slv_rpm_id = 120, 628 .num_links = ARRAY_SIZE(pcnoc_s_2_links), 629 .links = pcnoc_s_2_links, 630}; 631 632static const u16 pcnoc_s_3_links[] = { 633 QNOC_SLAVE_QDSS_CFG, 634 QNOC_SLAVE_USB_PHYS_CFG, 635 QNOC_SLAVE_SNOC_CFG 636}; 637 638static struct qcom_icc_node pcnoc_s_3 = { 639 .name = "pcnoc_s_3", 640 .id = QNOC_PNOC_SLV_3, 641 .buswidth = 4, 642 .mas_rpm_id = 92, 643 .slv_rpm_id = 121, 644 .num_links = ARRAY_SIZE(pcnoc_s_3_links), 645 .links = pcnoc_s_3_links, 646}; 647 648static const u16 pcnoc_s_4_links[] = { 649 QNOC_SLAVE_CAMERA_CFG, 650 QNOC_SLAVE_DISPLAY_CFG, 651 QNOC_SLAVE_VENUS_CFG 652}; 653 654static struct qcom_icc_node pcnoc_s_4 = { 655 .name = "pcnoc_s_4", 656 .id = QNOC_PNOC_SLV_4, 657 .buswidth = 4, 658 .mas_rpm_id = 93, 659 .slv_rpm_id = 122, 660 .qos.ap_owned = true, 661 .qos.qos_mode = NOC_QOS_MODE_INVALID, 662 .num_links = ARRAY_SIZE(pcnoc_s_4_links), 663 .links = pcnoc_s_4_links, 664}; 665 666static const u16 pcnoc_s_5_links[] = { 667 QNOC_SLAVE_TLMM 668}; 669 670static struct qcom_icc_node pcnoc_s_5 = { 671 .name = "pcnoc_s_5", 672 .id = QNOC_PNOC_SLV_5, 673 .buswidth = 4, 674 .mas_rpm_id = 129, 675 .slv_rpm_id = 189, 676 .num_links = ARRAY_SIZE(pcnoc_s_5_links), 677 .links = pcnoc_s_5_links, 678}; 679 680static const u16 pcnoc_s_7_links[] = { 681 QNOC_SLAVE_GRAPHICS_3D_CFG, 682 QNOC_SLAVE_IMEM_CFG, 683 QNOC_SLAVE_BIMC_CFG, 684 QNOC_SLAVE_PMIC_ARB 685}; 686 687static struct qcom_icc_node pcnoc_s_7 = { 688 .name = "pcnoc_s_7", 689 .id = QNOC_PNOC_SLV_7, 690 .buswidth = 4, 691 .mas_rpm_id = 95, 692 .slv_rpm_id = 124, 693 .num_links = ARRAY_SIZE(pcnoc_s_7_links), 694 .links = pcnoc_s_7_links, 695}; 696 697static const u16 mm_int_0_links[] = { 698 QNOC_SNOC_MM_INT_BIMC 699}; 700 701static struct qcom_icc_node mm_int_0 = { 702 .name = "mm_int_0", 703 .id = QNOC_SNOC_MM_INT_0, 704 .buswidth = 16, 705 .mas_rpm_id = 79, 706 .slv_rpm_id = 108, 707 .qos.ap_owned = true, 708 .qos.qos_mode = NOC_QOS_MODE_INVALID, 709 .num_links = ARRAY_SIZE(mm_int_0_links), 710 .links = mm_int_0_links, 711 .ab_coeff = 167, 712}; 713 714static const u16 mm_int_1_links[] = { 715 QNOC_SNOC_MM_INT_BIMC 716}; 717 718static struct qcom_icc_node mm_int_1 = { 719 .name = "mm_int_1", 720 .id = QNOC_SNOC_MM_INT_1, 721 .buswidth = 16, 722 .mas_rpm_id = 80, 723 .slv_rpm_id = 109, 724 .qos.ap_owned = true, 725 .qos.qos_mode = NOC_QOS_MODE_INVALID, 726 .num_links = ARRAY_SIZE(mm_int_1_links), 727 .links = mm_int_1_links, 728 .ab_coeff = 167, 729}; 730 731static const u16 mm_int_2_links[] = { 732 QNOC_SNOC_INT_0 733}; 734 735static struct qcom_icc_node mm_int_2 = { 736 .name = "mm_int_2", 737 .id = QNOC_SNOC_MM_INT_2, 738 .buswidth = 16, 739 .mas_rpm_id = 81, 740 .slv_rpm_id = 110, 741 .qos.ap_owned = true, 742 .qos.qos_mode = NOC_QOS_MODE_INVALID, 743 .num_links = ARRAY_SIZE(mm_int_2_links), 744 .links = mm_int_2_links, 745 .ab_coeff = 167, 746}; 747 748static const u16 mm_int_bimc_links[] = { 749 QNOC_SNOC_BIMC_1_SLV 750}; 751 752static struct qcom_icc_node mm_int_bimc = { 753 .name = "mm_int_bimc", 754 .id = QNOC_SNOC_MM_INT_BIMC, 755 .buswidth = 16, 756 .mas_rpm_id = 82, 757 .slv_rpm_id = 111, 758 .qos.ap_owned = true, 759 .qos.qos_mode = NOC_QOS_MODE_INVALID, 760 .num_links = ARRAY_SIZE(mm_int_bimc_links), 761 .links = mm_int_bimc_links, 762 .ab_coeff = 167, 763}; 764 765static const u16 qdss_int_links[] = { 766 QNOC_SNOC_INT_0, 767 QNOC_SNOC_INT_BIMC 768}; 769 770static struct qcom_icc_node qdss_int = { 771 .name = "qdss_int", 772 .id = QNOC_SNOC_QDSS_INT, 773 .buswidth = 8, 774 .mas_rpm_id = 98, 775 .slv_rpm_id = 128, 776 .qos.ap_owned = true, 777 .qos.qos_mode = NOC_QOS_MODE_INVALID, 778 .num_links = ARRAY_SIZE(qdss_int_links), 779 .links = qdss_int_links, 780}; 781 782static const u16 snoc_int_0_links[] = { 783 QNOC_SLAVE_SYSTEM_IMEM, 784 QNOC_SLAVE_QDSS_STM, 785 QNOC_SNOC_PNOC_SLV 786}; 787 788static struct qcom_icc_node snoc_int_0 = { 789 .name = "snoc_int_0", 790 .id = QNOC_SNOC_INT_0, 791 .buswidth = 8, 792 .mas_rpm_id = 99, 793 .slv_rpm_id = 130, 794 .num_links = ARRAY_SIZE(snoc_int_0_links), 795 .links = snoc_int_0_links, 796}; 797 798static const u16 snoc_int_1_links[] = { 799 QNOC_SLAVE_CATS_128, 800 QNOC_SLAVE_APPSS, 801 QNOC_SLAVE_OCMEM_64 802}; 803 804static struct qcom_icc_node snoc_int_1 = { 805 .name = "snoc_int_1", 806 .id = QNOC_SNOC_INT_1, 807 .buswidth = 8, 808 .mas_rpm_id = 100, 809 .slv_rpm_id = 131, 810 .qos.ap_owned = true, 811 .qos.qos_mode = NOC_QOS_MODE_INVALID, 812 .num_links = ARRAY_SIZE(snoc_int_1_links), 813 .links = snoc_int_1_links, 814}; 815 816static const u16 snoc_int_bimc_links[] = { 817 QNOC_SNOC_BIMC_0_SLV 818}; 819 820static struct qcom_icc_node snoc_int_bimc = { 821 .name = "snoc_int_bimc", 822 .id = QNOC_SNOC_INT_BIMC, 823 .buswidth = 8, 824 .mas_rpm_id = 101, 825 .slv_rpm_id = 132, 826 .num_links = ARRAY_SIZE(snoc_int_bimc_links), 827 .links = snoc_int_bimc_links, 828}; 829 830static struct qcom_icc_node slv_ebi = { 831 .name = "slv_ebi", 832 .id = QNOC_SLAVE_EBI_CH0, 833 .buswidth = 8, 834 .mas_rpm_id = -1, 835 .slv_rpm_id = 0, 836}; 837 838static const u16 slv_bimc_snoc_links[] = { 839 QNOC_BIMC_SNOC_MAS 840}; 841 842static struct qcom_icc_node slv_bimc_snoc = { 843 .name = "slv_bimc_snoc", 844 .id = QNOC_BIMC_SNOC_SLV, 845 .buswidth = 8, 846 .mas_rpm_id = -1, 847 .slv_rpm_id = 2, 848 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 849 .links = slv_bimc_snoc_links, 850}; 851 852static struct qcom_icc_node slv_tcsr = { 853 .name = "slv_tcsr", 854 .id = QNOC_SLAVE_TCSR, 855 .buswidth = 4, 856 .mas_rpm_id = -1, 857 .slv_rpm_id = 50, 858}; 859 860static struct qcom_icc_node slv_sdcc_1 = { 861 .name = "slv_sdcc_1", 862 .id = QNOC_SLAVE_SDCC_1, 863 .buswidth = 4, 864 .mas_rpm_id = -1, 865 .slv_rpm_id = 31, 866}; 867 868static struct qcom_icc_node slv_blsp_1 = { 869 .name = "slv_blsp_1", 870 .id = QNOC_SLAVE_BLSP_1, 871 .buswidth = 4, 872 .mas_rpm_id = -1, 873 .slv_rpm_id = 39, 874}; 875 876static struct qcom_icc_node slv_crypto_0_cfg = { 877 .name = "slv_crypto_0_cfg", 878 .id = QNOC_SLAVE_CRYPTO_0_CFG, 879 .buswidth = 4, 880 .mas_rpm_id = -1, 881 .slv_rpm_id = 52, 882 .qos.ap_owned = true, 883 .qos.qos_mode = NOC_QOS_MODE_INVALID, 884}; 885 886static struct qcom_icc_node slv_message_ram = { 887 .name = "slv_message_ram", 888 .id = QNOC_SLAVE_MESSAGE_RAM, 889 .buswidth = 4, 890 .mas_rpm_id = -1, 891 .slv_rpm_id = 55, 892}; 893 894static struct qcom_icc_node slv_pdm = { 895 .name = "slv_pdm", 896 .id = QNOC_SLAVE_PDM, 897 .buswidth = 4, 898 .mas_rpm_id = -1, 899 .slv_rpm_id = 41, 900}; 901 902static struct qcom_icc_node slv_prng = { 903 .name = "slv_prng", 904 .id = QNOC_SLAVE_PRNG, 905 .buswidth = 4, 906 .mas_rpm_id = -1, 907 .slv_rpm_id = 44, 908 .qos.ap_owned = true, 909 .qos.qos_mode = NOC_QOS_MODE_INVALID, 910}; 911 912static struct qcom_icc_node slv_usb_hs = { 913 .name = "slv_usb_hs", 914 .id = QNOC_SLAVE_USB_HS, 915 .buswidth = 4, 916 .mas_rpm_id = -1, 917 .slv_rpm_id = 40, 918}; 919 920static struct qcom_icc_node slv_qpic = { 921 .name = "slv_qpic", 922 .id = QNOC_SLAVE_QPIC, 923 .buswidth = 4, 924 .mas_rpm_id = -1, 925 .slv_rpm_id = 80, 926}; 927 928static struct qcom_icc_node slv_spdm = { 929 .name = "slv_spdm", 930 .id = QNOC_SLAVE_SPDM, 931 .buswidth = 4, 932 .mas_rpm_id = -1, 933 .slv_rpm_id = 60, 934}; 935 936static struct qcom_icc_node slv_sdcc_2 = { 937 .name = "slv_sdcc_2", 938 .id = QNOC_SLAVE_SDCC_2, 939 .buswidth = 4, 940 .mas_rpm_id = -1, 941 .slv_rpm_id = 33, 942}; 943 944static struct qcom_icc_node slv_audio = { 945 .name = "slv_audio", 946 .id = QNOC_SLAVE_AUDIO, 947 .buswidth = 4, 948 .mas_rpm_id = -1, 949 .slv_rpm_id = 105, 950}; 951 952static struct qcom_icc_node slv_dehr_cfg = { 953 .name = "slv_dehr_cfg", 954 .id = QNOC_SLAVE_DEHR_CFG, 955 .buswidth = 4, 956 .mas_rpm_id = -1, 957 .slv_rpm_id = 61, 958}; 959 960static struct qcom_icc_node slv_snoc_cfg = { 961 .name = "slv_snoc_cfg", 962 .id = QNOC_SLAVE_SNOC_CFG, 963 .buswidth = 4, 964 .mas_rpm_id = -1, 965 .slv_rpm_id = 70, 966}; 967 968static struct qcom_icc_node slv_qdss_cfg = { 969 .name = "slv_qdss_cfg", 970 .id = QNOC_SLAVE_QDSS_CFG, 971 .buswidth = 4, 972 .mas_rpm_id = -1, 973 .slv_rpm_id = 63, 974}; 975 976static struct qcom_icc_node slv_usb_phy = { 977 .name = "slv_usb_phy", 978 .id = QNOC_SLAVE_USB_PHYS_CFG, 979 .buswidth = 4, 980 .mas_rpm_id = -1, 981 .slv_rpm_id = 95, 982}; 983 984static struct qcom_icc_node slv_camera_ss_cfg = { 985 .name = "slv_camera_ss_cfg", 986 .id = QNOC_SLAVE_CAMERA_CFG, 987 .buswidth = 4, 988 .mas_rpm_id = -1, 989 .slv_rpm_id = 3, 990 .qos.ap_owned = true, 991 .qos.qos_mode = NOC_QOS_MODE_INVALID, 992}; 993 994static struct qcom_icc_node slv_disp_ss_cfg = { 995 .name = "slv_disp_ss_cfg", 996 .id = QNOC_SLAVE_DISPLAY_CFG, 997 .buswidth = 4, 998 .mas_rpm_id = -1, 999 .slv_rpm_id = 4, 1000 .qos.ap_owned = true, 1001 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1002}; 1003 1004static struct qcom_icc_node slv_venus_cfg = { 1005 .name = "slv_venus_cfg", 1006 .id = QNOC_SLAVE_VENUS_CFG, 1007 .buswidth = 4, 1008 .mas_rpm_id = -1, 1009 .slv_rpm_id = 10, 1010 .qos.ap_owned = true, 1011 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1012}; 1013 1014static struct qcom_icc_node slv_tlmm = { 1015 .name = "slv_tlmm", 1016 .id = QNOC_SLAVE_TLMM, 1017 .buswidth = 4, 1018 .mas_rpm_id = -1, 1019 .slv_rpm_id = 51, 1020}; 1021 1022static struct qcom_icc_node slv_gpu_cfg = { 1023 .name = "slv_gpu_cfg", 1024 .id = QNOC_SLAVE_GRAPHICS_3D_CFG, 1025 .buswidth = 4, 1026 .mas_rpm_id = -1, 1027 .slv_rpm_id = 11, 1028 .qos.ap_owned = true, 1029 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1030}; 1031 1032static struct qcom_icc_node slv_imem_cfg = { 1033 .name = "slv_imem_cfg", 1034 .id = QNOC_SLAVE_IMEM_CFG, 1035 .buswidth = 4, 1036 .mas_rpm_id = -1, 1037 .slv_rpm_id = 54, 1038}; 1039 1040static struct qcom_icc_node slv_bimc_cfg = { 1041 .name = "slv_bimc_cfg", 1042 .id = QNOC_SLAVE_BIMC_CFG, 1043 .buswidth = 4, 1044 .mas_rpm_id = -1, 1045 .slv_rpm_id = 56, 1046}; 1047 1048static struct qcom_icc_node slv_pmic_arb = { 1049 .name = "slv_pmic_arb", 1050 .id = QNOC_SLAVE_PMIC_ARB, 1051 .buswidth = 4, 1052 .mas_rpm_id = -1, 1053 .slv_rpm_id = 59, 1054}; 1055 1056static struct qcom_icc_node slv_tcu = { 1057 .name = "slv_tcu", 1058 .id = QNOC_SLAVE_TCU, 1059 .buswidth = 8, 1060 .mas_rpm_id = -1, 1061 .slv_rpm_id = 133, 1062 .qos.ap_owned = true, 1063 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1064}; 1065 1066static const u16 slv_pcnoc_snoc_links[] = { 1067 QNOC_PNOC_SNOC_MAS 1068}; 1069 1070static struct qcom_icc_node slv_pcnoc_snoc = { 1071 .name = "slv_pcnoc_snoc", 1072 .id = QNOC_PNOC_SNOC_SLV, 1073 .buswidth = 8, 1074 .mas_rpm_id = -1, 1075 .slv_rpm_id = 45, 1076 .num_links = ARRAY_SIZE(slv_pcnoc_snoc_links), 1077 .links = slv_pcnoc_snoc_links, 1078}; 1079 1080static struct qcom_icc_node slv_kpss_ahb = { 1081 .name = "slv_kpss_ahb", 1082 .id = QNOC_SLAVE_APPSS, 1083 .buswidth = 4, 1084 .mas_rpm_id = -1, 1085 .slv_rpm_id = 20, 1086 .qos.ap_owned = true, 1087 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1088}; 1089 1090static const u16 slv_snoc_bimc_0_links[] = { 1091 QNOC_SNOC_BIMC_0_MAS 1092}; 1093 1094static struct qcom_icc_node slv_snoc_bimc_0 = { 1095 .name = "slv_snoc_bimc_0", 1096 .id = QNOC_SNOC_BIMC_0_SLV, 1097 .buswidth = 8, 1098 .mas_rpm_id = -1, 1099 .slv_rpm_id = 24, 1100 .num_links = ARRAY_SIZE(slv_snoc_bimc_0_links), 1101 .links = slv_snoc_bimc_0_links, 1102}; 1103 1104static const u16 slv_snoc_bimc_1_links[] = { 1105 QNOC_SNOC_BIMC_1_MAS 1106}; 1107 1108static struct qcom_icc_node slv_snoc_bimc_1 = { 1109 .name = "slv_snoc_bimc_1", 1110 .id = QNOC_SNOC_BIMC_1_SLV, 1111 .buswidth = 16, 1112 .mas_rpm_id = -1, 1113 .slv_rpm_id = 104, 1114 .qos.ap_owned = true, 1115 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1116 .num_links = ARRAY_SIZE(slv_snoc_bimc_1_links), 1117 .links = slv_snoc_bimc_1_links, 1118}; 1119 1120static struct qcom_icc_node slv_imem = { 1121 .name = "slv_imem", 1122 .id = QNOC_SLAVE_SYSTEM_IMEM, 1123 .buswidth = 8, 1124 .mas_rpm_id = -1, 1125 .slv_rpm_id = 26, 1126}; 1127 1128static const u16 slv_snoc_pcnoc_links[] = { 1129 QNOC_SNOC_PNOC_MAS 1130}; 1131 1132static struct qcom_icc_node slv_snoc_pcnoc = { 1133 .name = "slv_snoc_pcnoc", 1134 .id = QNOC_SNOC_PNOC_SLV, 1135 .buswidth = 8, 1136 .mas_rpm_id = -1, 1137 .slv_rpm_id = 28, 1138 .num_links = ARRAY_SIZE(slv_snoc_pcnoc_links), 1139 .links = slv_snoc_pcnoc_links, 1140}; 1141 1142static struct qcom_icc_node slv_qdss_stm = { 1143 .name = "slv_qdss_stm", 1144 .id = QNOC_SLAVE_QDSS_STM, 1145 .buswidth = 4, 1146 .mas_rpm_id = -1, 1147 .slv_rpm_id = 30, 1148}; 1149 1150static struct qcom_icc_node slv_cats_0 = { 1151 .name = "slv_cats_0", 1152 .id = QNOC_SLAVE_CATS_128, 1153 .buswidth = 16, 1154 .mas_rpm_id = -1, 1155 .slv_rpm_id = 106, 1156 .qos.ap_owned = true, 1157 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1158}; 1159 1160static struct qcom_icc_node slv_cats_1 = { 1161 .name = "slv_cats_1", 1162 .id = QNOC_SLAVE_OCMEM_64, 1163 .buswidth = 8, 1164 .mas_rpm_id = -1, 1165 .slv_rpm_id = 107, 1166 .qos.ap_owned = true, 1167 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1168}; 1169 1170static struct qcom_icc_node * const msm8909_bimc_nodes[] = { 1171 [MAS_APPS_PROC] = &mas_apps_proc, 1172 [MAS_OXILI] = &mas_oxili, 1173 [MAS_SNOC_BIMC_0] = &mas_snoc_bimc_0, 1174 [MAS_SNOC_BIMC_1] = &mas_snoc_bimc_1, 1175 [MAS_TCU_0] = &mas_tcu_0, 1176 [MAS_TCU_1] = &mas_tcu_1, 1177 [SLV_EBI] = &slv_ebi, 1178 [SLV_BIMC_SNOC] = &slv_bimc_snoc, 1179}; 1180 1181static const struct regmap_config msm8909_bimc_regmap_config = { 1182 .reg_bits = 32, 1183 .reg_stride = 4, 1184 .val_bits = 32, 1185 .max_register = 0x62000, 1186 .fast_io = true, 1187}; 1188 1189static const struct qcom_icc_desc msm8909_bimc = { 1190 .type = QCOM_ICC_BIMC, 1191 .nodes = msm8909_bimc_nodes, 1192 .num_nodes = ARRAY_SIZE(msm8909_bimc_nodes), 1193 .bus_clk_desc = &bimc_clk, 1194 .regmap_cfg = &msm8909_bimc_regmap_config, 1195 .qos_offset = 0x8000, 1196 .ab_coeff = 154, 1197}; 1198 1199static struct qcom_icc_node * const msm8909_pcnoc_nodes[] = { 1200 [MAS_AUDIO] = &mas_audio, 1201 [MAS_SPDM] = &mas_spdm, 1202 [MAS_DEHR] = &mas_dehr, 1203 [MAS_QPIC] = &mas_qpic, 1204 [MAS_BLSP_1] = &mas_blsp_1, 1205 [MAS_USB_HS] = &mas_usb_hs, 1206 [MAS_CRYPTO] = &mas_crypto, 1207 [MAS_SDCC_1] = &mas_sdcc_1, 1208 [MAS_SDCC_2] = &mas_sdcc_2, 1209 [MAS_SNOC_PCNOC] = &mas_snoc_pcnoc, 1210 [PCNOC_M_0] = &pcnoc_m_0, 1211 [PCNOC_M_1] = &pcnoc_m_1, 1212 [PCNOC_INT_0] = &pcnoc_int_0, 1213 [PCNOC_INT_1] = &pcnoc_int_1, 1214 [PCNOC_S_0] = &pcnoc_s_0, 1215 [PCNOC_S_1] = &pcnoc_s_1, 1216 [PCNOC_S_2] = &pcnoc_s_2, 1217 [PCNOC_S_3] = &pcnoc_s_3, 1218 [PCNOC_S_4] = &pcnoc_s_4, 1219 [PCNOC_S_5] = &pcnoc_s_5, 1220 [PCNOC_S_7] = &pcnoc_s_7, 1221 [SLV_TCSR] = &slv_tcsr, 1222 [SLV_SDCC_1] = &slv_sdcc_1, 1223 [SLV_BLSP_1] = &slv_blsp_1, 1224 [SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1225 [SLV_MESSAGE_RAM] = &slv_message_ram, 1226 [SLV_PDM] = &slv_pdm, 1227 [SLV_PRNG] = &slv_prng, 1228 [SLV_USB_HS] = &slv_usb_hs, 1229 [SLV_QPIC] = &slv_qpic, 1230 [SLV_SPDM] = &slv_spdm, 1231 [SLV_SDCC_2] = &slv_sdcc_2, 1232 [SLV_AUDIO] = &slv_audio, 1233 [SLV_DEHR_CFG] = &slv_dehr_cfg, 1234 [SLV_SNOC_CFG] = &slv_snoc_cfg, 1235 [SLV_QDSS_CFG] = &slv_qdss_cfg, 1236 [SLV_USB_PHY] = &slv_usb_phy, 1237 [SLV_CAMERA_SS_CFG] = &slv_camera_ss_cfg, 1238 [SLV_DISP_SS_CFG] = &slv_disp_ss_cfg, 1239 [SLV_VENUS_CFG] = &slv_venus_cfg, 1240 [SLV_TLMM] = &slv_tlmm, 1241 [SLV_GPU_CFG] = &slv_gpu_cfg, 1242 [SLV_IMEM_CFG] = &slv_imem_cfg, 1243 [SLV_BIMC_CFG] = &slv_bimc_cfg, 1244 [SLV_PMIC_ARB] = &slv_pmic_arb, 1245 [SLV_TCU] = &slv_tcu, 1246 [SLV_PCNOC_SNOC] = &slv_pcnoc_snoc, 1247}; 1248 1249static const struct regmap_config msm8909_pcnoc_regmap_config = { 1250 .reg_bits = 32, 1251 .reg_stride = 4, 1252 .val_bits = 32, 1253 .max_register = 0x11000, 1254 .fast_io = true, 1255}; 1256 1257static const struct qcom_icc_desc msm8909_pcnoc = { 1258 .type = QCOM_ICC_NOC, 1259 .nodes = msm8909_pcnoc_nodes, 1260 .num_nodes = ARRAY_SIZE(msm8909_pcnoc_nodes), 1261 .bus_clk_desc = &bus_0_clk, 1262 .regmap_cfg = &msm8909_pcnoc_regmap_config, 1263 .qos_offset = 0x7000, 1264}; 1265 1266static struct qcom_icc_node * const msm8909_snoc_nodes[] = { 1267 [MAS_QDSS_BAM] = &mas_qdss_bam, 1268 [MAS_BIMC_SNOC] = &mas_bimc_snoc, 1269 [MAS_MDP] = &mas_mdp, 1270 [MAS_PCNOC_SNOC] = &mas_pcnoc_snoc, 1271 [MAS_VENUS] = &mas_venus, 1272 [MAS_VFE] = &mas_vfe, 1273 [MAS_QDSS_ETR] = &mas_qdss_etr, 1274 [MM_INT_0] = &mm_int_0, 1275 [MM_INT_1] = &mm_int_1, 1276 [MM_INT_2] = &mm_int_2, 1277 [MM_INT_BIMC] = &mm_int_bimc, 1278 [QDSS_INT] = &qdss_int, 1279 [SNOC_INT_0] = &snoc_int_0, 1280 [SNOC_INT_1] = &snoc_int_1, 1281 [SNOC_INT_BIMC] = &snoc_int_bimc, 1282 [SLV_KPSS_AHB] = &slv_kpss_ahb, 1283 [SLV_SNOC_BIMC_0] = &slv_snoc_bimc_0, 1284 [SLV_SNOC_BIMC_1] = &slv_snoc_bimc_1, 1285 [SLV_IMEM] = &slv_imem, 1286 [SLV_SNOC_PCNOC] = &slv_snoc_pcnoc, 1287 [SLV_QDSS_STM] = &slv_qdss_stm, 1288 [SLV_CATS_0] = &slv_cats_0, 1289 [SLV_CATS_1] = &slv_cats_1, 1290}; 1291 1292static const struct regmap_config msm8909_snoc_regmap_config = { 1293 .reg_bits = 32, 1294 .reg_stride = 4, 1295 .val_bits = 32, 1296 .max_register = 0x13000, 1297 .fast_io = true, 1298}; 1299 1300static const struct qcom_icc_desc msm8909_snoc = { 1301 .type = QCOM_ICC_NOC, 1302 .nodes = msm8909_snoc_nodes, 1303 .num_nodes = ARRAY_SIZE(msm8909_snoc_nodes), 1304 .bus_clk_desc = &bus_1_clk, 1305 .regmap_cfg = &msm8909_snoc_regmap_config, 1306 .qos_offset = 0x7000, 1307}; 1308 1309static const struct of_device_id msm8909_noc_of_match[] = { 1310 { .compatible = "qcom,msm8909-bimc", .data = &msm8909_bimc }, 1311 { .compatible = "qcom,msm8909-pcnoc", .data = &msm8909_pcnoc }, 1312 { .compatible = "qcom,msm8909-snoc", .data = &msm8909_snoc }, 1313 { } 1314}; 1315MODULE_DEVICE_TABLE(of, msm8909_noc_of_match); 1316 1317static struct platform_driver msm8909_noc_driver = { 1318 .probe = qnoc_probe, 1319 .remove_new = qnoc_remove, 1320 .driver = { 1321 .name = "qnoc-msm8909", 1322 .of_match_table = msm8909_noc_of_match, 1323 .sync_state = icc_sync_state, 1324 }, 1325}; 1326module_platform_driver(msm8909_noc_driver); 1327 1328MODULE_DESCRIPTION("Qualcomm MSM8909 NoC driver"); 1329MODULE_LICENSE("GPL"); 1330