1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright(c) 2015 - 2020 Intel Corporation.
4 */
5
6#ifndef _COMMON_H
7#define _COMMON_H
8
9#include <rdma/hfi/hfi1_user.h>
10
11/*
12 * This file contains defines, structures, etc. that are used
13 * to communicate between kernel and user code.
14 */
15
16/* version of protocol header (known to chip also). In the long run,
17 * we should be able to generate and accept a range of version numbers;
18 * for now we only accept one, and it's compiled in.
19 */
20#define IPS_PROTO_VERSION 2
21
22/*
23 * These are compile time constants that you may want to enable or disable
24 * if you are trying to debug problems with code or performance.
25 * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
26 * fast path code
27 * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
28 * traced in fast path code
29 * _HFI1_TRACING define as 0 if you want to remove all tracing in a
30 * compilation unit
31 */
32
33/* driver/hw feature set bitmask */
34#define HFI1_CAP_USER_SHIFT      24
35#define HFI1_CAP_MASK            ((1UL << HFI1_CAP_USER_SHIFT) - 1)
36/* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
37#define HFI1_CAP_LOCKED_SHIFT    63
38#define HFI1_CAP_LOCKED_MASK     0x1ULL
39#define HFI1_CAP_LOCKED_SMASK    (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
40/* extra bits used between kernel and user processes */
41#define HFI1_CAP_MISC_SHIFT      (HFI1_CAP_USER_SHIFT * 2)
42#define HFI1_CAP_MISC_MASK       ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
43					   HFI1_CAP_MISC_SHIFT)) - 1)
44
45#define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; })
46#define HFI1_CAP_KCLEAR(cap)						\
47	({								\
48		hfi1_cap_mask &= ~HFI1_CAP_##cap;			\
49		hfi1_cap_mask;						\
50	})
51#define HFI1_CAP_USET(cap)						\
52	({								\
53		hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
54		hfi1_cap_mask;						\
55		})
56#define HFI1_CAP_UCLEAR(cap)						\
57	({								\
58		hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
59		hfi1_cap_mask;						\
60	})
61#define HFI1_CAP_SET(cap)						\
62	({								\
63		hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap <<	\
64						  HFI1_CAP_USER_SHIFT)); \
65		hfi1_cap_mask;						\
66	})
67#define HFI1_CAP_CLEAR(cap)						\
68	({								\
69		hfi1_cap_mask &= ~(HFI1_CAP_##cap |			\
70				  (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
71		hfi1_cap_mask;						\
72	})
73#define HFI1_CAP_LOCK()							\
74	({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
75#define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
76/*
77 * The set of capability bits that can be changed after initial load
78 * This set is the same for kernel and user contexts. However, for
79 * user contexts, the set can be further filtered by using the
80 * HFI1_CAP_RESERVED_MASK bits.
81 */
82#define HFI1_CAP_WRITABLE_MASK   (HFI1_CAP_SDMA_AHG |			\
83				  HFI1_CAP_HDRSUPP |			\
84				  HFI1_CAP_MULTI_PKT_EGR |		\
85				  HFI1_CAP_NODROP_RHQ_FULL |		\
86				  HFI1_CAP_NODROP_EGR_FULL |		\
87				  HFI1_CAP_ALLOW_PERM_JKEY |		\
88				  HFI1_CAP_STATIC_RATE_CTRL |		\
89				  HFI1_CAP_PRINT_UNIMPL |		\
90				  HFI1_CAP_TID_UNMAP |			\
91				  HFI1_CAP_OPFN)
92/*
93 * A set of capability bits that are "global" and are not allowed to be
94 * set in the user bitmask.
95 */
96#define HFI1_CAP_RESERVED_MASK   ((HFI1_CAP_SDMA |			\
97				   HFI1_CAP_USE_SDMA_HEAD |		\
98				   HFI1_CAP_EXTENDED_PSN |		\
99				   HFI1_CAP_PRINT_UNIMPL |		\
100				   HFI1_CAP_NO_INTEGRITY |		\
101				   HFI1_CAP_PKEY_CHECK |		\
102				   HFI1_CAP_TID_RDMA |			\
103				   HFI1_CAP_OPFN |			\
104				   HFI1_CAP_AIP) <<			\
105				  HFI1_CAP_USER_SHIFT)
106/*
107 * Set of capabilities that need to be enabled for kernel context in
108 * order to be allowed for user contexts, as well.
109 */
110#define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
111/* Default enabled capabilities (both kernel and user) */
112#define HFI1_CAP_MASK_DEFAULT    (HFI1_CAP_HDRSUPP |			\
113				 HFI1_CAP_NODROP_RHQ_FULL |		\
114				 HFI1_CAP_NODROP_EGR_FULL |		\
115				 HFI1_CAP_SDMA |			\
116				 HFI1_CAP_PRINT_UNIMPL |		\
117				 HFI1_CAP_STATIC_RATE_CTRL |		\
118				 HFI1_CAP_PKEY_CHECK |			\
119				 HFI1_CAP_MULTI_PKT_EGR |		\
120				 HFI1_CAP_EXTENDED_PSN |		\
121				 HFI1_CAP_AIP |				\
122				 ((HFI1_CAP_HDRSUPP |			\
123				   HFI1_CAP_MULTI_PKT_EGR |		\
124				   HFI1_CAP_STATIC_RATE_CTRL |		\
125				   HFI1_CAP_PKEY_CHECK |		\
126				   HFI1_CAP_EARLY_CREDIT_RETURN) <<	\
127				  HFI1_CAP_USER_SHIFT))
128/*
129 * A bitmask of kernel/global capabilities that should be communicated
130 * to user level processes.
131 */
132#define HFI1_CAP_K2U (HFI1_CAP_SDMA |			\
133		     HFI1_CAP_EXTENDED_PSN |		\
134		     HFI1_CAP_PKEY_CHECK |		\
135		     HFI1_CAP_NO_INTEGRITY)
136
137#define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << HFI1_SWMAJOR_SHIFT) | \
138			     HFI1_USER_SWMINOR)
139
140/*
141 * The next set of defines are for packet headers, and chip register
142 * and memory bits that are visible to and/or used by user-mode software.
143 */
144
145/*
146 * Receive Header Flags
147 */
148#define RHF_PKT_LEN_SHIFT	0
149#define RHF_PKT_LEN_MASK	0xfffull
150#define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)
151
152#define RHF_RCV_TYPE_SHIFT	12
153#define RHF_RCV_TYPE_MASK	0x7ull
154#define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)
155
156#define RHF_USE_EGR_BFR_SHIFT	15
157#define RHF_USE_EGR_BFR_MASK	0x1ull
158#define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)
159
160#define RHF_EGR_INDEX_SHIFT	16
161#define RHF_EGR_INDEX_MASK	0x7ffull
162#define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)
163
164#define RHF_DC_INFO_SHIFT	27
165#define RHF_DC_INFO_MASK	0x1ull
166#define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)
167
168#define RHF_RCV_SEQ_SHIFT	28
169#define RHF_RCV_SEQ_MASK	0xfull
170#define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)
171
172#define RHF_EGR_OFFSET_SHIFT	32
173#define RHF_EGR_OFFSET_MASK	0xfffull
174#define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
175#define RHF_HDRQ_OFFSET_SHIFT	44
176#define RHF_HDRQ_OFFSET_MASK	0x1ffull
177#define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
178#define RHF_K_HDR_LEN_ERR	(0x1ull << 53)
179#define RHF_DC_UNC_ERR		(0x1ull << 54)
180#define RHF_DC_ERR		(0x1ull << 55)
181#define RHF_RCV_TYPE_ERR_SHIFT	56
182#define RHF_RCV_TYPE_ERR_MASK	0x7ul
183#define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
184#define RHF_TID_ERR		(0x1ull << 59)
185#define RHF_LEN_ERR		(0x1ull << 60)
186#define RHF_ECC_ERR		(0x1ull << 61)
187#define RHF_RESERVED		(0x1ull << 62)
188#define RHF_ICRC_ERR		(0x1ull << 63)
189
190#define RHF_ERROR_SMASK 0xffe0000000000000ull		/* bits 63:53 */
191
192/* RHF receive types */
193#define RHF_RCV_TYPE_EXPECTED 0
194#define RHF_RCV_TYPE_EAGER    1
195#define RHF_RCV_TYPE_IB       2 /* normal IB, IB Raw, or IPv6 */
196#define RHF_RCV_TYPE_ERROR    3
197#define RHF_RCV_TYPE_BYPASS   4
198#define RHF_RCV_TYPE_INVALID5 5
199#define RHF_RCV_TYPE_INVALID6 6
200#define RHF_RCV_TYPE_INVALID7 7
201
202/* RHF receive type error - expected packet errors */
203#define RHF_RTE_EXPECTED_FLOW_SEQ_ERR	0x2
204#define RHF_RTE_EXPECTED_FLOW_GEN_ERR	0x4
205
206/* RHF receive type error - eager packet errors */
207#define RHF_RTE_EAGER_NO_ERR		0x0
208
209/* RHF receive type error - IB packet errors */
210#define RHF_RTE_IB_NO_ERR		0x0
211
212/* RHF receive type error - error packet errors */
213#define RHF_RTE_ERROR_NO_ERR		0x0
214#define RHF_RTE_ERROR_OP_CODE_ERR	0x1
215#define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR	0x2
216#define RHF_RTE_ERROR_KHDR_HCRC_ERR	0x3
217#define RHF_RTE_ERROR_KHDR_KVER_ERR	0x4
218#define RHF_RTE_ERROR_CONTEXT_ERR	0x5
219#define RHF_RTE_ERROR_KHDR_TID_ERR	0x6
220
221/* RHF receive type error - bypass packet errors */
222#define RHF_RTE_BYPASS_NO_ERR		0x0
223
224/* MAX RcvSEQ */
225#define RHF_MAX_SEQ 13
226
227/* IB - LRH header constants */
228#define HFI1_LRH_GRH 0x0003      /* 1. word of IB LRH - next header: GRH */
229#define HFI1_LRH_BTH 0x0002      /* 1. word of IB LRH - next header: BTH */
230
231/* misc. */
232#define SC15_PACKET 0xF
233#define SIZE_OF_CRC 1
234#define SIZE_OF_LT 1
235#define MAX_16B_PADDING 12 /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */
236
237#define LIM_MGMT_P_KEY       0x7FFF
238#define FULL_MGMT_P_KEY      0xFFFF
239
240#define DEFAULT_P_KEY LIM_MGMT_P_KEY
241
242#define HFI1_PSM_IOC_BASE_SEQ 0x0
243
244/* Number of BTH.PSN bits used for sequence number in expected rcvs */
245#define HFI1_KDETH_BTH_SEQ_SHIFT 11
246#define HFI1_KDETH_BTH_SEQ_MASK (BIT(HFI1_KDETH_BTH_SEQ_SHIFT) - 1)
247
248static inline __u64 rhf_to_cpu(const __le32 *rbuf)
249{
250	return __le64_to_cpu(*((__le64 *)rbuf));
251}
252
253static inline u64 rhf_err_flags(u64 rhf)
254{
255	return rhf & RHF_ERROR_SMASK;
256}
257
258static inline u32 rhf_rcv_type(u64 rhf)
259{
260	return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
261}
262
263static inline u32 rhf_rcv_type_err(u64 rhf)
264{
265	return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
266}
267
268/* return size is in bytes, not DWORDs */
269static inline u32 rhf_pkt_len(u64 rhf)
270{
271	return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
272}
273
274static inline u32 rhf_egr_index(u64 rhf)
275{
276	return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
277}
278
279static inline u32 rhf_rcv_seq(u64 rhf)
280{
281	return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
282}
283
284/* returned offset is in DWORDS */
285static inline u32 rhf_hdrq_offset(u64 rhf)
286{
287	return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
288}
289
290static inline u64 rhf_use_egr_bfr(u64 rhf)
291{
292	return rhf & RHF_USE_EGR_BFR_SMASK;
293}
294
295static inline u64 rhf_dc_info(u64 rhf)
296{
297	return rhf & RHF_DC_INFO_SMASK;
298}
299
300static inline u32 rhf_egr_buf_offset(u64 rhf)
301{
302	return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
303}
304#endif /* _COMMON_H */
305