1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2022 Richtek Technology Corp. 4 * 5 * ChiYuan Huang <cy_huang@richtek.com> 6 */ 7 8#include <linux/bitops.h> 9#include <linux/delay.h> 10#include <linux/i2c.h> 11#include <linux/kernel.h> 12#include <linux/mod_devicetable.h> 13#include <linux/module.h> 14#include <linux/pm_runtime.h> 15#include <linux/property.h> 16#include <linux/regmap.h> 17#include <linux/sysfs.h> 18#include <linux/types.h> 19#include <linux/util_macros.h> 20 21#include <linux/iio/buffer.h> 22#include <linux/iio/iio.h> 23#include <linux/iio/sysfs.h> 24#include <linux/iio/trigger_consumer.h> 25#include <linux/iio/triggered_buffer.h> 26 27#define RTQ6056_REG_CONFIG 0x00 28#define RTQ6056_REG_SHUNTVOLT 0x01 29#define RTQ6056_REG_BUSVOLT 0x02 30#define RTQ6056_REG_POWER 0x03 31#define RTQ6056_REG_CURRENT 0x04 32#define RTQ6056_REG_CALIBRATION 0x05 33#define RTQ6056_REG_MASKENABLE 0x06 34#define RTQ6056_REG_ALERTLIMIT 0x07 35#define RTQ6056_REG_MANUFACTID 0xFE 36#define RTQ6056_REG_DIEID 0xFF 37 38#define RTQ6056_VENDOR_ID 0x1214 39#define RTQ6056_DEFAULT_CONFIG 0x4127 40#define RTQ6056_CONT_ALLON 7 41 42#define RTQ6059_DEFAULT_CONFIG 0x3C47 43#define RTQ6059_VBUS_LSB_OFFSET 3 44#define RTQ6059_AVG_BASE 8 45 46enum { 47 RTQ6056_CH_VSHUNT = 0, 48 RTQ6056_CH_VBUS, 49 RTQ6056_CH_POWER, 50 RTQ6056_CH_CURRENT, 51 RTQ6056_MAX_CHANNEL 52}; 53 54/* 55 * The enum is to present the 0x00 CONFIG RG bitfield for the 16bit RG value 56 * field value order from LSB to MSB 57 * RTQ6053/6 is OPMODE->VSHUNTCT->VBUSCT->AVG->RESET 58 * RTQ6059 is OPMODE->SADC->BADC->PGA->RESET 59 */ 60enum { 61 F_OPMODE = 0, 62 F_VSHUNTCT, 63 F_RTQ6059_SADC = F_VSHUNTCT, 64 F_VBUSCT, 65 F_RTQ6059_BADC = F_VBUSCT, 66 F_AVG, 67 F_RTQ6059_PGA = F_AVG, 68 F_RESET, 69 F_MAX_FIELDS 70}; 71 72struct rtq6056_priv; 73 74struct richtek_dev_data { 75 bool fixed_samp_freq; 76 u8 vbus_offset; 77 int default_conv_time_us; 78 unsigned int default_config; 79 unsigned int calib_coefficient; 80 const int *avg_sample_list; 81 int avg_sample_list_length; 82 const struct reg_field *reg_fields; 83 const struct iio_chan_spec *channels; 84 int num_channels; 85 int (*read_scale)(struct iio_chan_spec const *ch, int *val, int *val2); 86 int (*set_average)(struct rtq6056_priv *priv, int val); 87}; 88 89struct rtq6056_priv { 90 struct device *dev; 91 struct regmap *regmap; 92 struct regmap_field *rm_fields[F_MAX_FIELDS]; 93 const struct richtek_dev_data *devdata; 94 u32 shunt_resistor_uohm; 95 int vshuntct_us; 96 int vbusct_us; 97 int avg_sample; 98}; 99 100static const struct reg_field rtq6056_reg_fields[F_MAX_FIELDS] = { 101 [F_OPMODE] = REG_FIELD(RTQ6056_REG_CONFIG, 0, 2), 102 [F_VSHUNTCT] = REG_FIELD(RTQ6056_REG_CONFIG, 3, 5), 103 [F_VBUSCT] = REG_FIELD(RTQ6056_REG_CONFIG, 6, 8), 104 [F_AVG] = REG_FIELD(RTQ6056_REG_CONFIG, 9, 11), 105 [F_RESET] = REG_FIELD(RTQ6056_REG_CONFIG, 15, 15), 106}; 107 108static const struct reg_field rtq6059_reg_fields[F_MAX_FIELDS] = { 109 [F_OPMODE] = REG_FIELD(RTQ6056_REG_CONFIG, 0, 2), 110 [F_RTQ6059_SADC] = REG_FIELD(RTQ6056_REG_CONFIG, 3, 6), 111 [F_RTQ6059_BADC] = REG_FIELD(RTQ6056_REG_CONFIG, 7, 10), 112 [F_RTQ6059_PGA] = REG_FIELD(RTQ6056_REG_CONFIG, 11, 12), 113 [F_RESET] = REG_FIELD(RTQ6056_REG_CONFIG, 15, 15), 114}; 115 116static const struct iio_chan_spec rtq6056_channels[RTQ6056_MAX_CHANNEL + 1] = { 117 { 118 .type = IIO_VOLTAGE, 119 .indexed = 1, 120 .channel = 0, 121 .address = RTQ6056_REG_SHUNTVOLT, 122 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 123 BIT(IIO_CHAN_INFO_SCALE) | 124 BIT(IIO_CHAN_INFO_SAMP_FREQ), 125 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 126 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 127 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 128 .scan_index = 0, 129 .scan_type = { 130 .sign = 's', 131 .realbits = 16, 132 .storagebits = 16, 133 .endianness = IIO_CPU, 134 }, 135 }, 136 { 137 .type = IIO_VOLTAGE, 138 .indexed = 1, 139 .channel = 1, 140 .address = RTQ6056_REG_BUSVOLT, 141 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 142 BIT(IIO_CHAN_INFO_SCALE) | 143 BIT(IIO_CHAN_INFO_SAMP_FREQ), 144 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 145 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 146 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 147 .scan_index = 1, 148 .scan_type = { 149 .sign = 'u', 150 .realbits = 16, 151 .storagebits = 16, 152 .endianness = IIO_CPU, 153 }, 154 }, 155 { 156 .type = IIO_POWER, 157 .indexed = 1, 158 .channel = 2, 159 .address = RTQ6056_REG_POWER, 160 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 161 BIT(IIO_CHAN_INFO_SCALE) | 162 BIT(IIO_CHAN_INFO_SAMP_FREQ), 163 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 164 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 165 .scan_index = 2, 166 .scan_type = { 167 .sign = 'u', 168 .realbits = 16, 169 .storagebits = 16, 170 .endianness = IIO_CPU, 171 }, 172 }, 173 { 174 .type = IIO_CURRENT, 175 .indexed = 1, 176 .channel = 3, 177 .address = RTQ6056_REG_CURRENT, 178 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 179 BIT(IIO_CHAN_INFO_SAMP_FREQ), 180 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 181 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 182 .scan_index = 3, 183 .scan_type = { 184 .sign = 's', 185 .realbits = 16, 186 .storagebits = 16, 187 .endianness = IIO_CPU, 188 }, 189 }, 190 IIO_CHAN_SOFT_TIMESTAMP(RTQ6056_MAX_CHANNEL), 191}; 192 193/* 194 * Difference between RTQ6056 and RTQ6059 195 * - Fixed sampling conversion time 196 * - Average sample numbers 197 * - Channel scale 198 * - calibration coefficient 199 */ 200static const struct iio_chan_spec rtq6059_channels[RTQ6056_MAX_CHANNEL + 1] = { 201 { 202 .type = IIO_VOLTAGE, 203 .indexed = 1, 204 .channel = 0, 205 .address = RTQ6056_REG_SHUNTVOLT, 206 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 207 BIT(IIO_CHAN_INFO_SCALE) | 208 BIT(IIO_CHAN_INFO_SAMP_FREQ), 209 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 210 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 211 .scan_index = 0, 212 .scan_type = { 213 .sign = 's', 214 .realbits = 16, 215 .storagebits = 16, 216 .endianness = IIO_CPU, 217 }, 218 }, 219 { 220 .type = IIO_VOLTAGE, 221 .indexed = 1, 222 .channel = 1, 223 .address = RTQ6056_REG_BUSVOLT, 224 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 225 BIT(IIO_CHAN_INFO_SCALE) | 226 BIT(IIO_CHAN_INFO_SAMP_FREQ), 227 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 228 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 229 .scan_index = 1, 230 .scan_type = { 231 .sign = 'u', 232 .realbits = 16, 233 .storagebits = 16, 234 .endianness = IIO_CPU, 235 }, 236 }, 237 { 238 .type = IIO_POWER, 239 .indexed = 1, 240 .channel = 2, 241 .address = RTQ6056_REG_POWER, 242 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 243 BIT(IIO_CHAN_INFO_SCALE) | 244 BIT(IIO_CHAN_INFO_SAMP_FREQ), 245 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 246 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 247 .scan_index = 2, 248 .scan_type = { 249 .sign = 'u', 250 .realbits = 16, 251 .storagebits = 16, 252 .endianness = IIO_CPU, 253 }, 254 }, 255 { 256 .type = IIO_CURRENT, 257 .indexed = 1, 258 .channel = 3, 259 .address = RTQ6056_REG_CURRENT, 260 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 261 BIT(IIO_CHAN_INFO_SAMP_FREQ), 262 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 263 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 264 .scan_index = 3, 265 .scan_type = { 266 .sign = 's', 267 .realbits = 16, 268 .storagebits = 16, 269 .endianness = IIO_CPU, 270 }, 271 }, 272 IIO_CHAN_SOFT_TIMESTAMP(RTQ6056_MAX_CHANNEL), 273}; 274 275static int rtq6056_adc_read_channel(struct rtq6056_priv *priv, 276 struct iio_chan_spec const *ch, 277 int *val) 278{ 279 const struct richtek_dev_data *devdata = priv->devdata; 280 struct device *dev = priv->dev; 281 unsigned int addr = ch->address; 282 unsigned int regval; 283 int ret; 284 285 pm_runtime_get_sync(dev); 286 ret = regmap_read(priv->regmap, addr, ®val); 287 pm_runtime_mark_last_busy(dev); 288 pm_runtime_put(dev); 289 if (ret) 290 return ret; 291 292 /* Power and VBUS is unsigned 16-bit, others are signed 16-bit */ 293 switch (addr) { 294 case RTQ6056_REG_BUSVOLT: 295 regval >>= devdata->vbus_offset; 296 *val = regval; 297 return IIO_VAL_INT; 298 case RTQ6056_REG_POWER: 299 *val = regval; 300 return IIO_VAL_INT; 301 case RTQ6056_REG_SHUNTVOLT: 302 case RTQ6056_REG_CURRENT: 303 *val = sign_extend32(regval, 16); 304 return IIO_VAL_INT; 305 default: 306 return -EINVAL; 307 } 308} 309 310static int rtq6056_adc_read_scale(struct iio_chan_spec const *ch, int *val, 311 int *val2) 312{ 313 switch (ch->address) { 314 case RTQ6056_REG_SHUNTVOLT: 315 /* VSHUNT lsb 2.5uV */ 316 *val = 2500; 317 *val2 = 1000000; 318 return IIO_VAL_FRACTIONAL; 319 case RTQ6056_REG_BUSVOLT: 320 /* VBUS lsb 1.25mV */ 321 *val = 1250; 322 *val2 = 1000; 323 return IIO_VAL_FRACTIONAL; 324 case RTQ6056_REG_POWER: 325 /* Power lsb 25mW */ 326 *val = 25; 327 return IIO_VAL_INT; 328 default: 329 return -EINVAL; 330 } 331} 332 333static int rtq6059_adc_read_scale(struct iio_chan_spec const *ch, int *val, 334 int *val2) 335{ 336 switch (ch->address) { 337 case RTQ6056_REG_SHUNTVOLT: 338 /* VSHUNT lsb 10uV */ 339 *val = 10000; 340 *val2 = 1000000; 341 return IIO_VAL_FRACTIONAL; 342 case RTQ6056_REG_BUSVOLT: 343 /* VBUS lsb 4mV */ 344 *val = 4; 345 return IIO_VAL_INT; 346 case RTQ6056_REG_POWER: 347 /* Power lsb 20mW */ 348 *val = 20; 349 return IIO_VAL_INT; 350 default: 351 return -EINVAL; 352 } 353} 354 355/* 356 * Sample frequency for channel VSHUNT and VBUS. The indices correspond 357 * with the bit value expected by the chip. And it can be found at 358 * https://www.richtek.com/assets/product_file/RTQ6056/DSQ6056-00.pdf 359 */ 360static const int rtq6056_samp_freq_list[] = { 361 7194, 4926, 3717, 1904, 964, 485, 243, 122, 362}; 363 364static int rtq6056_adc_set_samp_freq(struct rtq6056_priv *priv, 365 struct iio_chan_spec const *ch, int val) 366{ 367 struct regmap_field *rm_field; 368 unsigned int selector; 369 int *ct, ret; 370 371 if (val > 7194 || val < 122) 372 return -EINVAL; 373 374 if (ch->address == RTQ6056_REG_SHUNTVOLT) { 375 rm_field = priv->rm_fields[F_VSHUNTCT]; 376 ct = &priv->vshuntct_us; 377 } else if (ch->address == RTQ6056_REG_BUSVOLT) { 378 rm_field = priv->rm_fields[F_VBUSCT]; 379 ct = &priv->vbusct_us; 380 } else 381 return -EINVAL; 382 383 selector = find_closest_descending(val, rtq6056_samp_freq_list, 384 ARRAY_SIZE(rtq6056_samp_freq_list)); 385 386 ret = regmap_field_write(rm_field, selector); 387 if (ret) 388 return ret; 389 390 *ct = 1000000 / rtq6056_samp_freq_list[selector]; 391 392 return 0; 393} 394 395/* 396 * Available averaging rate for rtq6056. The indices correspond with the bit 397 * value expected by the chip. And it can be found at 398 * https://www.richtek.com/assets/product_file/RTQ6056/DSQ6056-00.pdf 399 */ 400static const int rtq6056_avg_sample_list[] = { 401 1, 4, 16, 64, 128, 256, 512, 1024, 402}; 403 404static const int rtq6059_avg_sample_list[] = { 405 1, 2, 4, 8, 16, 32, 64, 128, 406}; 407 408static int rtq6056_adc_set_average(struct rtq6056_priv *priv, int val) 409{ 410 unsigned int selector; 411 int ret; 412 413 if (val > 1024 || val < 1) 414 return -EINVAL; 415 416 selector = find_closest(val, rtq6056_avg_sample_list, 417 ARRAY_SIZE(rtq6056_avg_sample_list)); 418 419 ret = regmap_field_write(priv->rm_fields[F_AVG], selector); 420 if (ret) 421 return ret; 422 423 priv->avg_sample = rtq6056_avg_sample_list[selector]; 424 425 return 0; 426} 427 428static int rtq6059_adc_set_average(struct rtq6056_priv *priv, int val) 429{ 430 unsigned int selector; 431 int ret; 432 433 if (val > 128 || val < 1) 434 return -EINVAL; 435 436 /* The supported average sample is 2^x (x from 0 to 7) */ 437 selector = fls(val) - 1; 438 439 ret = regmap_field_write(priv->rm_fields[F_RTQ6059_BADC], 440 RTQ6059_AVG_BASE + selector); 441 if (ret) 442 return ret; 443 444 ret = regmap_field_write(priv->rm_fields[F_RTQ6059_SADC], 445 RTQ6059_AVG_BASE + selector); 446 447 priv->avg_sample = BIT(selector); 448 449 return 0; 450} 451 452static int rtq6056_adc_get_sample_freq(struct rtq6056_priv *priv, 453 struct iio_chan_spec const *ch, int *val) 454{ 455 int sample_time; 456 457 if (ch->address == RTQ6056_REG_SHUNTVOLT) 458 sample_time = priv->vshuntct_us; 459 else if (ch->address == RTQ6056_REG_BUSVOLT) 460 sample_time = priv->vbusct_us; 461 else { 462 sample_time = priv->vshuntct_us + priv->vbusct_us; 463 sample_time *= priv->avg_sample; 464 } 465 466 *val = 1000000 / sample_time; 467 468 return IIO_VAL_INT; 469} 470 471static int rtq6056_adc_read_raw(struct iio_dev *indio_dev, 472 struct iio_chan_spec const *chan, int *val, 473 int *val2, long mask) 474{ 475 struct rtq6056_priv *priv = iio_priv(indio_dev); 476 const struct richtek_dev_data *devdata = priv->devdata; 477 478 switch (mask) { 479 case IIO_CHAN_INFO_RAW: 480 return rtq6056_adc_read_channel(priv, chan, val); 481 case IIO_CHAN_INFO_SCALE: 482 return devdata->read_scale(chan, val, val2); 483 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 484 *val = priv->avg_sample; 485 return IIO_VAL_INT; 486 case IIO_CHAN_INFO_SAMP_FREQ: 487 return rtq6056_adc_get_sample_freq(priv, chan, val); 488 default: 489 return -EINVAL; 490 } 491} 492 493static int rtq6056_adc_read_avail(struct iio_dev *indio_dev, 494 struct iio_chan_spec const *chan, 495 const int **vals, int *type, int *length, 496 long mask) 497{ 498 struct rtq6056_priv *priv = iio_priv(indio_dev); 499 const struct richtek_dev_data *devdata = priv->devdata; 500 501 switch (mask) { 502 case IIO_CHAN_INFO_SAMP_FREQ: 503 *vals = rtq6056_samp_freq_list; 504 *type = IIO_VAL_INT; 505 *length = ARRAY_SIZE(rtq6056_samp_freq_list); 506 return IIO_AVAIL_LIST; 507 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 508 *vals = devdata->avg_sample_list; 509 *length = devdata->avg_sample_list_length; 510 *type = IIO_VAL_INT; 511 return IIO_AVAIL_LIST; 512 default: 513 return -EINVAL; 514 } 515} 516 517static int rtq6056_adc_write_raw(struct iio_dev *indio_dev, 518 struct iio_chan_spec const *chan, int val, 519 int val2, long mask) 520{ 521 struct rtq6056_priv *priv = iio_priv(indio_dev); 522 const struct richtek_dev_data *devdata = priv->devdata; 523 int ret; 524 525 ret = iio_device_claim_direct_mode(indio_dev); 526 if (ret) 527 return ret; 528 529 switch (mask) { 530 case IIO_CHAN_INFO_SAMP_FREQ: 531 if (devdata->fixed_samp_freq) { 532 ret = -EINVAL; 533 break; 534 } 535 536 ret = rtq6056_adc_set_samp_freq(priv, chan, val); 537 break; 538 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 539 ret = devdata->set_average(priv, val); 540 break; 541 default: 542 ret = -EINVAL; 543 break; 544 } 545 546 iio_device_release_direct_mode(indio_dev); 547 548 return ret; 549} 550 551static const char *rtq6056_channel_labels[RTQ6056_MAX_CHANNEL] = { 552 [RTQ6056_CH_VSHUNT] = "Vshunt", 553 [RTQ6056_CH_VBUS] = "Vbus", 554 [RTQ6056_CH_POWER] = "Power", 555 [RTQ6056_CH_CURRENT] = "Current", 556}; 557 558static int rtq6056_adc_read_label(struct iio_dev *indio_dev, 559 struct iio_chan_spec const *chan, 560 char *label) 561{ 562 return sysfs_emit(label, "%s\n", rtq6056_channel_labels[chan->channel]); 563} 564 565static int rtq6056_set_shunt_resistor(struct rtq6056_priv *priv, 566 int resistor_uohm) 567{ 568 const struct richtek_dev_data *devdata = priv->devdata; 569 unsigned int calib_val; 570 int ret; 571 572 if (resistor_uohm <= 0) { 573 dev_err(priv->dev, "Invalid resistor [%d]\n", resistor_uohm); 574 return -EINVAL; 575 } 576 577 /* calibration = coefficient / (Rshunt (uOhm) * current lsb (1mA)) */ 578 calib_val = devdata->calib_coefficient / resistor_uohm; 579 ret = regmap_write(priv->regmap, RTQ6056_REG_CALIBRATION, calib_val); 580 if (ret) 581 return ret; 582 583 priv->shunt_resistor_uohm = resistor_uohm; 584 585 return 0; 586} 587 588static ssize_t shunt_resistor_show(struct device *dev, 589 struct device_attribute *attr, char *buf) 590{ 591 struct rtq6056_priv *priv = iio_priv(dev_to_iio_dev(dev)); 592 int vals[2] = { priv->shunt_resistor_uohm, 1000000 }; 593 594 return iio_format_value(buf, IIO_VAL_FRACTIONAL, 1, vals); 595} 596 597static ssize_t shunt_resistor_store(struct device *dev, 598 struct device_attribute *attr, 599 const char *buf, size_t len) 600{ 601 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 602 struct rtq6056_priv *priv = iio_priv(indio_dev); 603 int val, val_fract, ret; 604 605 ret = iio_device_claim_direct_mode(indio_dev); 606 if (ret) 607 return ret; 608 609 ret = iio_str_to_fixpoint(buf, 100000, &val, &val_fract); 610 if (ret) 611 goto out_store; 612 613 ret = rtq6056_set_shunt_resistor(priv, val * 1000000 + val_fract); 614 615out_store: 616 iio_device_release_direct_mode(indio_dev); 617 618 return ret ?: len; 619} 620 621static IIO_DEVICE_ATTR_RW(shunt_resistor, 0); 622 623static struct attribute *rtq6056_attributes[] = { 624 &iio_dev_attr_shunt_resistor.dev_attr.attr, 625 NULL 626}; 627 628static const struct attribute_group rtq6056_attribute_group = { 629 .attrs = rtq6056_attributes, 630}; 631 632static const struct iio_info rtq6056_info = { 633 .attrs = &rtq6056_attribute_group, 634 .read_raw = rtq6056_adc_read_raw, 635 .read_avail = rtq6056_adc_read_avail, 636 .write_raw = rtq6056_adc_write_raw, 637 .read_label = rtq6056_adc_read_label, 638}; 639 640static irqreturn_t rtq6056_buffer_trigger_handler(int irq, void *p) 641{ 642 struct iio_poll_func *pf = p; 643 struct iio_dev *indio_dev = pf->indio_dev; 644 struct rtq6056_priv *priv = iio_priv(indio_dev); 645 const struct richtek_dev_data *devdata = priv->devdata; 646 struct device *dev = priv->dev; 647 struct { 648 u16 vals[RTQ6056_MAX_CHANNEL]; 649 s64 timestamp __aligned(8); 650 } data; 651 unsigned int raw; 652 int i = 0, bit, ret; 653 654 memset(&data, 0, sizeof(data)); 655 656 pm_runtime_get_sync(dev); 657 658 for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->masklength) { 659 unsigned int addr = rtq6056_channels[bit].address; 660 661 ret = regmap_read(priv->regmap, addr, &raw); 662 if (ret) 663 goto out; 664 665 if (addr == RTQ6056_REG_BUSVOLT) 666 raw >>= devdata->vbus_offset; 667 668 data.vals[i++] = raw; 669 } 670 671 iio_push_to_buffers_with_timestamp(indio_dev, &data, iio_get_time_ns(indio_dev)); 672 673out: 674 pm_runtime_mark_last_busy(dev); 675 pm_runtime_put(dev); 676 677 iio_trigger_notify_done(indio_dev->trig); 678 679 return IRQ_HANDLED; 680} 681 682static void rtq6056_enter_shutdown_state(void *dev) 683{ 684 struct rtq6056_priv *priv = dev_get_drvdata(dev); 685 686 /* Enter shutdown state */ 687 regmap_field_write(priv->rm_fields[F_OPMODE], 0); 688} 689 690static bool rtq6056_is_readable_reg(struct device *dev, unsigned int reg) 691{ 692 switch (reg) { 693 case RTQ6056_REG_CONFIG ... RTQ6056_REG_ALERTLIMIT: 694 case RTQ6056_REG_MANUFACTID ... RTQ6056_REG_DIEID: 695 return true; 696 default: 697 return false; 698 } 699} 700 701static bool rtq6056_is_writeable_reg(struct device *dev, unsigned int reg) 702{ 703 switch (reg) { 704 case RTQ6056_REG_CONFIG: 705 case RTQ6056_REG_CALIBRATION ... RTQ6056_REG_ALERTLIMIT: 706 return true; 707 default: 708 return false; 709 } 710} 711 712static const struct regmap_config rtq6056_regmap_config = { 713 .reg_bits = 8, 714 .val_bits = 16, 715 .val_format_endian = REGMAP_ENDIAN_BIG, 716 .max_register = RTQ6056_REG_DIEID, 717 .readable_reg = rtq6056_is_readable_reg, 718 .writeable_reg = rtq6056_is_writeable_reg, 719}; 720 721static int rtq6056_probe(struct i2c_client *i2c) 722{ 723 struct iio_dev *indio_dev; 724 struct rtq6056_priv *priv; 725 struct device *dev = &i2c->dev; 726 struct regmap *regmap; 727 const struct richtek_dev_data *devdata; 728 unsigned int vendor_id, shunt_resistor_uohm; 729 int ret; 730 731 if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_WORD_DATA)) 732 return -EOPNOTSUPP; 733 734 devdata = device_get_match_data(dev); 735 if (!devdata) 736 return dev_err_probe(dev, -EINVAL, "Invalid dev data\n"); 737 738 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv)); 739 if (!indio_dev) 740 return -ENOMEM; 741 742 priv = iio_priv(indio_dev); 743 priv->dev = dev; 744 priv->vshuntct_us = priv->vbusct_us = devdata->default_conv_time_us; 745 priv->avg_sample = 1; 746 priv->devdata = devdata; 747 i2c_set_clientdata(i2c, priv); 748 749 regmap = devm_regmap_init_i2c(i2c, &rtq6056_regmap_config); 750 if (IS_ERR(regmap)) 751 return dev_err_probe(dev, PTR_ERR(regmap), 752 "Failed to init regmap\n"); 753 754 priv->regmap = regmap; 755 756 ret = regmap_read(regmap, RTQ6056_REG_MANUFACTID, &vendor_id); 757 if (ret) 758 return dev_err_probe(dev, ret, 759 "Failed to get manufacturer info\n"); 760 761 if (vendor_id != RTQ6056_VENDOR_ID) 762 return dev_err_probe(dev, -ENODEV, 763 "Invalid vendor id 0x%04x\n", vendor_id); 764 765 ret = devm_regmap_field_bulk_alloc(dev, regmap, priv->rm_fields, 766 devdata->reg_fields, F_MAX_FIELDS); 767 if (ret) 768 return dev_err_probe(dev, ret, "Failed to init regmap field\n"); 769 770 ret = regmap_write(regmap, RTQ6056_REG_CONFIG, devdata->default_config); 771 if (ret) 772 return dev_err_probe(dev, ret, 773 "Failed to enable continuous sensing\n"); 774 775 ret = devm_add_action_or_reset(dev, rtq6056_enter_shutdown_state, dev); 776 if (ret) 777 return ret; 778 779 pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); 780 pm_runtime_use_autosuspend(dev); 781 pm_runtime_set_active(dev); 782 pm_runtime_mark_last_busy(dev); 783 ret = devm_pm_runtime_enable(dev); 784 if (ret) 785 return dev_err_probe(dev, ret, "Failed to enable pm_runtime\n"); 786 787 /* By default, use 2000 micro-Ohm resistor */ 788 shunt_resistor_uohm = 2000; 789 device_property_read_u32(dev, "shunt-resistor-micro-ohms", 790 &shunt_resistor_uohm); 791 792 ret = rtq6056_set_shunt_resistor(priv, shunt_resistor_uohm); 793 if (ret) 794 return dev_err_probe(dev, ret, 795 "Failed to init shunt resistor\n"); 796 797 indio_dev->name = "rtq6056"; 798 indio_dev->modes = INDIO_DIRECT_MODE; 799 indio_dev->channels = devdata->channels; 800 indio_dev->num_channels = devdata->num_channels; 801 indio_dev->info = &rtq6056_info; 802 803 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 804 rtq6056_buffer_trigger_handler, 805 NULL); 806 if (ret) 807 return dev_err_probe(dev, ret, 808 "Failed to allocate iio trigger buffer\n"); 809 810 return devm_iio_device_register(dev, indio_dev); 811} 812 813static int rtq6056_runtime_suspend(struct device *dev) 814{ 815 struct rtq6056_priv *priv = dev_get_drvdata(dev); 816 817 /* Configure to shutdown mode */ 818 return regmap_field_write(priv->rm_fields[F_OPMODE], 0); 819} 820 821static int rtq6056_runtime_resume(struct device *dev) 822{ 823 struct rtq6056_priv *priv = dev_get_drvdata(dev); 824 int sample_rdy_time_us, ret; 825 826 ret = regmap_field_write(priv->rm_fields[F_OPMODE], RTQ6056_CONT_ALLON); 827 if (ret) 828 return ret; 829 830 sample_rdy_time_us = priv->vbusct_us + priv->vshuntct_us; 831 sample_rdy_time_us *= priv->avg_sample; 832 833 usleep_range(sample_rdy_time_us, sample_rdy_time_us + 100); 834 835 return 0; 836} 837 838static DEFINE_RUNTIME_DEV_PM_OPS(rtq6056_pm_ops, rtq6056_runtime_suspend, 839 rtq6056_runtime_resume, NULL); 840 841static const struct richtek_dev_data rtq6056_devdata = { 842 .default_conv_time_us = 1037, 843 .calib_coefficient = 5120000, 844 /* 845 * By default, configure average sample as 1, bus and shunt conversion 846 * time as 1037 microsecond, and operating mode to all on. 847 */ 848 .default_config = RTQ6056_DEFAULT_CONFIG, 849 .avg_sample_list = rtq6056_avg_sample_list, 850 .avg_sample_list_length = ARRAY_SIZE(rtq6056_avg_sample_list), 851 .reg_fields = rtq6056_reg_fields, 852 .channels = rtq6056_channels, 853 .num_channels = ARRAY_SIZE(rtq6056_channels), 854 .read_scale = rtq6056_adc_read_scale, 855 .set_average = rtq6056_adc_set_average, 856}; 857 858static const struct richtek_dev_data rtq6059_devdata = { 859 .fixed_samp_freq = true, 860 .vbus_offset = RTQ6059_VBUS_LSB_OFFSET, 861 .default_conv_time_us = 532, 862 .calib_coefficient = 40960000, 863 /* 864 * By default, configure average sample as 1, bus and shunt conversion 865 * time as 532 microsecond, and operating mode to all on. 866 */ 867 .default_config = RTQ6059_DEFAULT_CONFIG, 868 .avg_sample_list = rtq6059_avg_sample_list, 869 .avg_sample_list_length = ARRAY_SIZE(rtq6059_avg_sample_list), 870 .reg_fields = rtq6059_reg_fields, 871 .channels = rtq6059_channels, 872 .num_channels = ARRAY_SIZE(rtq6059_channels), 873 .read_scale = rtq6059_adc_read_scale, 874 .set_average = rtq6059_adc_set_average, 875}; 876 877static const struct of_device_id rtq6056_device_match[] = { 878 { .compatible = "richtek,rtq6056", .data = &rtq6056_devdata }, 879 { .compatible = "richtek,rtq6059", .data = &rtq6059_devdata }, 880 {} 881}; 882MODULE_DEVICE_TABLE(of, rtq6056_device_match); 883 884static struct i2c_driver rtq6056_driver = { 885 .driver = { 886 .name = "rtq6056", 887 .of_match_table = rtq6056_device_match, 888 .pm = pm_ptr(&rtq6056_pm_ops), 889 }, 890 .probe = rtq6056_probe, 891}; 892module_i2c_driver(rtq6056_driver); 893 894MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>"); 895MODULE_DESCRIPTION("Richtek RTQ6056 Driver"); 896MODULE_LICENSE("GPL v2"); 897