1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/bitops.h>
7#include <linux/completion.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/iio/iio.h>
11#include <linux/interrupt.h>
12#include <linux/kernel.h>
13#include <linux/mutex.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/regmap.h>
18#include <linux/slab.h>
19
20/* IADC register and bit definition */
21#define IADC_REVISION2				0x1
22#define IADC_REVISION2_SUPPORTED_IADC		1
23
24#define IADC_PERPH_TYPE				0x4
25#define IADC_PERPH_TYPE_ADC			8
26
27#define IADC_PERPH_SUBTYPE			0x5
28#define IADC_PERPH_SUBTYPE_IADC			3
29
30#define IADC_STATUS1				0x8
31#define IADC_STATUS1_OP_MODE			4
32#define IADC_STATUS1_REQ_STS			BIT(1)
33#define IADC_STATUS1_EOC			BIT(0)
34#define IADC_STATUS1_REQ_STS_EOC_MASK		0x3
35
36#define IADC_MODE_CTL				0x40
37#define IADC_OP_MODE_SHIFT			3
38#define IADC_OP_MODE_NORMAL			0
39#define IADC_TRIM_EN				BIT(0)
40
41#define IADC_EN_CTL1				0x46
42#define IADC_EN_CTL1_SET			BIT(7)
43
44#define IADC_CH_SEL_CTL				0x48
45
46#define IADC_DIG_PARAM				0x50
47#define IADC_DIG_DEC_RATIO_SEL_SHIFT		2
48
49#define IADC_HW_SETTLE_DELAY			0x51
50
51#define IADC_CONV_REQ				0x52
52#define IADC_CONV_REQ_SET			BIT(7)
53
54#define IADC_FAST_AVG_CTL			0x5a
55#define IADC_FAST_AVG_EN			0x5b
56#define IADC_FAST_AVG_EN_SET			BIT(7)
57
58#define IADC_PERH_RESET_CTL3			0xda
59#define IADC_FOLLOW_WARM_RB			BIT(2)
60
61#define IADC_DATA				0x60	/* 16 bits */
62
63#define IADC_SEC_ACCESS				0xd0
64#define IADC_SEC_ACCESS_DATA			0xa5
65
66#define IADC_NOMINAL_RSENSE			0xf4
67#define IADC_NOMINAL_RSENSE_SIGN_MASK		BIT(7)
68
69#define IADC_REF_GAIN_MICRO_VOLTS		17857
70
71#define IADC_INT_RSENSE_DEVIATION		15625	/* nano Ohms per bit */
72
73#define IADC_INT_RSENSE_IDEAL_VALUE		10000	/* micro Ohms */
74#define IADC_INT_RSENSE_DEFAULT_VALUE		7800	/* micro Ohms */
75#define IADC_INT_RSENSE_DEFAULT_GF		9000	/* micro Ohms */
76#define IADC_INT_RSENSE_DEFAULT_SMIC		9700	/* micro Ohms */
77
78#define IADC_CONV_TIME_MIN_US			2000
79#define IADC_CONV_TIME_MAX_US			2100
80
81#define IADC_DEF_PRESCALING			0 /* 1:1 */
82#define IADC_DEF_DECIMATION			0 /* 512 */
83#define IADC_DEF_HW_SETTLE_TIME			0 /* 0 us */
84#define IADC_DEF_AVG_SAMPLES			0 /* 1 sample */
85
86/* IADC channel list */
87#define IADC_INT_RSENSE				0
88#define IADC_EXT_RSENSE				1
89#define IADC_GAIN_17P857MV			3
90#define IADC_EXT_OFFSET_CSP_CSN			5
91#define IADC_INT_OFFSET_CSP2_CSN2		6
92
93/**
94 * struct iadc_chip - IADC Current ADC device structure.
95 * @regmap: regmap for register read/write.
96 * @dev: This device pointer.
97 * @base: base offset for the ADC peripheral.
98 * @rsense: Values of the internal and external sense resister in micro Ohms.
99 * @poll_eoc: Poll for end of conversion instead of waiting for IRQ.
100 * @offset: Raw offset values for the internal and external channels.
101 * @gain: Raw gain of the channels.
102 * @lock: ADC lock for access to the peripheral.
103 * @complete: ADC notification after end of conversion interrupt is received.
104 */
105struct iadc_chip {
106	struct regmap	*regmap;
107	struct device	*dev;
108	u16		base;
109	bool		poll_eoc;
110	u32		rsense[2];
111	u16		offset[2];
112	u16		gain;
113	struct mutex	lock;
114	struct completion complete;
115};
116
117static int iadc_read(struct iadc_chip *iadc, u16 offset, u8 *data)
118{
119	unsigned int val;
120	int ret;
121
122	ret = regmap_read(iadc->regmap, iadc->base + offset, &val);
123	if (ret < 0)
124		return ret;
125
126	*data = val;
127	return 0;
128}
129
130static int iadc_write(struct iadc_chip *iadc, u16 offset, u8 data)
131{
132	return regmap_write(iadc->regmap, iadc->base + offset, data);
133}
134
135static int iadc_reset(struct iadc_chip *iadc)
136{
137	u8 data;
138	int ret;
139
140	ret = iadc_write(iadc, IADC_SEC_ACCESS, IADC_SEC_ACCESS_DATA);
141	if (ret < 0)
142		return ret;
143
144	ret = iadc_read(iadc, IADC_PERH_RESET_CTL3, &data);
145	if (ret < 0)
146		return ret;
147
148	ret = iadc_write(iadc, IADC_SEC_ACCESS, IADC_SEC_ACCESS_DATA);
149	if (ret < 0)
150		return ret;
151
152	data |= IADC_FOLLOW_WARM_RB;
153
154	return iadc_write(iadc, IADC_PERH_RESET_CTL3, data);
155}
156
157static int iadc_set_state(struct iadc_chip *iadc, bool state)
158{
159	return iadc_write(iadc, IADC_EN_CTL1, state ? IADC_EN_CTL1_SET : 0);
160}
161
162static void iadc_status_show(struct iadc_chip *iadc)
163{
164	u8 mode, sta1, chan, dig, en, req;
165	int ret;
166
167	ret = iadc_read(iadc, IADC_MODE_CTL, &mode);
168	if (ret < 0)
169		return;
170
171	ret = iadc_read(iadc, IADC_DIG_PARAM, &dig);
172	if (ret < 0)
173		return;
174
175	ret = iadc_read(iadc, IADC_CH_SEL_CTL, &chan);
176	if (ret < 0)
177		return;
178
179	ret = iadc_read(iadc, IADC_CONV_REQ, &req);
180	if (ret < 0)
181		return;
182
183	ret = iadc_read(iadc, IADC_STATUS1, &sta1);
184	if (ret < 0)
185		return;
186
187	ret = iadc_read(iadc, IADC_EN_CTL1, &en);
188	if (ret < 0)
189		return;
190
191	dev_err(iadc->dev,
192		"mode:%02x en:%02x chan:%02x dig:%02x req:%02x sta1:%02x\n",
193		mode, en, chan, dig, req, sta1);
194}
195
196static int iadc_configure(struct iadc_chip *iadc, int channel)
197{
198	u8 decim, mode;
199	int ret;
200
201	/* Mode selection */
202	mode = (IADC_OP_MODE_NORMAL << IADC_OP_MODE_SHIFT) | IADC_TRIM_EN;
203	ret = iadc_write(iadc, IADC_MODE_CTL, mode);
204	if (ret < 0)
205		return ret;
206
207	/* Channel selection */
208	ret = iadc_write(iadc, IADC_CH_SEL_CTL, channel);
209	if (ret < 0)
210		return ret;
211
212	/* Digital parameter setup */
213	decim = IADC_DEF_DECIMATION << IADC_DIG_DEC_RATIO_SEL_SHIFT;
214	ret = iadc_write(iadc, IADC_DIG_PARAM, decim);
215	if (ret < 0)
216		return ret;
217
218	/* HW settle time delay */
219	ret = iadc_write(iadc, IADC_HW_SETTLE_DELAY, IADC_DEF_HW_SETTLE_TIME);
220	if (ret < 0)
221		return ret;
222
223	ret = iadc_write(iadc, IADC_FAST_AVG_CTL, IADC_DEF_AVG_SAMPLES);
224	if (ret < 0)
225		return ret;
226
227	if (IADC_DEF_AVG_SAMPLES)
228		ret = iadc_write(iadc, IADC_FAST_AVG_EN, IADC_FAST_AVG_EN_SET);
229	else
230		ret = iadc_write(iadc, IADC_FAST_AVG_EN, 0);
231
232	if (ret < 0)
233		return ret;
234
235	if (!iadc->poll_eoc)
236		reinit_completion(&iadc->complete);
237
238	ret = iadc_set_state(iadc, true);
239	if (ret < 0)
240		return ret;
241
242	/* Request conversion */
243	return iadc_write(iadc, IADC_CONV_REQ, IADC_CONV_REQ_SET);
244}
245
246static int iadc_poll_wait_eoc(struct iadc_chip *iadc, unsigned int interval_us)
247{
248	unsigned int count, retry;
249	int ret;
250	u8 sta1;
251
252	retry = interval_us / IADC_CONV_TIME_MIN_US;
253
254	for (count = 0; count < retry; count++) {
255		ret = iadc_read(iadc, IADC_STATUS1, &sta1);
256		if (ret < 0)
257			return ret;
258
259		sta1 &= IADC_STATUS1_REQ_STS_EOC_MASK;
260		if (sta1 == IADC_STATUS1_EOC)
261			return 0;
262
263		usleep_range(IADC_CONV_TIME_MIN_US, IADC_CONV_TIME_MAX_US);
264	}
265
266	iadc_status_show(iadc);
267
268	return -ETIMEDOUT;
269}
270
271static int iadc_read_result(struct iadc_chip *iadc, u16 *data)
272{
273	return regmap_bulk_read(iadc->regmap, iadc->base + IADC_DATA, data, 2);
274}
275
276static int iadc_do_conversion(struct iadc_chip *iadc, int chan, u16 *data)
277{
278	unsigned int wait;
279	int ret;
280
281	ret = iadc_configure(iadc, chan);
282	if (ret < 0)
283		goto exit;
284
285	wait = BIT(IADC_DEF_AVG_SAMPLES) * IADC_CONV_TIME_MIN_US * 2;
286
287	if (iadc->poll_eoc) {
288		ret = iadc_poll_wait_eoc(iadc, wait);
289	} else {
290		ret = wait_for_completion_timeout(&iadc->complete,
291			usecs_to_jiffies(wait));
292		if (!ret)
293			ret = -ETIMEDOUT;
294		else
295			/* double check conversion status */
296			ret = iadc_poll_wait_eoc(iadc, IADC_CONV_TIME_MIN_US);
297	}
298
299	if (!ret)
300		ret = iadc_read_result(iadc, data);
301exit:
302	iadc_set_state(iadc, false);
303	if (ret < 0)
304		dev_err(iadc->dev, "conversion failed\n");
305
306	return ret;
307}
308
309static int iadc_read_raw(struct iio_dev *indio_dev,
310			 struct iio_chan_spec const *chan,
311			 int *val, int *val2, long mask)
312{
313	struct iadc_chip *iadc = iio_priv(indio_dev);
314	s32 isense_ua, vsense_uv;
315	u16 adc_raw, vsense_raw;
316	int ret;
317
318	switch (mask) {
319	case IIO_CHAN_INFO_RAW:
320		mutex_lock(&iadc->lock);
321		ret = iadc_do_conversion(iadc, chan->channel, &adc_raw);
322		mutex_unlock(&iadc->lock);
323		if (ret < 0)
324			return ret;
325
326		vsense_raw = adc_raw - iadc->offset[chan->channel];
327
328		vsense_uv = vsense_raw * IADC_REF_GAIN_MICRO_VOLTS;
329		vsense_uv /= (s32)iadc->gain - iadc->offset[chan->channel];
330
331		isense_ua = vsense_uv / iadc->rsense[chan->channel];
332
333		dev_dbg(iadc->dev, "off %d gain %d adc %d %duV I %duA\n",
334			iadc->offset[chan->channel], iadc->gain,
335			adc_raw, vsense_uv, isense_ua);
336
337		*val = isense_ua;
338		return IIO_VAL_INT;
339	case IIO_CHAN_INFO_SCALE:
340		*val = 0;
341		*val2 = 1000;
342		return IIO_VAL_INT_PLUS_MICRO;
343	}
344
345	return -EINVAL;
346}
347
348static const struct iio_info iadc_info = {
349	.read_raw = iadc_read_raw,
350};
351
352static irqreturn_t iadc_isr(int irq, void *dev_id)
353{
354	struct iadc_chip *iadc = dev_id;
355
356	complete(&iadc->complete);
357
358	return IRQ_HANDLED;
359}
360
361static int iadc_update_offset(struct iadc_chip *iadc)
362{
363	int ret;
364
365	ret = iadc_do_conversion(iadc, IADC_GAIN_17P857MV, &iadc->gain);
366	if (ret < 0)
367		return ret;
368
369	ret = iadc_do_conversion(iadc, IADC_INT_OFFSET_CSP2_CSN2,
370				 &iadc->offset[IADC_INT_RSENSE]);
371	if (ret < 0)
372		return ret;
373
374	if (iadc->gain == iadc->offset[IADC_INT_RSENSE]) {
375		dev_err(iadc->dev, "error: internal offset == gain %d\n",
376			iadc->gain);
377		return -EINVAL;
378	}
379
380	ret = iadc_do_conversion(iadc, IADC_EXT_OFFSET_CSP_CSN,
381				 &iadc->offset[IADC_EXT_RSENSE]);
382	if (ret < 0)
383		return ret;
384
385	if (iadc->gain == iadc->offset[IADC_EXT_RSENSE]) {
386		dev_err(iadc->dev, "error: external offset == gain %d\n",
387			iadc->gain);
388		return -EINVAL;
389	}
390
391	return 0;
392}
393
394static int iadc_version_check(struct iadc_chip *iadc)
395{
396	u8 val;
397	int ret;
398
399	ret = iadc_read(iadc, IADC_PERPH_TYPE, &val);
400	if (ret < 0)
401		return ret;
402
403	if (val < IADC_PERPH_TYPE_ADC) {
404		dev_err(iadc->dev, "%d is not ADC\n", val);
405		return -EINVAL;
406	}
407
408	ret = iadc_read(iadc, IADC_PERPH_SUBTYPE, &val);
409	if (ret < 0)
410		return ret;
411
412	if (val < IADC_PERPH_SUBTYPE_IADC) {
413		dev_err(iadc->dev, "%d is not IADC\n", val);
414		return -EINVAL;
415	}
416
417	ret = iadc_read(iadc, IADC_REVISION2, &val);
418	if (ret < 0)
419		return ret;
420
421	if (val < IADC_REVISION2_SUPPORTED_IADC) {
422		dev_err(iadc->dev, "revision %d not supported\n", val);
423		return -EINVAL;
424	}
425
426	return 0;
427}
428
429static int iadc_rsense_read(struct iadc_chip *iadc, struct device_node *node)
430{
431	int ret, sign, int_sense;
432	u8 deviation;
433
434	ret = of_property_read_u32(node, "qcom,external-resistor-micro-ohms",
435				   &iadc->rsense[IADC_EXT_RSENSE]);
436	if (ret < 0)
437		iadc->rsense[IADC_EXT_RSENSE] = IADC_INT_RSENSE_IDEAL_VALUE;
438
439	if (!iadc->rsense[IADC_EXT_RSENSE]) {
440		dev_err(iadc->dev, "external resistor can't be zero Ohms");
441		return -EINVAL;
442	}
443
444	ret = iadc_read(iadc, IADC_NOMINAL_RSENSE, &deviation);
445	if (ret < 0)
446		return ret;
447
448	/*
449	 * Deviation value stored is an offset from 10 mili Ohms, bit 7 is
450	 * the sign, the remaining bits have an LSB of 15625 nano Ohms.
451	 */
452	sign = (deviation & IADC_NOMINAL_RSENSE_SIGN_MASK) ? -1 : 1;
453
454	deviation &= ~IADC_NOMINAL_RSENSE_SIGN_MASK;
455
456	/* Scale it to nono Ohms */
457	int_sense = IADC_INT_RSENSE_IDEAL_VALUE * 1000;
458	int_sense += sign * deviation * IADC_INT_RSENSE_DEVIATION;
459	int_sense /= 1000; /* micro Ohms */
460
461	iadc->rsense[IADC_INT_RSENSE] = int_sense;
462	return 0;
463}
464
465static const struct iio_chan_spec iadc_channels[] = {
466	{
467		.type = IIO_CURRENT,
468		.datasheet_name	= "INTERNAL_RSENSE",
469		.channel = 0,
470		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
471				      BIT(IIO_CHAN_INFO_SCALE),
472		.indexed = 1,
473	},
474	{
475		.type = IIO_CURRENT,
476		.datasheet_name	= "EXTERNAL_RSENSE",
477		.channel = 1,
478		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
479				      BIT(IIO_CHAN_INFO_SCALE),
480		.indexed = 1,
481	},
482};
483
484static int iadc_probe(struct platform_device *pdev)
485{
486	struct device_node *node = pdev->dev.of_node;
487	struct device *dev = &pdev->dev;
488	struct iio_dev *indio_dev;
489	struct iadc_chip *iadc;
490	int ret, irq_eoc;
491	u32 res;
492
493	indio_dev = devm_iio_device_alloc(dev, sizeof(*iadc));
494	if (!indio_dev)
495		return -ENOMEM;
496
497	iadc = iio_priv(indio_dev);
498	iadc->dev = dev;
499
500	iadc->regmap = dev_get_regmap(dev->parent, NULL);
501	if (!iadc->regmap)
502		return -ENODEV;
503
504	init_completion(&iadc->complete);
505	mutex_init(&iadc->lock);
506
507	ret = of_property_read_u32(node, "reg", &res);
508	if (ret < 0)
509		return -ENODEV;
510
511	iadc->base = res;
512
513	ret = iadc_version_check(iadc);
514	if (ret < 0)
515		return -ENODEV;
516
517	ret = iadc_rsense_read(iadc, node);
518	if (ret < 0)
519		return -ENODEV;
520
521	dev_dbg(iadc->dev, "sense resistors %d and %d micro Ohm\n",
522		iadc->rsense[IADC_INT_RSENSE],
523		iadc->rsense[IADC_EXT_RSENSE]);
524
525	irq_eoc = platform_get_irq(pdev, 0);
526	if (irq_eoc == -EPROBE_DEFER)
527		return irq_eoc;
528
529	if (irq_eoc < 0)
530		iadc->poll_eoc = true;
531
532	ret = iadc_reset(iadc);
533	if (ret < 0) {
534		dev_err(dev, "reset failed\n");
535		return ret;
536	}
537
538	if (!iadc->poll_eoc) {
539		ret = devm_request_irq(dev, irq_eoc, iadc_isr, 0,
540					"spmi-iadc", iadc);
541		if (!ret)
542			enable_irq_wake(irq_eoc);
543		else
544			return ret;
545	} else {
546		device_init_wakeup(iadc->dev, 1);
547	}
548
549	ret = iadc_update_offset(iadc);
550	if (ret < 0) {
551		dev_err(dev, "failed offset calibration\n");
552		return ret;
553	}
554
555	indio_dev->name = pdev->name;
556	indio_dev->modes = INDIO_DIRECT_MODE;
557	indio_dev->info = &iadc_info;
558	indio_dev->channels = iadc_channels;
559	indio_dev->num_channels = ARRAY_SIZE(iadc_channels);
560
561	return devm_iio_device_register(dev, indio_dev);
562}
563
564static const struct of_device_id iadc_match_table[] = {
565	{ .compatible = "qcom,spmi-iadc" },
566	{ }
567};
568
569MODULE_DEVICE_TABLE(of, iadc_match_table);
570
571static struct platform_driver iadc_driver = {
572	.driver = {
573		   .name = "qcom-spmi-iadc",
574		   .of_match_table = iadc_match_table,
575	},
576	.probe = iadc_probe,
577};
578
579module_platform_driver(iadc_driver);
580
581MODULE_ALIAS("platform:qcom-spmi-iadc");
582MODULE_DESCRIPTION("Qualcomm SPMI PMIC current ADC driver");
583MODULE_LICENSE("GPL v2");
584MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
585