1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Analog Devices AD9467 SPI ADC driver 4 * 5 * Copyright 2012-2020 Analog Devices Inc. 6 */ 7#include <linux/cleanup.h> 8#include <linux/module.h> 9#include <linux/mutex.h> 10#include <linux/device.h> 11#include <linux/kernel.h> 12#include <linux/slab.h> 13#include <linux/spi/spi.h> 14#include <linux/err.h> 15#include <linux/delay.h> 16#include <linux/gpio/consumer.h> 17#include <linux/of.h> 18 19 20#include <linux/iio/backend.h> 21#include <linux/iio/iio.h> 22#include <linux/iio/sysfs.h> 23 24#include <linux/clk.h> 25 26/* 27 * ADI High-Speed ADC common spi interface registers 28 * See Application-Note AN-877: 29 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf 30 */ 31 32#define AN877_ADC_REG_CHIP_PORT_CONF 0x00 33#define AN877_ADC_REG_CHIP_ID 0x01 34#define AN877_ADC_REG_CHIP_GRADE 0x02 35#define AN877_ADC_REG_CHAN_INDEX 0x05 36#define AN877_ADC_REG_TRANSFER 0xFF 37#define AN877_ADC_REG_MODES 0x08 38#define AN877_ADC_REG_TEST_IO 0x0D 39#define AN877_ADC_REG_ADC_INPUT 0x0F 40#define AN877_ADC_REG_OFFSET 0x10 41#define AN877_ADC_REG_OUTPUT_MODE 0x14 42#define AN877_ADC_REG_OUTPUT_ADJUST 0x15 43#define AN877_ADC_REG_OUTPUT_PHASE 0x16 44#define AN877_ADC_REG_OUTPUT_DELAY 0x17 45#define AN877_ADC_REG_VREF 0x18 46#define AN877_ADC_REG_ANALOG_INPUT 0x2C 47 48/* AN877_ADC_REG_TEST_IO */ 49#define AN877_ADC_TESTMODE_OFF 0x0 50#define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1 51#define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2 52#define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3 53#define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4 54#define AN877_ADC_TESTMODE_PN23_SEQ 0x5 55#define AN877_ADC_TESTMODE_PN9_SEQ 0x6 56#define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7 57#define AN877_ADC_TESTMODE_USER 0x8 58#define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9 59#define AN877_ADC_TESTMODE_SYNC 0xA 60#define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB 61#define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC 62#define AN877_ADC_TESTMODE_RAMP 0xF 63 64/* AN877_ADC_REG_TRANSFER */ 65#define AN877_ADC_TRANSFER_SYNC 0x1 66 67/* AN877_ADC_REG_OUTPUT_MODE */ 68#define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0 69#define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1 70#define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2 71 72/* AN877_ADC_REG_OUTPUT_PHASE */ 73#define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20 74#define AN877_ADC_INVERT_DCO_CLK 0x80 75 76/* AN877_ADC_REG_OUTPUT_DELAY */ 77#define AN877_ADC_DCO_DELAY_ENABLE 0x80 78 79/* 80 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC 81 */ 82 83#define CHIPID_AD9265 0x64 84#define AD9265_DEF_OUTPUT_MODE 0x40 85#define AD9265_REG_VREF_MASK 0xC0 86 87/* 88 * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC 89 */ 90 91#define CHIPID_AD9434 0x6A 92#define AD9434_DEF_OUTPUT_MODE 0x00 93#define AD9434_REG_VREF_MASK 0xC0 94 95/* 96 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC 97 */ 98 99#define CHIPID_AD9467 0x50 100#define AD9467_DEF_OUTPUT_MODE 0x08 101#define AD9467_REG_VREF_MASK 0x0F 102 103struct ad9467_chip_info { 104 const char *name; 105 unsigned int id; 106 const struct iio_chan_spec *channels; 107 unsigned int num_channels; 108 const unsigned int (*scale_table)[2]; 109 int num_scales; 110 unsigned long max_rate; 111 unsigned int default_output_mode; 112 unsigned int vref_mask; 113}; 114 115struct ad9467_state { 116 const struct ad9467_chip_info *info; 117 struct iio_backend *back; 118 struct spi_device *spi; 119 struct clk *clk; 120 unsigned int output_mode; 121 unsigned int (*scales)[2]; 122 123 struct gpio_desc *pwrdown_gpio; 124 /* ensure consistent state obtained on multiple related accesses */ 125 struct mutex lock; 126}; 127 128static int ad9467_spi_read(struct spi_device *spi, unsigned int reg) 129{ 130 unsigned char tbuf[2], rbuf[1]; 131 int ret; 132 133 tbuf[0] = 0x80 | (reg >> 8); 134 tbuf[1] = reg & 0xFF; 135 136 ret = spi_write_then_read(spi, 137 tbuf, ARRAY_SIZE(tbuf), 138 rbuf, ARRAY_SIZE(rbuf)); 139 140 if (ret < 0) 141 return ret; 142 143 return rbuf[0]; 144} 145 146static int ad9467_spi_write(struct spi_device *spi, unsigned int reg, 147 unsigned int val) 148{ 149 unsigned char buf[3]; 150 151 buf[0] = reg >> 8; 152 buf[1] = reg & 0xFF; 153 buf[2] = val; 154 155 return spi_write(spi, buf, ARRAY_SIZE(buf)); 156} 157 158static int ad9467_reg_access(struct iio_dev *indio_dev, unsigned int reg, 159 unsigned int writeval, unsigned int *readval) 160{ 161 struct ad9467_state *st = iio_priv(indio_dev); 162 struct spi_device *spi = st->spi; 163 int ret; 164 165 if (!readval) { 166 guard(mutex)(&st->lock); 167 ret = ad9467_spi_write(spi, reg, writeval); 168 if (ret) 169 return ret; 170 return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER, 171 AN877_ADC_TRANSFER_SYNC); 172 } 173 174 ret = ad9467_spi_read(spi, reg); 175 if (ret < 0) 176 return ret; 177 *readval = ret; 178 179 return 0; 180} 181 182static const unsigned int ad9265_scale_table[][2] = { 183 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0}, 184}; 185 186static const unsigned int ad9434_scale_table[][2] = { 187 {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00}, 188 {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05}, 189 {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A}, 190 {1200, 0x0B}, {1180, 0x0C}, 191}; 192 193static const unsigned int ad9467_scale_table[][2] = { 194 {2000, 0}, {2100, 6}, {2200, 7}, 195 {2300, 8}, {2400, 9}, {2500, 10}, 196}; 197 198static void __ad9467_get_scale(struct ad9467_state *st, int index, 199 unsigned int *val, unsigned int *val2) 200{ 201 const struct ad9467_chip_info *info = st->info; 202 const struct iio_chan_spec *chan = &info->channels[0]; 203 unsigned int tmp; 204 205 tmp = (info->scale_table[index][0] * 1000000ULL) >> 206 chan->scan_type.realbits; 207 *val = tmp / 1000000; 208 *val2 = tmp % 1000000; 209} 210 211#define AD9467_CHAN(_chan, _si, _bits, _sign) \ 212{ \ 213 .type = IIO_VOLTAGE, \ 214 .indexed = 1, \ 215 .channel = _chan, \ 216 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 217 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 218 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 219 .scan_index = _si, \ 220 .scan_type = { \ 221 .sign = _sign, \ 222 .realbits = _bits, \ 223 .storagebits = 16, \ 224 }, \ 225} 226 227static const struct iio_chan_spec ad9434_channels[] = { 228 AD9467_CHAN(0, 0, 12, 'S'), 229}; 230 231static const struct iio_chan_spec ad9467_channels[] = { 232 AD9467_CHAN(0, 0, 16, 'S'), 233}; 234 235static const struct ad9467_chip_info ad9467_chip_tbl = { 236 .name = "ad9467", 237 .id = CHIPID_AD9467, 238 .max_rate = 250000000UL, 239 .scale_table = ad9467_scale_table, 240 .num_scales = ARRAY_SIZE(ad9467_scale_table), 241 .channels = ad9467_channels, 242 .num_channels = ARRAY_SIZE(ad9467_channels), 243 .default_output_mode = AD9467_DEF_OUTPUT_MODE, 244 .vref_mask = AD9467_REG_VREF_MASK, 245}; 246 247static const struct ad9467_chip_info ad9434_chip_tbl = { 248 .name = "ad9434", 249 .id = CHIPID_AD9434, 250 .max_rate = 500000000UL, 251 .scale_table = ad9434_scale_table, 252 .num_scales = ARRAY_SIZE(ad9434_scale_table), 253 .channels = ad9434_channels, 254 .num_channels = ARRAY_SIZE(ad9434_channels), 255 .default_output_mode = AD9434_DEF_OUTPUT_MODE, 256 .vref_mask = AD9434_REG_VREF_MASK, 257}; 258 259static const struct ad9467_chip_info ad9265_chip_tbl = { 260 .name = "ad9265", 261 .id = CHIPID_AD9265, 262 .max_rate = 125000000UL, 263 .scale_table = ad9265_scale_table, 264 .num_scales = ARRAY_SIZE(ad9265_scale_table), 265 .channels = ad9467_channels, 266 .num_channels = ARRAY_SIZE(ad9467_channels), 267 .default_output_mode = AD9265_DEF_OUTPUT_MODE, 268 .vref_mask = AD9265_REG_VREF_MASK, 269}; 270 271static int ad9467_get_scale(struct ad9467_state *st, int *val, int *val2) 272{ 273 const struct ad9467_chip_info *info = st->info; 274 unsigned int i, vref_val; 275 int ret; 276 277 ret = ad9467_spi_read(st->spi, AN877_ADC_REG_VREF); 278 if (ret < 0) 279 return ret; 280 281 vref_val = ret & info->vref_mask; 282 283 for (i = 0; i < info->num_scales; i++) { 284 if (vref_val == info->scale_table[i][1]) 285 break; 286 } 287 288 if (i == info->num_scales) 289 return -ERANGE; 290 291 __ad9467_get_scale(st, i, val, val2); 292 293 return IIO_VAL_INT_PLUS_MICRO; 294} 295 296static int ad9467_set_scale(struct ad9467_state *st, int val, int val2) 297{ 298 const struct ad9467_chip_info *info = st->info; 299 unsigned int scale_val[2]; 300 unsigned int i; 301 int ret; 302 303 if (val != 0) 304 return -EINVAL; 305 306 for (i = 0; i < info->num_scales; i++) { 307 __ad9467_get_scale(st, i, &scale_val[0], &scale_val[1]); 308 if (scale_val[0] != val || scale_val[1] != val2) 309 continue; 310 311 guard(mutex)(&st->lock); 312 ret = ad9467_spi_write(st->spi, AN877_ADC_REG_VREF, 313 info->scale_table[i][1]); 314 if (ret < 0) 315 return ret; 316 317 return ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER, 318 AN877_ADC_TRANSFER_SYNC); 319 } 320 321 return -EINVAL; 322} 323 324static int ad9467_read_raw(struct iio_dev *indio_dev, 325 struct iio_chan_spec const *chan, 326 int *val, int *val2, long m) 327{ 328 struct ad9467_state *st = iio_priv(indio_dev); 329 330 switch (m) { 331 case IIO_CHAN_INFO_SCALE: 332 return ad9467_get_scale(st, val, val2); 333 case IIO_CHAN_INFO_SAMP_FREQ: 334 *val = clk_get_rate(st->clk); 335 336 return IIO_VAL_INT; 337 default: 338 return -EINVAL; 339 } 340} 341 342static int ad9467_write_raw(struct iio_dev *indio_dev, 343 struct iio_chan_spec const *chan, 344 int val, int val2, long mask) 345{ 346 struct ad9467_state *st = iio_priv(indio_dev); 347 const struct ad9467_chip_info *info = st->info; 348 long r_clk; 349 350 switch (mask) { 351 case IIO_CHAN_INFO_SCALE: 352 return ad9467_set_scale(st, val, val2); 353 case IIO_CHAN_INFO_SAMP_FREQ: 354 r_clk = clk_round_rate(st->clk, val); 355 if (r_clk < 0 || r_clk > info->max_rate) { 356 dev_warn(&st->spi->dev, 357 "Error setting ADC sample rate %ld", r_clk); 358 return -EINVAL; 359 } 360 361 return clk_set_rate(st->clk, r_clk); 362 default: 363 return -EINVAL; 364 } 365} 366 367static int ad9467_read_avail(struct iio_dev *indio_dev, 368 struct iio_chan_spec const *chan, 369 const int **vals, int *type, int *length, 370 long mask) 371{ 372 struct ad9467_state *st = iio_priv(indio_dev); 373 const struct ad9467_chip_info *info = st->info; 374 375 switch (mask) { 376 case IIO_CHAN_INFO_SCALE: 377 *vals = (const int *)st->scales; 378 *type = IIO_VAL_INT_PLUS_MICRO; 379 /* Values are stored in a 2D matrix */ 380 *length = info->num_scales * 2; 381 return IIO_AVAIL_LIST; 382 default: 383 return -EINVAL; 384 } 385} 386 387static int ad9467_update_scan_mode(struct iio_dev *indio_dev, 388 const unsigned long *scan_mask) 389{ 390 struct ad9467_state *st = iio_priv(indio_dev); 391 unsigned int c; 392 int ret; 393 394 for (c = 0; c < st->info->num_channels; c++) { 395 if (test_bit(c, scan_mask)) 396 ret = iio_backend_chan_enable(st->back, c); 397 else 398 ret = iio_backend_chan_disable(st->back, c); 399 if (ret) 400 return ret; 401 } 402 403 return 0; 404} 405 406static const struct iio_info ad9467_info = { 407 .read_raw = ad9467_read_raw, 408 .write_raw = ad9467_write_raw, 409 .update_scan_mode = ad9467_update_scan_mode, 410 .debugfs_reg_access = ad9467_reg_access, 411 .read_avail = ad9467_read_avail, 412}; 413 414static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode) 415{ 416 int ret; 417 418 ret = ad9467_spi_write(spi, AN877_ADC_REG_OUTPUT_MODE, mode); 419 if (ret < 0) 420 return ret; 421 422 return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER, 423 AN877_ADC_TRANSFER_SYNC); 424} 425 426static int ad9467_scale_fill(struct ad9467_state *st) 427{ 428 const struct ad9467_chip_info *info = st->info; 429 unsigned int i, val1, val2; 430 431 st->scales = devm_kmalloc_array(&st->spi->dev, info->num_scales, 432 sizeof(*st->scales), GFP_KERNEL); 433 if (!st->scales) 434 return -ENOMEM; 435 436 for (i = 0; i < info->num_scales; i++) { 437 __ad9467_get_scale(st, i, &val1, &val2); 438 st->scales[i][0] = val1; 439 st->scales[i][1] = val2; 440 } 441 442 return 0; 443} 444 445static int ad9467_setup(struct ad9467_state *st) 446{ 447 struct iio_backend_data_fmt data = { 448 .sign_extend = true, 449 .enable = true, 450 }; 451 unsigned int c, mode; 452 int ret; 453 454 mode = st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT; 455 ret = ad9467_outputmode_set(st->spi, mode); 456 if (ret) 457 return ret; 458 459 for (c = 0; c < st->info->num_channels; c++) { 460 ret = iio_backend_data_format_set(st->back, c, &data); 461 if (ret) 462 return ret; 463 } 464 465 return 0; 466} 467 468static int ad9467_reset(struct device *dev) 469{ 470 struct gpio_desc *gpio; 471 472 gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 473 if (IS_ERR_OR_NULL(gpio)) 474 return PTR_ERR_OR_ZERO(gpio); 475 476 fsleep(1); 477 gpiod_set_value_cansleep(gpio, 0); 478 fsleep(10 * USEC_PER_MSEC); 479 480 return 0; 481} 482 483static int ad9467_iio_backend_get(struct ad9467_state *st) 484{ 485 struct device *dev = &st->spi->dev; 486 struct device_node *__back; 487 488 st->back = devm_iio_backend_get(dev, NULL); 489 if (!IS_ERR(st->back)) 490 return 0; 491 /* If not found, don't error out as we might have legacy DT property */ 492 if (PTR_ERR(st->back) != -ENOENT) 493 return PTR_ERR(st->back); 494 495 /* 496 * if we don't get the backend using the normal API's, use the legacy 497 * 'adi,adc-dev' property. So we get all nodes with that property, and 498 * look for the one pointing at us. Then we directly lookup that fwnode 499 * on the backend list of registered devices. This is done so we don't 500 * make io-backends mandatory which would break DT ABI. 501 */ 502 for_each_node_with_property(__back, "adi,adc-dev") { 503 struct device_node *__me; 504 505 __me = of_parse_phandle(__back, "adi,adc-dev", 0); 506 if (!__me) 507 continue; 508 509 if (!device_match_of_node(dev, __me)) { 510 of_node_put(__me); 511 continue; 512 } 513 514 of_node_put(__me); 515 st->back = __devm_iio_backend_get_from_fwnode_lookup(dev, 516 of_fwnode_handle(__back)); 517 of_node_put(__back); 518 return PTR_ERR_OR_ZERO(st->back); 519 } 520 521 return -ENODEV; 522} 523 524static int ad9467_probe(struct spi_device *spi) 525{ 526 struct iio_dev *indio_dev; 527 struct ad9467_state *st; 528 unsigned int id; 529 int ret; 530 531 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 532 if (!indio_dev) 533 return -ENOMEM; 534 535 st = iio_priv(indio_dev); 536 st->spi = spi; 537 538 st->info = spi_get_device_match_data(spi); 539 if (!st->info) 540 return -ENODEV; 541 542 st->clk = devm_clk_get_enabled(&spi->dev, "adc-clk"); 543 if (IS_ERR(st->clk)) 544 return PTR_ERR(st->clk); 545 546 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown", 547 GPIOD_OUT_LOW); 548 if (IS_ERR(st->pwrdown_gpio)) 549 return PTR_ERR(st->pwrdown_gpio); 550 551 ret = ad9467_reset(&spi->dev); 552 if (ret) 553 return ret; 554 555 ret = ad9467_scale_fill(st); 556 if (ret) 557 return ret; 558 559 id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID); 560 if (id != st->info->id) { 561 dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n", 562 id, st->info->id); 563 return -ENODEV; 564 } 565 566 indio_dev->name = st->info->name; 567 indio_dev->channels = st->info->channels; 568 indio_dev->num_channels = st->info->num_channels; 569 indio_dev->info = &ad9467_info; 570 571 ret = ad9467_iio_backend_get(st); 572 if (ret) 573 return ret; 574 575 ret = devm_iio_backend_request_buffer(&spi->dev, st->back, indio_dev); 576 if (ret) 577 return ret; 578 579 ret = devm_iio_backend_enable(&spi->dev, st->back); 580 if (ret) 581 return ret; 582 583 ret = ad9467_setup(st); 584 if (ret) 585 return ret; 586 587 return devm_iio_device_register(&spi->dev, indio_dev); 588} 589 590static const struct of_device_id ad9467_of_match[] = { 591 { .compatible = "adi,ad9265", .data = &ad9265_chip_tbl, }, 592 { .compatible = "adi,ad9434", .data = &ad9434_chip_tbl, }, 593 { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl, }, 594 {} 595}; 596MODULE_DEVICE_TABLE(of, ad9467_of_match); 597 598static const struct spi_device_id ad9467_ids[] = { 599 { "ad9265", (kernel_ulong_t)&ad9265_chip_tbl }, 600 { "ad9434", (kernel_ulong_t)&ad9434_chip_tbl }, 601 { "ad9467", (kernel_ulong_t)&ad9467_chip_tbl }, 602 {} 603}; 604MODULE_DEVICE_TABLE(spi, ad9467_ids); 605 606static struct spi_driver ad9467_driver = { 607 .driver = { 608 .name = "ad9467", 609 .of_match_table = ad9467_of_match, 610 }, 611 .probe = ad9467_probe, 612 .id_table = ad9467_ids, 613}; 614module_spi_driver(ad9467_driver); 615 616MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 617MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver"); 618MODULE_LICENSE("GPL v2"); 619MODULE_IMPORT_NS(IIO_BACKEND); 620