1175383Sjhb// SPDX-License-Identifier: GPL-2.0 2175383Sjhb/* 3175383Sjhb * Analog Devices AD7768-1 SPI ADC driver 4175383Sjhb * 5175383Sjhb * Copyright 2017 Analog Devices Inc. 6175383Sjhb */ 7175383Sjhb#include <linux/bitfield.h> 8175383Sjhb#include <linux/clk.h> 9175383Sjhb#include <linux/delay.h> 10175383Sjhb#include <linux/device.h> 11175383Sjhb#include <linux/err.h> 12175383Sjhb#include <linux/gpio/consumer.h> 13175383Sjhb#include <linux/kernel.h> 14175383Sjhb#include <linux/module.h> 15175383Sjhb#include <linux/regulator/consumer.h> 16175383Sjhb#include <linux/sysfs.h> 17175383Sjhb#include <linux/spi/spi.h> 18175383Sjhb 19175383Sjhb#include <linux/iio/buffer.h> 20175383Sjhb#include <linux/iio/iio.h> 21175383Sjhb#include <linux/iio/sysfs.h> 22175383Sjhb#include <linux/iio/trigger.h> 23175383Sjhb#include <linux/iio/triggered_buffer.h> 24175383Sjhb#include <linux/iio/trigger_consumer.h> 25175383Sjhb 26175383Sjhb/* AD7768 registers definition */ 27175383Sjhb#define AD7768_REG_CHIP_TYPE 0x3 28175383Sjhb#define AD7768_REG_PROD_ID_L 0x4 29175383Sjhb#define AD7768_REG_PROD_ID_H 0x5 30175383Sjhb#define AD7768_REG_CHIP_GRADE 0x6 31175383Sjhb#define AD7768_REG_SCRATCH_PAD 0x0A 32175383Sjhb#define AD7768_REG_VENDOR_L 0x0C 33175383Sjhb#define AD7768_REG_VENDOR_H 0x0D 34175383Sjhb#define AD7768_REG_INTERFACE_FORMAT 0x14 35175383Sjhb#define AD7768_REG_POWER_CLOCK 0x15 36175383Sjhb#define AD7768_REG_ANALOG 0x16 37175383Sjhb#define AD7768_REG_ANALOG2 0x17 38175383Sjhb#define AD7768_REG_CONVERSION 0x18 39289437Sngie#define AD7768_REG_DIGITAL_FILTER 0x19 40175383Sjhb#define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A 41175383Sjhb#define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B 42175383Sjhb#define AD7768_REG_DUTY_CYCLE_RATIO 0x1C 43175383Sjhb#define AD7768_REG_SYNC_RESET 0x1D 44175383Sjhb#define AD7768_REG_GPIO_CONTROL 0x1E 45289437Sngie#define AD7768_REG_GPIO_WRITE 0x1F 46175383Sjhb#define AD7768_REG_GPIO_READ 0x20 47289437Sngie#define AD7768_REG_OFFSET_HI 0x21 48289437Sngie#define AD7768_REG_OFFSET_MID 0x22 49175383Sjhb#define AD7768_REG_OFFSET_LO 0x23 50289437Sngie#define AD7768_REG_GAIN_HI 0x24 51289437Sngie#define AD7768_REG_GAIN_MID 0x25 52289437Sngie#define AD7768_REG_GAIN_LO 0x26 53289437Sngie#define AD7768_REG_SPI_DIAG_ENABLE 0x28 54299058Sngie#define AD7768_REG_ADC_DIAG_ENABLE 0x29 55299058Sngie#define AD7768_REG_DIG_DIAG_ENABLE 0x2A 56289437Sngie#define AD7768_REG_ADC_DATA 0x2C 57289437Sngie#define AD7768_REG_MASTER_STATUS 0x2D 58289437Sngie#define AD7768_REG_SPI_DIAG_STATUS 0x2E 59289437Sngie#define AD7768_REG_ADC_DIAG_STATUS 0x2F 60289437Sngie#define AD7768_REG_DIG_DIAG_STATUS 0x30 61289437Sngie#define AD7768_REG_MCLK_COUNTER 0x31 62289437Sngie 63175383Sjhb/* AD7768_REG_POWER_CLOCK */ 64175383Sjhb#define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4) 65175383Sjhb#define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x) 66175383Sjhb#define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0) 67175383Sjhb#define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x) 68175383Sjhb 69175383Sjhb/* AD7768_REG_DIGITAL_FILTER */ 70175383Sjhb#define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4) 71175383Sjhb#define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x) 72289437Sngie#define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) 73289437Sngie#define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) 74289437Sngie 75289437Sngie/* AD7768_REG_CONVERSION */ 76175383Sjhb#define AD7768_CONV_MODE_MSK GENMASK(2, 0) 77175383Sjhb#define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) 78175383Sjhb 79175383Sjhb#define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F)) 80175383Sjhb#define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F) 81175383Sjhb 82175383Sjhbenum ad7768_conv_mode { 83175383Sjhb AD7768_CONTINUOUS, 84175383Sjhb AD7768_ONE_SHOT, 85289437Sngie AD7768_SINGLE, 86289437Sngie AD7768_PERIODIC, 87289437Sngie AD7768_STANDBY 88289437Sngie}; 89175383Sjhb 90175383Sjhbenum ad7768_pwrmode { 91175383Sjhb AD7768_ECO_MODE = 0, 92175383Sjhb AD7768_MED_MODE = 2, 93175383Sjhb AD7768_FAST_MODE = 3 94175383Sjhb}; 95175383Sjhb 96175383Sjhbenum ad7768_mclk_div { 97175383Sjhb AD7768_MCLK_DIV_16, 98175383Sjhb AD7768_MCLK_DIV_8, 99299058Sngie AD7768_MCLK_DIV_4, 100175383Sjhb AD7768_MCLK_DIV_2 101289437Sngie}; 102289437Sngie 103299058Sngieenum ad7768_dec_rate { 104299058Sngie AD7768_DEC_RATE_32 = 0, 105289437Sngie AD7768_DEC_RATE_64 = 1, 106175383Sjhb AD7768_DEC_RATE_128 = 2, 107289437Sngie AD7768_DEC_RATE_256 = 3, 108289437Sngie AD7768_DEC_RATE_512 = 4, 109289437Sngie AD7768_DEC_RATE_1024 = 5, 110175383Sjhb AD7768_DEC_RATE_8 = 9, 111289437Sngie AD7768_DEC_RATE_16 = 10 112289441Sngie}; 113299058Sngie 114289441Sngiestruct ad7768_clk_configuration { 115175383Sjhb enum ad7768_mclk_div mclk_div; 116299058Sngie enum ad7768_dec_rate dec_rate; 117289437Sngie unsigned int clk_div; 118289441Sngie enum ad7768_pwrmode pwrmode; 119175383Sjhb}; 120175383Sjhb 121299058Sngiestatic const struct ad7768_clk_configuration ad7768_clk_config[] = { 122299058Sngie { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, 123175383Sjhb { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, 124175383Sjhb { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE }, 125175383Sjhb { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE }, 126175383Sjhb { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE }, 127289437Sngie { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE }, 128289437Sngie { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE }, 129175383Sjhb { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE }, 130175383Sjhb { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE }, 131299058Sngie { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE }, 132175383Sjhb { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, 133299058Sngie}; 134299058Sngie 135175383Sjhbstatic const struct iio_chan_spec ad7768_channels[] = { 136175383Sjhb { 137299058Sngie .type = IIO_VOLTAGE, 138289441Sngie .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 139289441Sngie .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 140175383Sjhb .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 141289441Sngie .indexed = 1, 142289441Sngie .channel = 0, 143175383Sjhb .scan_index = 0, 144175383Sjhb .scan_type = { 145299058Sngie .sign = 'u', 146299058Sngie .realbits = 24, 147175383Sjhb .storagebits = 32, 148289441Sngie .shift = 8, 149289441Sngie .endianness = IIO_BE, 150175383Sjhb }, 151175383Sjhb }, 152289437Sngie}; 153289437Sngie 154175383Sjhbstruct ad7768_state { 155175383Sjhb struct spi_device *spi; 156299058Sngie struct regulator *vref; 157175383Sjhb struct mutex lock; 158299058Sngie struct clk *mclk; 159299058Sngie unsigned int mclk_freq; 160175383Sjhb unsigned int samp_freq; 161175383Sjhb struct completion completion; 162175383Sjhb struct iio_trigger *trig; 163289437Sngie struct gpio_desc *gpio_sync_in; 164289441Sngie const char *labels[ARRAY_SIZE(ad7768_channels)]; 165289441Sngie /* 166289441Sngie * DMA (thus cache coherency maintenance) may require the 167299058Sngie * transfer buffers to live in their own cache lines. 168289441Sngie */ 169289441Sngie union { 170175383Sjhb struct { 171289441Sngie __be32 chan; 172289441Sngie s64 timestamp; 173175383Sjhb } scan; 174299058Sngie __be32 d32; 175299058Sngie u8 d8[2]; 176175383Sjhb } data __aligned(IIO_DMA_MINALIGN); 177289441Sngie}; 178289441Sngie 179175383Sjhbstatic int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr, 180175383Sjhb unsigned int len) 181289437Sngie{ 182289437Sngie unsigned int shift; 183175383Sjhb int ret; 184175383Sjhb 185299058Sngie shift = 32 - (8 * len); 186175383Sjhb st->data.d8[0] = AD7768_RD_FLAG_MSK(addr); 187299058Sngie 188299058Sngie ret = spi_write_then_read(st->spi, st->data.d8, 1, 189289437Sngie &st->data.d32, len); 190289437Sngie if (ret < 0) 191289437Sngie return ret; 192289441Sngie 193175383Sjhb return (be32_to_cpu(st->data.d32) >> shift); 194175383Sjhb} 195299058Sngie 196289441Sngiestatic int ad7768_spi_reg_write(struct ad7768_state *st, 197289441Sngie unsigned int addr, 198175383Sjhb unsigned int val) 199289441Sngie{ 200289441Sngie st->data.d8[0] = AD7768_WR_FLAG_MSK(addr); 201289441Sngie st->data.d8[1] = val & 0xFF; 202289441Sngie 203175383Sjhb return spi_write(st->spi, st->data.d8, 2); 204289441Sngie} 205289441Sngie 206175383Sjhbstatic int ad7768_set_mode(struct ad7768_state *st, 207175383Sjhb enum ad7768_conv_mode mode) 208289437Sngie{ 209289437Sngie int regval; 210175383Sjhb 211175383Sjhb regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1); 212175383Sjhb if (regval < 0) 213289437Sngie return regval; 214289437Sngie 215289437Sngie regval &= ~AD7768_CONV_MODE_MSK; 216289441Sngie regval |= AD7768_CONV_MODE(mode); 217175383Sjhb 218175383Sjhb return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval); 219289441Sngie} 220289441Sngie 221175383Sjhbstatic int ad7768_scan_direct(struct iio_dev *indio_dev) 222289437Sngie{ 223175383Sjhb struct ad7768_state *st = iio_priv(indio_dev); 224175383Sjhb int readval, ret; 225289437Sngie 226289437Sngie reinit_completion(&st->completion); 227175383Sjhb 228175383Sjhb ret = ad7768_set_mode(st, AD7768_ONE_SHOT); 229175383Sjhb if (ret < 0) 230175383Sjhb return ret; 231175383Sjhb 232289437Sngie ret = wait_for_completion_timeout(&st->completion, 233289437Sngie msecs_to_jiffies(1000)); 234175383Sjhb if (!ret) 235175383Sjhb return -ETIMEDOUT; 236289437Sngie 237289437Sngie readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); 238289437Sngie if (readval < 0) 239175383Sjhb return readval; 240175383Sjhb /* 241289437Sngie * Any SPI configuration of the AD7768-1 can only be 242289437Sngie * performed in continuous conversion mode. 243175383Sjhb */ 244175383Sjhb ret = ad7768_set_mode(st, AD7768_CONTINUOUS); 245289437Sngie if (ret < 0) 246289437Sngie return ret; 247289437Sngie 248175383Sjhb return readval; 249175383Sjhb} 250289437Sngie 251289437Sngiestatic int ad7768_reg_access(struct iio_dev *indio_dev, 252175383Sjhb unsigned int reg, 253175383Sjhb unsigned int writeval, 254175383Sjhb unsigned int *readval) 255175383Sjhb{ 256289441Sngie struct ad7768_state *st = iio_priv(indio_dev); 257175383Sjhb int ret; 258175383Sjhb 259175383Sjhb mutex_lock(&st->lock); 260289437Sngie if (readval) { 261289437Sngie ret = ad7768_spi_reg_read(st, reg, 1); 262175383Sjhb if (ret < 0) 263175383Sjhb goto err_unlock; 264175383Sjhb *readval = ret; 265175383Sjhb ret = 0; 266175383Sjhb } else { 267289437Sngie ret = ad7768_spi_reg_write(st, reg, writeval); 268289437Sngie } 269175383Sjhberr_unlock: 270175383Sjhb mutex_unlock(&st->lock); 271175383Sjhb 272175383Sjhb return ret; 273175383Sjhb} 274289437Sngie 275289437Sngiestatic int ad7768_set_dig_fil(struct ad7768_state *st, 276175383Sjhb enum ad7768_dec_rate dec_rate) 277175383Sjhb{ 278175383Sjhb unsigned int mode; 279175383Sjhb int ret; 280175383Sjhb 281175383Sjhb if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16) 282175383Sjhb mode = AD7768_DIG_FIL_FIL(dec_rate); 283175383Sjhb else 284175383Sjhb mode = AD7768_DIG_FIL_DEC_RATE(dec_rate); 285175383Sjhb 286289437Sngie ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode); 287289437Sngie if (ret < 0) 288175383Sjhb return ret; 289175383Sjhb 290175383Sjhb /* A sync-in pulse is required every time the filter dec rate changes */ 291175383Sjhb gpiod_set_value(st->gpio_sync_in, 1); 292175383Sjhb gpiod_set_value(st->gpio_sync_in, 0); 293289437Sngie 294289437Sngie return 0; 295175383Sjhb} 296175383Sjhb 297175383Sjhbstatic int ad7768_set_freq(struct ad7768_state *st, 298289437Sngie unsigned int freq) 299289437Sngie{ 300289437Sngie unsigned int diff_new, diff_old, pwr_mode, i, idx; 301289441Sngie int res, ret; 302175383Sjhb 303175383Sjhb diff_old = U32_MAX; 304289437Sngie idx = 0; 305175383Sjhb 306175383Sjhb res = DIV_ROUND_CLOSEST(st->mclk_freq, freq); 307289441Sngie 308289441Sngie /* Find the closest match for the desired sampling frequency */ 309175383Sjhb for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { 310175383Sjhb diff_new = abs(res - ad7768_clk_config[i].clk_div); 311289437Sngie if (diff_new < diff_old) { 312289437Sngie diff_old = diff_new; 313175383Sjhb idx = i; 314175383Sjhb } 315175383Sjhb } 316175383Sjhb 317289437Sngie /* 318289437Sngie * Set both the mclk_div and pwrmode with a single write to the 319175383Sjhb * POWER_CLOCK register 320289437Sngie */ 321289441Sngie pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) | 322289441Sngie AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode); 323289441Sngie ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode); 324289441Sngie if (ret < 0) 325289441Sngie return ret; 326289441Sngie 327175383Sjhb ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate); 328175383Sjhb if (ret < 0) 329175383Sjhb return ret; 330289437Sngie 331289441Sngie st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, 332289441Sngie ad7768_clk_config[idx].clk_div); 333289441Sngie 334289441Sngie return 0; 335289441Sngie} 336175383Sjhb 337289441Sngiestatic ssize_t ad7768_sampling_freq_avail(struct device *dev, 338289441Sngie struct device_attribute *attr, 339175383Sjhb char *buf) 340175383Sjhb{ 341289437Sngie struct iio_dev *indio_dev = dev_to_iio_dev(dev); 342289437Sngie struct ad7768_state *st = iio_priv(indio_dev); 343175383Sjhb unsigned int freq; 344175383Sjhb int i, len = 0; 345175383Sjhb 346175383Sjhb for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { 347175383Sjhb freq = DIV_ROUND_CLOSEST(st->mclk_freq, 348289437Sngie ad7768_clk_config[i].clk_div); 349289437Sngie len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq); 350175383Sjhb } 351175383Sjhb 352175383Sjhb buf[len - 1] = '\n'; 353175383Sjhb 354175383Sjhb return len; 355175383Sjhb} 356175383Sjhb 357175383Sjhbstatic IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail); 358175383Sjhb 359175383Sjhbstatic int ad7768_read_raw(struct iio_dev *indio_dev, 360289437Sngie struct iio_chan_spec const *chan, 361289437Sngie int *val, int *val2, long info) 362175383Sjhb{ 363175383Sjhb struct ad7768_state *st = iio_priv(indio_dev); 364175383Sjhb int scale_uv, ret; 365299058Sngie 366299058Sngie switch (info) { 367175383Sjhb case IIO_CHAN_INFO_RAW: 368299058Sngie ret = iio_device_claim_direct_mode(indio_dev); 369299058Sngie if (ret) 370175383Sjhb return ret; 371289441Sngie 372289441Sngie ret = ad7768_scan_direct(indio_dev); 373289441Sngie if (ret >= 0) 374175383Sjhb *val = ret; 375299058Sngie 376289441Sngie iio_device_release_direct_mode(indio_dev); 377289441Sngie if (ret < 0) 378289441Sngie return ret; 379289441Sngie 380289441Sngie return IIO_VAL_INT; 381299058Sngie 382289441Sngie case IIO_CHAN_INFO_SCALE: 383299058Sngie scale_uv = regulator_get_voltage(st->vref); 384289441Sngie if (scale_uv < 0) 385175383Sjhb return scale_uv; 386299058Sngie 387289441Sngie *val = (scale_uv * 2) / 1000; 388289437Sngie *val2 = chan->scan_type.realbits; 389175383Sjhb 390175383Sjhb return IIO_VAL_FRACTIONAL_LOG2; 391175383Sjhb 392299058Sngie case IIO_CHAN_INFO_SAMP_FREQ: 393299058Sngie *val = st->samp_freq; 394175383Sjhb 395175383Sjhb return IIO_VAL_INT; 396299058Sngie } 397289441Sngie 398175383Sjhb return -EINVAL; 399289441Sngie} 400289441Sngie 401289441Sngiestatic int ad7768_write_raw(struct iio_dev *indio_dev, 402299058Sngie struct iio_chan_spec const *chan, 403289441Sngie int val, int val2, long info) 404299058Sngie{ 405289441Sngie struct ad7768_state *st = iio_priv(indio_dev); 406175383Sjhb 407299058Sngie switch (info) { 408289441Sngie case IIO_CHAN_INFO_SAMP_FREQ: 409289441Sngie return ad7768_set_freq(st, val); 410175383Sjhb default: 411289441Sngie return -EINVAL; 412289441Sngie } 413175383Sjhb} 414175383Sjhb 415299058Sngiestatic int ad7768_read_label(struct iio_dev *indio_dev, 416175383Sjhb const struct iio_chan_spec *chan, char *label) 417175383Sjhb{ 418299058Sngie struct ad7768_state *st = iio_priv(indio_dev); 419289441Sngie 420175383Sjhb return sprintf(label, "%s\n", st->labels[chan->channel]); 421289441Sngie} 422289441Sngie 423289441Sngiestatic struct attribute *ad7768_attributes[] = { 424299058Sngie &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 425289441Sngie NULL 426299058Sngie}; 427289441Sngie 428175383Sjhbstatic const struct attribute_group ad7768_group = { 429175383Sjhb .attrs = ad7768_attributes, 430175383Sjhb}; 431175383Sjhb 432175383Sjhbstatic const struct iio_info ad7768_info = { 433289441Sngie .attrs = &ad7768_group, 434289441Sngie .read_raw = &ad7768_read_raw, 435175383Sjhb .write_raw = &ad7768_write_raw, 436175383Sjhb .read_label = ad7768_read_label, 437175383Sjhb .debugfs_reg_access = &ad7768_reg_access, 438175383Sjhb}; 439175383Sjhb 440175383Sjhbstatic int ad7768_setup(struct ad7768_state *st) 441299058Sngie{ 442175383Sjhb int ret; 443299058Sngie 444175383Sjhb /* 445175383Sjhb * Two writes to the SPI_RESET[1:0] bits are required to initiate 446175383Sjhb * a software reset. The bits must first be set to 11, and then 447175383Sjhb * to 10. When the sequence is detected, the reset occurs. 448175383Sjhb * See the datasheet, page 70. 449175383Sjhb */ 450299058Sngie ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3); 451175383Sjhb if (ret) 452175383Sjhb return ret; 453175383Sjhb 454289441Sngie ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2); 455289441Sngie if (ret) 456289441Sngie return ret; 457289441Sngie 458289441Sngie st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in", 459289437Sngie GPIOD_OUT_LOW); 460175383Sjhb if (IS_ERR(st->gpio_sync_in)) 461175383Sjhb return PTR_ERR(st->gpio_sync_in); 462299058Sngie 463289441Sngie /* Set the default sampling frequency to 32000 kSPS */ 464175383Sjhb return ad7768_set_freq(st, 32000); 465289441Sngie} 466289441Sngie 467289441Sngiestatic irqreturn_t ad7768_trigger_handler(int irq, void *p) 468299058Sngie{ 469289441Sngie struct iio_poll_func *pf = p; 470299058Sngie struct iio_dev *indio_dev = pf->indio_dev; 471289441Sngie struct ad7768_state *st = iio_priv(indio_dev); 472175383Sjhb int ret; 473175383Sjhb 474175383Sjhb mutex_lock(&st->lock); 475175383Sjhb 476175383Sjhb ret = spi_read(st->spi, &st->data.scan.chan, 3); 477175383Sjhb if (ret < 0) 478175383Sjhb goto err_unlock; 479175383Sjhb 480175383Sjhb iio_push_to_buffers_with_timestamp(indio_dev, &st->data.scan, 481299058Sngie iio_get_time_ns(indio_dev)); 482289441Sngie 483299058Sngieerr_unlock: 484175383Sjhb iio_trigger_notify_done(indio_dev->trig); 485175383Sjhb mutex_unlock(&st->lock); 486175383Sjhb 487175383Sjhb return IRQ_HANDLED; 488289437Sngie} 489289437Sngie 490289437Sngiestatic irqreturn_t ad7768_interrupt(int irq, void *dev_id) 491175383Sjhb{ 492289437Sngie struct iio_dev *indio_dev = dev_id; 493289437Sngie struct ad7768_state *st = iio_priv(indio_dev); 494175383Sjhb 495289437Sngie if (iio_buffer_enabled(indio_dev)) 496289437Sngie iio_trigger_poll(st->trig); 497289437Sngie else 498289437Sngie complete(&st->completion); 499289437Sngie 500289437Sngie return IRQ_HANDLED; 501289437Sngie}; 502289437Sngie 503289437Sngiestatic int ad7768_buffer_postenable(struct iio_dev *indio_dev) 504289437Sngie{ 505289437Sngie struct ad7768_state *st = iio_priv(indio_dev); 506289437Sngie 507289437Sngie /* 508289437Sngie * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter 509289437Sngie * continuous read mode. Subsequent data reads do not require an 510289437Sngie * initial 8-bit write to query the ADC_DATA register. 511289437Sngie */ 512289437Sngie return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01); 513289437Sngie} 514289437Sngie 515289437Sngiestatic int ad7768_buffer_predisable(struct iio_dev *indio_dev) 516289437Sngie{ 517289437Sngie struct ad7768_state *st = iio_priv(indio_dev); 518289437Sngie 519289437Sngie /* 520289437Sngie * To exit continuous read mode, perform a single read of the ADC_DATA 521289437Sngie * reg (0x2C), which allows further configuration of the device. 522289437Sngie */ 523289437Sngie return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); 524289437Sngie} 525289437Sngie 526289437Sngiestatic const struct iio_buffer_setup_ops ad7768_buffer_ops = { 527289437Sngie .postenable = &ad7768_buffer_postenable, 528289437Sngie .predisable = &ad7768_buffer_predisable, 529289437Sngie}; 530299058Sngie 531289437Sngiestatic const struct iio_trigger_ops ad7768_trigger_ops = { 532289437Sngie .validate_device = iio_trigger_validate_own_device, 533289437Sngie}; 534289437Sngie 535289437Sngiestatic void ad7768_regulator_disable(void *data) 536289437Sngie{ 537289437Sngie struct ad7768_state *st = data; 538289437Sngie 539289437Sngie regulator_disable(st->vref); 540289437Sngie} 541289437Sngie 542289437Sngiestatic int ad7768_set_channel_label(struct iio_dev *indio_dev, 543289437Sngie int num_channels) 544289437Sngie{ 545289437Sngie struct ad7768_state *st = iio_priv(indio_dev); 546289437Sngie struct device *device = indio_dev->dev.parent; 547289437Sngie struct fwnode_handle *fwnode; 548299058Sngie struct fwnode_handle *child; 549289437Sngie const char *label; 550289437Sngie int crt_ch = 0; 551289437Sngie 552289437Sngie fwnode = dev_fwnode(device); 553289437Sngie fwnode_for_each_child_node(fwnode, child) { 554289437Sngie if (fwnode_property_read_u32(child, "reg", &crt_ch)) 555289437Sngie continue; 556289437Sngie 557289437Sngie if (crt_ch >= num_channels) 558289437Sngie continue; 559289437Sngie 560289437Sngie if (fwnode_property_read_string(child, "label", &label)) 561289437Sngie continue; 562289437Sngie 563289437Sngie st->labels[crt_ch] = label; 564289437Sngie } 565289437Sngie 566289437Sngie return 0; 567289437Sngie} 568289437Sngie 569289437Sngiestatic int ad7768_probe(struct spi_device *spi) 570289437Sngie{ 571289437Sngie struct ad7768_state *st; 572289437Sngie struct iio_dev *indio_dev; 573289437Sngie int ret; 574289437Sngie 575289437Sngie indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 576289437Sngie if (!indio_dev) 577289437Sngie return -ENOMEM; 578289437Sngie 579289437Sngie st = iio_priv(indio_dev); 580289437Sngie st->spi = spi; 581289437Sngie 582289437Sngie st->vref = devm_regulator_get(&spi->dev, "vref"); 583289437Sngie if (IS_ERR(st->vref)) 584289437Sngie return PTR_ERR(st->vref); 585289437Sngie 586289437Sngie ret = regulator_enable(st->vref); 587289437Sngie if (ret) { 588289437Sngie dev_err(&spi->dev, "Failed to enable specified vref supply\n"); 589289437Sngie return ret; 590289437Sngie } 591289437Sngie 592289437Sngie ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st); 593289437Sngie if (ret) 594289437Sngie return ret; 595289437Sngie 596289437Sngie st->mclk = devm_clk_get_enabled(&spi->dev, "mclk"); 597289437Sngie if (IS_ERR(st->mclk)) 598289437Sngie return PTR_ERR(st->mclk); 599289437Sngie 600289437Sngie st->mclk_freq = clk_get_rate(st->mclk); 601289437Sngie 602289437Sngie mutex_init(&st->lock); 603289437Sngie 604289437Sngie indio_dev->channels = ad7768_channels; 605289437Sngie indio_dev->num_channels = ARRAY_SIZE(ad7768_channels); 606299058Sngie indio_dev->name = spi_get_device_id(spi)->name; 607299058Sngie indio_dev->info = &ad7768_info; 608299058Sngie indio_dev->modes = INDIO_DIRECT_MODE; 609299058Sngie 610175383Sjhb ret = ad7768_setup(st); 611289437Sngie if (ret < 0) { 612289437Sngie dev_err(&spi->dev, "AD7768 setup failed\n"); 613289437Sngie return ret; 614289437Sngie } 615289437Sngie 616289437Sngie st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d", 617289437Sngie indio_dev->name, 618289437Sngie iio_device_id(indio_dev)); 619289437Sngie if (!st->trig) 620289437Sngie return -ENOMEM; 621289437Sngie 622289437Sngie st->trig->ops = &ad7768_trigger_ops; 623289437Sngie iio_trigger_set_drvdata(st->trig, indio_dev); 624289437Sngie ret = devm_iio_trigger_register(&spi->dev, st->trig); 625289437Sngie if (ret) 626289437Sngie return ret; 627289437Sngie 628289437Sngie indio_dev->trig = iio_trigger_get(st->trig); 629289437Sngie 630289437Sngie init_completion(&st->completion); 631289437Sngie 632289437Sngie ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels)); 633289437Sngie if (ret) 634289437Sngie return ret; 635289437Sngie 636 ret = devm_request_irq(&spi->dev, spi->irq, 637 &ad7768_interrupt, 638 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 639 indio_dev->name, indio_dev); 640 if (ret) 641 return ret; 642 643 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 644 &iio_pollfunc_store_time, 645 &ad7768_trigger_handler, 646 &ad7768_buffer_ops); 647 if (ret) 648 return ret; 649 650 return devm_iio_device_register(&spi->dev, indio_dev); 651} 652 653static const struct spi_device_id ad7768_id_table[] = { 654 { "ad7768-1", 0 }, 655 {} 656}; 657MODULE_DEVICE_TABLE(spi, ad7768_id_table); 658 659static const struct of_device_id ad7768_of_match[] = { 660 { .compatible = "adi,ad7768-1" }, 661 { }, 662}; 663MODULE_DEVICE_TABLE(of, ad7768_of_match); 664 665static struct spi_driver ad7768_driver = { 666 .driver = { 667 .name = "ad7768-1", 668 .of_match_table = ad7768_of_match, 669 }, 670 .probe = ad7768_probe, 671 .id_table = ad7768_id_table, 672}; 673module_spi_driver(ad7768_driver); 674 675MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 676MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver"); 677MODULE_LICENSE("GPL v2"); 678