1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * AD7606 ADC driver 4 * 5 * Copyright 2011 Analog Devices Inc. 6 */ 7 8#ifndef IIO_ADC_AD7606_H_ 9#define IIO_ADC_AD7606_H_ 10 11#define AD760X_CHANNEL(num, mask_sep, mask_type, mask_all) { \ 12 .type = IIO_VOLTAGE, \ 13 .indexed = 1, \ 14 .channel = num, \ 15 .address = num, \ 16 .info_mask_separate = mask_sep, \ 17 .info_mask_shared_by_type = mask_type, \ 18 .info_mask_shared_by_all = mask_all, \ 19 .scan_index = num, \ 20 .scan_type = { \ 21 .sign = 's', \ 22 .realbits = 16, \ 23 .storagebits = 16, \ 24 .endianness = IIO_CPU, \ 25 }, \ 26} 27 28#define AD7605_CHANNEL(num) \ 29 AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW), \ 30 BIT(IIO_CHAN_INFO_SCALE), 0) 31 32#define AD7606_CHANNEL(num) \ 33 AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW), \ 34 BIT(IIO_CHAN_INFO_SCALE), \ 35 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)) 36 37#define AD7616_CHANNEL(num) \ 38 AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),\ 39 0, BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)) 40 41/** 42 * struct ad7606_chip_info - chip specific information 43 * @channels: channel specification 44 * @num_channels: number of channels 45 * @oversampling_avail pointer to the array which stores the available 46 * oversampling ratios. 47 * @oversampling_num number of elements stored in oversampling_avail array 48 * @os_req_reset some devices require a reset to update oversampling 49 * @init_delay_ms required delay in miliseconds for initialization 50 * after a restart 51 */ 52struct ad7606_chip_info { 53 const struct iio_chan_spec *channels; 54 unsigned int num_channels; 55 const unsigned int *oversampling_avail; 56 unsigned int oversampling_num; 57 bool os_req_reset; 58 unsigned long init_delay_ms; 59}; 60 61/** 62 * struct ad7606_state - driver instance specific data 63 * @dev pointer to kernel device 64 * @chip_info entry in the table of chips that describes this device 65 * @bops bus operations (SPI or parallel) 66 * @range voltage range selection, selects which scale to apply 67 * @oversampling oversampling selection 68 * @base_address address from where to read data in parallel operation 69 * @sw_mode_en software mode enabled 70 * @scale_avail pointer to the array which stores the available scales 71 * @num_scales number of elements stored in the scale_avail array 72 * @oversampling_avail pointer to the array which stores the available 73 * oversampling ratios. 74 * @num_os_ratios number of elements stored in oversampling_avail array 75 * @write_scale pointer to the function which writes the scale 76 * @write_os pointer to the function which writes the os 77 * @lock protect sensor state from concurrent accesses to GPIOs 78 * @gpio_convst GPIO descriptor for conversion start signal (CONVST) 79 * @gpio_reset GPIO descriptor for device hard-reset 80 * @gpio_range GPIO descriptor for range selection 81 * @gpio_standby GPIO descriptor for stand-by signal (STBY), 82 * controls power-down mode of device 83 * @gpio_frstdata GPIO descriptor for reading from device when data 84 * is being read on the first channel 85 * @gpio_os GPIO descriptors to control oversampling on the device 86 * @complete completion to indicate end of conversion 87 * @trig The IIO trigger associated with the device. 88 * @data buffer for reading data from the device 89 * @d16 be16 buffer for reading data from the device 90 */ 91struct ad7606_state { 92 struct device *dev; 93 const struct ad7606_chip_info *chip_info; 94 const struct ad7606_bus_ops *bops; 95 unsigned int range[16]; 96 unsigned int oversampling; 97 void __iomem *base_address; 98 bool sw_mode_en; 99 const unsigned int *scale_avail; 100 unsigned int num_scales; 101 const unsigned int *oversampling_avail; 102 unsigned int num_os_ratios; 103 int (*write_scale)(struct iio_dev *indio_dev, int ch, int val); 104 int (*write_os)(struct iio_dev *indio_dev, int val); 105 106 struct mutex lock; /* protect sensor state */ 107 struct gpio_desc *gpio_convst; 108 struct gpio_desc *gpio_reset; 109 struct gpio_desc *gpio_range; 110 struct gpio_desc *gpio_standby; 111 struct gpio_desc *gpio_frstdata; 112 struct gpio_descs *gpio_os; 113 struct iio_trigger *trig; 114 struct completion completion; 115 116 /* 117 * DMA (thus cache coherency maintenance) may require the 118 * transfer buffers to live in their own cache lines. 119 * 16 * 16-bit samples + 64-bit timestamp 120 */ 121 unsigned short data[20] __aligned(IIO_DMA_MINALIGN); 122 __be16 d16[2]; 123}; 124 125/** 126 * struct ad7606_bus_ops - driver bus operations 127 * @read_block function pointer for reading blocks of data 128 * @sw_mode_config: pointer to a function which configured the device 129 * for software mode 130 * @reg_read function pointer for reading spi register 131 * @reg_write function pointer for writing spi register 132 * @write_mask function pointer for write spi register with mask 133 * @rd_wr_cmd pointer to the function which calculates the spi address 134 */ 135struct ad7606_bus_ops { 136 /* more methods added in future? */ 137 int (*read_block)(struct device *dev, int num, void *data); 138 int (*sw_mode_config)(struct iio_dev *indio_dev); 139 int (*reg_read)(struct ad7606_state *st, unsigned int addr); 140 int (*reg_write)(struct ad7606_state *st, 141 unsigned int addr, 142 unsigned int val); 143 int (*write_mask)(struct ad7606_state *st, 144 unsigned int addr, 145 unsigned long mask, 146 unsigned int val); 147 u16 (*rd_wr_cmd)(int addr, char isWriteOp); 148}; 149 150int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, 151 const char *name, unsigned int id, 152 const struct ad7606_bus_ops *bops); 153 154enum ad7606_supported_device_ids { 155 ID_AD7605_4, 156 ID_AD7606_8, 157 ID_AD7606_6, 158 ID_AD7606_4, 159 ID_AD7606B, 160 ID_AD7616, 161}; 162 163#ifdef CONFIG_PM_SLEEP 164extern const struct dev_pm_ops ad7606_pm_ops; 165#define AD7606_PM_OPS (&ad7606_pm_ops) 166#else 167#define AD7606_PM_OPS NULL 168#endif 169 170#endif /* IIO_ADC_AD7606_H_ */ 171