1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Murata SCA3300 3-axis industrial accelerometer
4 *
5 * Copyright (c) 2021 Vaisala Oyj. All rights reserved.
6 */
7
8#include <linux/bitops.h>
9#include <linux/crc8.h>
10#include <linux/delay.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/spi/spi.h>
14
15#include <asm/unaligned.h>
16
17#include <linux/iio/buffer.h>
18#include <linux/iio/iio.h>
19#include <linux/iio/sysfs.h>
20#include <linux/iio/trigger_consumer.h>
21#include <linux/iio/triggered_buffer.h>
22
23#define SCA3300_ALIAS "sca3300"
24
25#define SCA3300_CRC8_POLYNOMIAL 0x1d
26
27/* Device mode register */
28#define SCA3300_REG_MODE	0xd
29#define SCA3300_MODE_SW_RESET	0x20
30
31/* Last register in map */
32#define SCA3300_REG_SELBANK	0x1f
33
34/* Device status and mask */
35#define SCA3300_REG_STATUS	0x6
36#define SCA3300_STATUS_MASK	GENMASK(8, 0)
37
38/* Device ID */
39#define SCA3300_REG_WHOAMI	0x10
40#define SCA3300_WHOAMI_ID	0x51
41#define SCL3300_WHOAMI_ID	0xC1
42
43/* Device return status and mask */
44#define SCA3300_VALUE_RS_ERROR	0x3
45#define SCA3300_MASK_RS_STATUS	GENMASK(1, 0)
46
47#define SCL3300_REG_ANG_CTRL 0x0C
48#define SCL3300_ANG_ENABLE   0x1F
49
50enum sca3300_scan_indexes {
51	SCA3300_ACC_X = 0,
52	SCA3300_ACC_Y,
53	SCA3300_ACC_Z,
54	SCA3300_TEMP,
55	SCA3300_INCLI_X,
56	SCA3300_INCLI_Y,
57	SCA3300_INCLI_Z,
58	SCA3300_SCAN_MAX
59};
60
61/*
62 * Buffer size max case:
63 * Three accel channels, two bytes per channel.
64 * Temperature channel, two bytes.
65 * Three incli channels, two bytes per channel.
66 * Timestamp channel, eight bytes.
67 */
68#define SCA3300_MAX_BUFFER_SIZE (ALIGN(sizeof(s16) * SCA3300_SCAN_MAX, sizeof(s64)) + sizeof(s64))
69
70#define SCA3300_ACCEL_CHANNEL(index, reg, axis) {			\
71	.type = IIO_ACCEL,						\
72	.address = reg,							\
73	.modified = 1,							\
74	.channel2 = IIO_MOD_##axis,					\
75	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
76	.info_mask_shared_by_type =					\
77	BIT(IIO_CHAN_INFO_SCALE) |					\
78	BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),		\
79	.info_mask_shared_by_type_available =				\
80	BIT(IIO_CHAN_INFO_SCALE) |					\
81	BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),		\
82	.scan_index = index,						\
83	.scan_type = {							\
84		.sign = 's',						\
85		.realbits = 16,						\
86		.storagebits = 16,					\
87		.endianness = IIO_CPU,					\
88	},								\
89}
90
91#define SCA3300_INCLI_CHANNEL(index, reg, axis) {			\
92	.type = IIO_INCLI,						\
93	.address = reg,							\
94	.modified = 1,							\
95	.channel2 = IIO_MOD_##axis,					\
96	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),		\
97	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
98	.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
99	.scan_index = index,						\
100	.scan_type = {							\
101		.sign = 's',						\
102		.realbits = 16,						\
103		.storagebits = 16,					\
104		.endianness = IIO_CPU,					\
105	},								\
106}
107
108#define SCA3300_TEMP_CHANNEL(index, reg) {				\
109		.type = IIO_TEMP,					\
110		.address = reg,						\
111		.scan_index = index,					\
112		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
113		.scan_type = {						\
114			.sign = 's',					\
115			.realbits = 16,					\
116			.storagebits = 16,				\
117			.endianness = IIO_CPU,				\
118		},							\
119}
120
121static const struct iio_chan_spec sca3300_channels[] = {
122	SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X),
123	SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y),
124	SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z),
125	SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05),
126	IIO_CHAN_SOFT_TIMESTAMP(4),
127};
128
129static const int sca3300_lp_freq[] = {70, 10};
130static const int sca3300_lp_freq_map[] = {0, 0, 0, 1};
131
132static const int scl3300_lp_freq[] = {40, 70, 10};
133static const int scl3300_lp_freq_map[] = {0, 1, 2};
134
135static const int sca3300_accel_scale[][2] = {{0, 370}, {0, 741}, {0, 185}};
136static const int sca3300_accel_scale_map[] = {0, 1, 2, 2};
137
138static const int scl3300_accel_scale[][2] = {{0, 167}, {0, 333}, {0, 83}};
139static const int scl3300_accel_scale_map[] = {0, 1, 2};
140
141static const int scl3300_incli_scale[][2] = {{0, 5495}};
142static const int scl3300_incli_scale_map[] = {0, 0, 0};
143
144static const int sca3300_avail_modes_map[] = {0, 1, 2, 3};
145static const int scl3300_avail_modes_map[] = {0, 1, 3};
146
147static const struct iio_chan_spec scl3300_channels[] = {
148	SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X),
149	SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y),
150	SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z),
151	SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05),
152	SCA3300_INCLI_CHANNEL(SCA3300_INCLI_X, 0x09, X),
153	SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Y, 0x0A, Y),
154	SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Z, 0x0B, Z),
155	IIO_CHAN_SOFT_TIMESTAMP(7),
156};
157
158static const unsigned long sca3300_scan_masks[] = {
159	BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) |
160	BIT(SCA3300_TEMP),
161	0
162};
163
164static const unsigned long scl3300_scan_masks[] = {
165	BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) |
166	BIT(SCA3300_TEMP) |
167	BIT(SCA3300_INCLI_X) | BIT(SCA3300_INCLI_Y) | BIT(SCA3300_INCLI_Z),
168	0
169};
170
171struct sca3300_chip_info {
172	const char *name;
173	const unsigned long *scan_masks;
174	const struct iio_chan_spec *channels;
175	u8 num_channels;
176	u8 num_accel_scales;
177	const int (*accel_scale)[2];
178	const int *accel_scale_map;
179	const int (*incli_scale)[2];
180	const int *incli_scale_map;
181	u8 num_incli_scales;
182	u8 num_freqs;
183	const int *freq_table;
184	const int *freq_map;
185	const int *avail_modes_table;
186	u8 num_avail_modes;
187	u8 chip_id;
188	bool angle_supported;
189};
190
191/**
192 * struct sca3300_data - device data
193 * @spi: SPI device structure
194 * @lock: Data buffer lock
195 * @chip: Sensor chip specific information
196 * @buffer: Triggered buffer:
197 *          -SCA3300: 4 channel 16-bit data + 64-bit timestamp
198 *          -SCL3300: 7 channel 16-bit data + 64-bit timestamp
199 * @txbuf: Transmit buffer
200 * @rxbuf: Receive buffer
201 */
202struct sca3300_data {
203	struct spi_device *spi;
204	struct mutex lock;
205	const struct sca3300_chip_info *chip;
206	u8 buffer[SCA3300_MAX_BUFFER_SIZE] __aligned(sizeof(s64));
207	u8 txbuf[4] __aligned(IIO_DMA_MINALIGN);
208	u8 rxbuf[4];
209};
210
211static const struct sca3300_chip_info sca3300_chip_tbl[] = {
212	{
213		.name = "sca3300",
214		.scan_masks = sca3300_scan_masks,
215		.channels = sca3300_channels,
216		.num_channels = ARRAY_SIZE(sca3300_channels),
217		.num_accel_scales = ARRAY_SIZE(sca3300_accel_scale)*2,
218		.accel_scale = sca3300_accel_scale,
219		.accel_scale_map = sca3300_accel_scale_map,
220		.num_freqs = ARRAY_SIZE(sca3300_lp_freq),
221		.freq_table = sca3300_lp_freq,
222		.freq_map = sca3300_lp_freq_map,
223		.avail_modes_table = sca3300_avail_modes_map,
224		.num_avail_modes = 4,
225		.chip_id = SCA3300_WHOAMI_ID,
226		.angle_supported = false,
227	},
228	{
229		.name = "scl3300",
230		.scan_masks = scl3300_scan_masks,
231		.channels = scl3300_channels,
232		.num_channels = ARRAY_SIZE(scl3300_channels),
233		.num_accel_scales = ARRAY_SIZE(scl3300_accel_scale)*2,
234		.accel_scale = scl3300_accel_scale,
235		.accel_scale_map = scl3300_accel_scale_map,
236		.incli_scale = scl3300_incli_scale,
237		.incli_scale_map = scl3300_incli_scale_map,
238		.num_incli_scales =  ARRAY_SIZE(scl3300_incli_scale)*2,
239		.num_freqs = ARRAY_SIZE(scl3300_lp_freq),
240		.freq_table = scl3300_lp_freq,
241		.freq_map = scl3300_lp_freq_map,
242		.avail_modes_table = scl3300_avail_modes_map,
243		.num_avail_modes = 3,
244		.chip_id = SCL3300_WHOAMI_ID,
245		.angle_supported = true,
246	},
247};
248
249DECLARE_CRC8_TABLE(sca3300_crc_table);
250
251static int sca3300_transfer(struct sca3300_data *sca_data, int *val)
252{
253	/* Consecutive requests min. 10 us delay (Datasheet section 5.1.2) */
254	struct spi_delay delay = { .value = 10, .unit = SPI_DELAY_UNIT_USECS };
255	int32_t ret;
256	int rs;
257	u8 crc;
258	struct spi_transfer xfers[2] = {
259		{
260			.tx_buf = sca_data->txbuf,
261			.len = ARRAY_SIZE(sca_data->txbuf),
262			.delay = delay,
263			.cs_change = 1,
264		},
265		{
266			.rx_buf = sca_data->rxbuf,
267			.len = ARRAY_SIZE(sca_data->rxbuf),
268			.delay = delay,
269		}
270	};
271
272	/* inverted crc value as described in device data sheet */
273	crc = ~crc8(sca3300_crc_table, &sca_data->txbuf[0], 3, CRC8_INIT_VALUE);
274	sca_data->txbuf[3] = crc;
275
276	ret = spi_sync_transfer(sca_data->spi, xfers, ARRAY_SIZE(xfers));
277	if (ret) {
278		dev_err(&sca_data->spi->dev,
279			"transfer error, error: %d\n", ret);
280		return -EIO;
281	}
282
283	crc = ~crc8(sca3300_crc_table, &sca_data->rxbuf[0], 3, CRC8_INIT_VALUE);
284	if (sca_data->rxbuf[3] != crc) {
285		dev_err(&sca_data->spi->dev, "CRC checksum mismatch");
286		return -EIO;
287	}
288
289	/* get return status */
290	rs = sca_data->rxbuf[0] & SCA3300_MASK_RS_STATUS;
291	if (rs == SCA3300_VALUE_RS_ERROR)
292		ret = -EINVAL;
293
294	*val = sign_extend32(get_unaligned_be16(&sca_data->rxbuf[1]), 15);
295
296	return ret;
297}
298
299static int sca3300_error_handler(struct sca3300_data *sca_data)
300{
301	int ret;
302	int val;
303
304	mutex_lock(&sca_data->lock);
305	sca_data->txbuf[0] = SCA3300_REG_STATUS << 2;
306	ret = sca3300_transfer(sca_data, &val);
307	mutex_unlock(&sca_data->lock);
308	/*
309	 * Return status error is cleared after reading status register once,
310	 * expect EINVAL here.
311	 */
312	if (ret != -EINVAL) {
313		dev_err(&sca_data->spi->dev,
314			"error reading device status: %d\n", ret);
315		return ret;
316	}
317
318	dev_err(&sca_data->spi->dev, "device status: 0x%lx\n",
319		val & SCA3300_STATUS_MASK);
320
321	return 0;
322}
323
324static int sca3300_read_reg(struct sca3300_data *sca_data, u8 reg, int *val)
325{
326	int ret;
327
328	mutex_lock(&sca_data->lock);
329	sca_data->txbuf[0] = reg << 2;
330	ret = sca3300_transfer(sca_data, val);
331	mutex_unlock(&sca_data->lock);
332	if (ret != -EINVAL)
333		return ret;
334
335	return sca3300_error_handler(sca_data);
336}
337
338static int sca3300_write_reg(struct sca3300_data *sca_data, u8 reg, int val)
339{
340	int reg_val = 0;
341	int ret;
342
343	mutex_lock(&sca_data->lock);
344	/* BIT(7) for write operation */
345	sca_data->txbuf[0] = BIT(7) | (reg << 2);
346	put_unaligned_be16(val, &sca_data->txbuf[1]);
347	ret = sca3300_transfer(sca_data, &reg_val);
348	mutex_unlock(&sca_data->lock);
349	if (ret != -EINVAL)
350		return ret;
351
352	return sca3300_error_handler(sca_data);
353}
354
355static int sca3300_set_op_mode(struct sca3300_data *sca_data, int index)
356{
357	if ((index < 0) || (index >= sca_data->chip->num_avail_modes))
358		return -EINVAL;
359
360	return sca3300_write_reg(sca_data, SCA3300_REG_MODE,
361				 sca_data->chip->avail_modes_table[index]);
362}
363
364static int sca3300_get_op_mode(struct sca3300_data *sca_data, int *index)
365{
366	int reg_val;
367	int ret;
368	int i;
369
370	ret = sca3300_read_reg(sca_data, SCA3300_REG_MODE, &reg_val);
371	if (ret)
372		return ret;
373
374	for (i = 0; i < sca_data->chip->num_avail_modes; i++) {
375		if (sca_data->chip->avail_modes_table[i] == reg_val)
376			break;
377	}
378	if (i == sca_data->chip->num_avail_modes)
379		return -EINVAL;
380
381	*index = i;
382	return 0;
383}
384
385static int sca3300_set_frequency(struct sca3300_data *data, int val)
386{
387	const struct sca3300_chip_info *chip = data->chip;
388	unsigned int index;
389	int *opmode_scale;
390	int *new_scale;
391	unsigned int i;
392
393	if (sca3300_get_op_mode(data, &index))
394		return -EINVAL;
395
396	/*
397	 * Find a mode in which the requested sampling frequency is available
398	 * and the scaling currently set is retained.
399	 */
400	opmode_scale = (int *)chip->accel_scale[chip->accel_scale_map[index]];
401	for (i = 0; i < chip->num_avail_modes; i++) {
402		new_scale = (int *)chip->accel_scale[chip->accel_scale_map[i]];
403		if ((val == chip->freq_table[chip->freq_map[i]]) &&
404		    (opmode_scale[1] == new_scale[1]) &&
405		    (opmode_scale[0] == new_scale[0]))
406			break;
407	}
408	if (i == chip->num_avail_modes)
409		return -EINVAL;
410
411	return sca3300_set_op_mode(data, i);
412}
413
414static int sca3300_write_raw(struct iio_dev *indio_dev,
415			     struct iio_chan_spec const *chan,
416			     int val, int val2, long mask)
417{
418	struct sca3300_data *data = iio_priv(indio_dev);
419	int index;
420	int i;
421
422	switch (mask) {
423	case IIO_CHAN_INFO_SCALE:
424		if (chan->type != IIO_ACCEL)
425			return -EINVAL;
426		/*
427		 * Letting scale take priority over sampling frequency.
428		 * That makes sense given we can only ever end up increasing
429		 * the sampling frequency which is unlikely to be a problem.
430		 */
431		for (i = 0; i < data->chip->num_avail_modes; i++) {
432			index = data->chip->accel_scale_map[i];
433			if ((val  == data->chip->accel_scale[index][0]) &&
434			    (val2 == data->chip->accel_scale[index][1]))
435				return sca3300_set_op_mode(data, i);
436		}
437		return -EINVAL;
438	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
439		return sca3300_set_frequency(data, val);
440	default:
441		return -EINVAL;
442	}
443}
444
445static int sca3300_read_raw(struct iio_dev *indio_dev,
446			    struct iio_chan_spec const *chan,
447			    int *val, int *val2, long mask)
448{
449	struct sca3300_data *data = iio_priv(indio_dev);
450	int index;
451	int ret;
452
453	switch (mask) {
454	case IIO_CHAN_INFO_RAW:
455		ret = sca3300_read_reg(data, chan->address, val);
456		if (ret)
457			return ret;
458		return IIO_VAL_INT;
459	case IIO_CHAN_INFO_SCALE:
460		ret = sca3300_get_op_mode(data, &index);
461		if (ret)
462			return ret;
463		switch (chan->type) {
464		case IIO_INCLI:
465			index = data->chip->incli_scale_map[index];
466			*val  = data->chip->incli_scale[index][0];
467			*val2 = data->chip->incli_scale[index][1];
468			return IIO_VAL_INT_PLUS_MICRO;
469		case IIO_ACCEL:
470			index = data->chip->accel_scale_map[index];
471			*val  = data->chip->accel_scale[index][0];
472			*val2 = data->chip->accel_scale[index][1];
473			return IIO_VAL_INT_PLUS_MICRO;
474		default:
475			return -EINVAL;
476		}
477	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
478		ret = sca3300_get_op_mode(data, &index);
479		if (ret)
480			return ret;
481		index = data->chip->freq_map[index];
482		*val = data->chip->freq_table[index];
483		return IIO_VAL_INT;
484	default:
485		return -EINVAL;
486	}
487}
488
489static irqreturn_t sca3300_trigger_handler(int irq, void *p)
490{
491	struct iio_poll_func *pf = p;
492	struct iio_dev *indio_dev = pf->indio_dev;
493	struct sca3300_data *data = iio_priv(indio_dev);
494	int bit, ret, val, i = 0;
495	s16 *channels = (s16 *)data->buffer;
496
497	for_each_set_bit(bit, indio_dev->active_scan_mask,
498			 indio_dev->masklength) {
499		ret = sca3300_read_reg(data, indio_dev->channels[bit].address, &val);
500		if (ret) {
501			dev_err_ratelimited(&data->spi->dev,
502				"failed to read register, error: %d\n", ret);
503			/* handled, but bailing out due to errors */
504			goto out;
505		}
506		channels[i++] = val;
507	}
508
509	iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
510					   iio_get_time_ns(indio_dev));
511out:
512	iio_trigger_notify_done(indio_dev->trig);
513
514	return IRQ_HANDLED;
515}
516
517/*
518 * sca3300_init - Device init sequence. See datasheet rev 2 section
519 * 4.2 Start-Up Sequence for details.
520 */
521static int sca3300_init(struct sca3300_data *sca_data,
522			struct iio_dev *indio_dev)
523{
524	int value = 0;
525	int ret;
526	int i;
527
528	ret = sca3300_write_reg(sca_data, SCA3300_REG_MODE,
529				SCA3300_MODE_SW_RESET);
530	if (ret)
531		return ret;
532
533	/*
534	 * Wait 1ms after SW-reset command.
535	 * Wait for the settling of signal paths,
536	 * 15ms for SCA3300 and 25ms for SCL3300,
537	 */
538	usleep_range(26e3, 50e3);
539
540	ret = sca3300_read_reg(sca_data, SCA3300_REG_WHOAMI, &value);
541	if (ret)
542		return ret;
543
544	for (i = 0; i < ARRAY_SIZE(sca3300_chip_tbl); i++) {
545		if (sca3300_chip_tbl[i].chip_id == value)
546			break;
547	}
548	if (i == ARRAY_SIZE(sca3300_chip_tbl)) {
549		dev_err(&sca_data->spi->dev, "unknown chip id %x\n", value);
550		return -ENODEV;
551	}
552
553	sca_data->chip = &sca3300_chip_tbl[i];
554
555	if (sca_data->chip->angle_supported) {
556		ret = sca3300_write_reg(sca_data, SCL3300_REG_ANG_CTRL,
557					SCL3300_ANG_ENABLE);
558		if (ret)
559			return ret;
560	}
561
562	return 0;
563}
564
565static int sca3300_debugfs_reg_access(struct iio_dev *indio_dev,
566				      unsigned int reg, unsigned int writeval,
567				      unsigned int *readval)
568{
569	struct sca3300_data *data = iio_priv(indio_dev);
570	int value;
571	int ret;
572
573	if (reg > SCA3300_REG_SELBANK)
574		return -EINVAL;
575
576	if (!readval)
577		return sca3300_write_reg(data, reg, writeval);
578
579	ret = sca3300_read_reg(data, reg, &value);
580	if (ret)
581		return ret;
582
583	*readval = value;
584
585	return 0;
586}
587
588static int sca3300_read_avail(struct iio_dev *indio_dev,
589			      struct iio_chan_spec const *chan,
590			      const int **vals, int *type, int *length,
591			      long mask)
592{
593	struct sca3300_data *data = iio_priv(indio_dev);
594	switch (mask) {
595	case IIO_CHAN_INFO_SCALE:
596		switch (chan->type) {
597		case IIO_INCLI:
598			*vals = (const int *)data->chip->incli_scale;
599			*length = data->chip->num_incli_scales;
600			*type = IIO_VAL_INT_PLUS_MICRO;
601			return IIO_AVAIL_LIST;
602		case IIO_ACCEL:
603			*vals = (const int *)data->chip->accel_scale;
604			*length = data->chip->num_accel_scales;
605			*type = IIO_VAL_INT_PLUS_MICRO;
606			return IIO_AVAIL_LIST;
607		default:
608			return -EINVAL;
609		}
610	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
611		*vals = (const int *)data->chip->freq_table;
612		*length = data->chip->num_freqs;
613		*type = IIO_VAL_INT;
614		return IIO_AVAIL_LIST;
615	default:
616		return -EINVAL;
617	}
618}
619
620static const struct iio_info sca3300_info = {
621	.read_raw = sca3300_read_raw,
622	.write_raw = sca3300_write_raw,
623	.debugfs_reg_access = &sca3300_debugfs_reg_access,
624	.read_avail = sca3300_read_avail,
625};
626
627static int sca3300_probe(struct spi_device *spi)
628{
629	struct sca3300_data *sca_data;
630	struct iio_dev *indio_dev;
631	int ret;
632
633	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*sca_data));
634	if (!indio_dev)
635		return -ENOMEM;
636
637	sca_data = iio_priv(indio_dev);
638	mutex_init(&sca_data->lock);
639	sca_data->spi = spi;
640
641	crc8_populate_msb(sca3300_crc_table, SCA3300_CRC8_POLYNOMIAL);
642
643	indio_dev->info = &sca3300_info;
644
645	ret = sca3300_init(sca_data, indio_dev);
646	if (ret) {
647		dev_err(&spi->dev, "failed to init device, error: %d\n", ret);
648		return ret;
649	}
650
651	indio_dev->name = sca_data->chip->name;
652	indio_dev->modes = INDIO_DIRECT_MODE;
653	indio_dev->channels = sca_data->chip->channels;
654	indio_dev->num_channels = sca_data->chip->num_channels;
655	indio_dev->available_scan_masks = sca_data->chip->scan_masks;
656
657	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
658					      iio_pollfunc_store_time,
659					      sca3300_trigger_handler, NULL);
660	if (ret) {
661		dev_err(&spi->dev,
662			"iio triggered buffer setup failed, error: %d\n", ret);
663		return ret;
664	}
665
666	ret = devm_iio_device_register(&spi->dev, indio_dev);
667	if (ret) {
668		dev_err(&spi->dev, "iio device register failed, error: %d\n",
669			ret);
670	}
671
672	return ret;
673}
674
675static const struct of_device_id sca3300_dt_ids[] = {
676	{ .compatible = "murata,sca3300"},
677	{ .compatible = "murata,scl3300"},
678	{}
679};
680MODULE_DEVICE_TABLE(of, sca3300_dt_ids);
681
682static const struct spi_device_id sca3300_ids[] = {
683	{ "sca3300" },
684	{ "scl3300" },
685	{}
686};
687MODULE_DEVICE_TABLE(spi, sca3300_ids);
688
689static struct spi_driver sca3300_driver = {
690	.driver   = {
691		.name		= SCA3300_ALIAS,
692		.of_match_table = sca3300_dt_ids,
693	},
694	.probe	  = sca3300_probe,
695	.id_table = sca3300_ids,
696};
697module_spi_driver(sca3300_driver);
698
699MODULE_AUTHOR("Tomas Melin <tomas.melin@vaisala.com>");
700MODULE_DESCRIPTION("Murata SCA3300 SPI Accelerometer");
701MODULE_LICENSE("GPL v2");
702