1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * 3-axis accelerometer driver for MXC4005XC Memsic sensor
4 *
5 * Copyright (c) 2014, Intel Corporation.
6 */
7
8#include <linux/delay.h>
9#include <linux/module.h>
10#include <linux/i2c.h>
11#include <linux/iio/iio.h>
12#include <linux/mod_devicetable.h>
13#include <linux/regmap.h>
14#include <linux/iio/sysfs.h>
15#include <linux/iio/trigger.h>
16#include <linux/iio/buffer.h>
17#include <linux/iio/triggered_buffer.h>
18#include <linux/iio/trigger_consumer.h>
19
20#define MXC4005_DRV_NAME		"mxc4005"
21#define MXC4005_IRQ_NAME		"mxc4005_event"
22#define MXC4005_REGMAP_NAME		"mxc4005_regmap"
23
24#define MXC4005_REG_XOUT_UPPER		0x03
25#define MXC4005_REG_XOUT_LOWER		0x04
26#define MXC4005_REG_YOUT_UPPER		0x05
27#define MXC4005_REG_YOUT_LOWER		0x06
28#define MXC4005_REG_ZOUT_UPPER		0x07
29#define MXC4005_REG_ZOUT_LOWER		0x08
30
31#define MXC4005_REG_INT_MASK0		0x0A
32
33#define MXC4005_REG_INT_MASK1		0x0B
34#define MXC4005_REG_INT_MASK1_BIT_DRDYE	0x01
35
36#define MXC4005_REG_INT_CLR0		0x00
37
38#define MXC4005_REG_INT_CLR1		0x01
39#define MXC4005_REG_INT_CLR1_BIT_DRDYC	0x01
40#define MXC4005_REG_INT_CLR1_SW_RST	0x10
41
42#define MXC4005_REG_CONTROL		0x0D
43#define MXC4005_REG_CONTROL_MASK_FSR	GENMASK(6, 5)
44#define MXC4005_CONTROL_FSR_SHIFT	5
45
46#define MXC4005_REG_DEVICE_ID		0x0E
47
48/* Datasheet does not specify a reset time, this is a conservative guess */
49#define MXC4005_RESET_TIME_US		2000
50
51enum mxc4005_axis {
52	AXIS_X,
53	AXIS_Y,
54	AXIS_Z,
55};
56
57enum mxc4005_range {
58	MXC4005_RANGE_2G,
59	MXC4005_RANGE_4G,
60	MXC4005_RANGE_8G,
61};
62
63struct mxc4005_data {
64	struct device *dev;
65	struct mutex mutex;
66	struct regmap *regmap;
67	struct iio_trigger *dready_trig;
68	/* Ensure timestamp is naturally aligned */
69	struct {
70		__be16 chans[3];
71		s64 timestamp __aligned(8);
72	} scan;
73	bool trigger_enabled;
74	unsigned int control;
75	unsigned int int_mask1;
76};
77
78/*
79 * MXC4005 can operate in the following ranges:
80 * +/- 2G, 4G, 8G (the default +/-2G)
81 *
82 * (2 + 2) * 9.81 / (2^12 - 1) = 0.009582
83 * (4 + 4) * 9.81 / (2^12 - 1) = 0.019164
84 * (8 + 8) * 9.81 / (2^12 - 1) = 0.038329
85 */
86static const struct {
87	u8 range;
88	int scale;
89} mxc4005_scale_table[] = {
90	{MXC4005_RANGE_2G, 9582},
91	{MXC4005_RANGE_4G, 19164},
92	{MXC4005_RANGE_8G, 38329},
93};
94
95
96static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329");
97
98static struct attribute *mxc4005_attributes[] = {
99	&iio_const_attr_in_accel_scale_available.dev_attr.attr,
100	NULL,
101};
102
103static const struct attribute_group mxc4005_attrs_group = {
104	.attrs = mxc4005_attributes,
105};
106
107static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg)
108{
109	switch (reg) {
110	case MXC4005_REG_XOUT_UPPER:
111	case MXC4005_REG_XOUT_LOWER:
112	case MXC4005_REG_YOUT_UPPER:
113	case MXC4005_REG_YOUT_LOWER:
114	case MXC4005_REG_ZOUT_UPPER:
115	case MXC4005_REG_ZOUT_LOWER:
116	case MXC4005_REG_DEVICE_ID:
117	case MXC4005_REG_CONTROL:
118		return true;
119	default:
120		return false;
121	}
122}
123
124static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg)
125{
126	switch (reg) {
127	case MXC4005_REG_INT_CLR0:
128	case MXC4005_REG_INT_CLR1:
129	case MXC4005_REG_INT_MASK0:
130	case MXC4005_REG_INT_MASK1:
131	case MXC4005_REG_CONTROL:
132		return true;
133	default:
134		return false;
135	}
136}
137
138static const struct regmap_config mxc4005_regmap_config = {
139	.name = MXC4005_REGMAP_NAME,
140
141	.reg_bits = 8,
142	.val_bits = 8,
143
144	.max_register = MXC4005_REG_DEVICE_ID,
145
146	.readable_reg = mxc4005_is_readable_reg,
147	.writeable_reg = mxc4005_is_writeable_reg,
148};
149
150static int mxc4005_read_xyz(struct mxc4005_data *data)
151{
152	int ret;
153
154	ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER,
155			       data->scan.chans, sizeof(data->scan.chans));
156	if (ret < 0) {
157		dev_err(data->dev, "failed to read axes\n");
158		return ret;
159	}
160
161	return 0;
162}
163
164static int mxc4005_read_axis(struct mxc4005_data *data,
165			     unsigned int addr)
166{
167	__be16 reg;
168	int ret;
169
170	ret = regmap_bulk_read(data->regmap, addr, &reg, sizeof(reg));
171	if (ret < 0) {
172		dev_err(data->dev, "failed to read reg %02x\n", addr);
173		return ret;
174	}
175
176	return be16_to_cpu(reg);
177}
178
179static int mxc4005_read_scale(struct mxc4005_data *data)
180{
181	unsigned int reg;
182	int ret;
183	int i;
184
185	ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, &reg);
186	if (ret < 0) {
187		dev_err(data->dev, "failed to read reg_control\n");
188		return ret;
189	}
190
191	i = reg >> MXC4005_CONTROL_FSR_SHIFT;
192
193	if (i < 0 || i >= ARRAY_SIZE(mxc4005_scale_table))
194		return -EINVAL;
195
196	return mxc4005_scale_table[i].scale;
197}
198
199static int mxc4005_set_scale(struct mxc4005_data *data, int val)
200{
201	unsigned int reg;
202	int i;
203	int ret;
204
205	for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) {
206		if (mxc4005_scale_table[i].scale == val) {
207			reg = i << MXC4005_CONTROL_FSR_SHIFT;
208			ret = regmap_update_bits(data->regmap,
209						 MXC4005_REG_CONTROL,
210						 MXC4005_REG_CONTROL_MASK_FSR,
211						 reg);
212			if (ret < 0)
213				dev_err(data->dev,
214					"failed to write reg_control\n");
215			return ret;
216		}
217	}
218
219	return -EINVAL;
220}
221
222static int mxc4005_read_raw(struct iio_dev *indio_dev,
223			    struct iio_chan_spec const *chan,
224			    int *val, int *val2, long mask)
225{
226	struct mxc4005_data *data = iio_priv(indio_dev);
227	int ret;
228
229	switch (mask) {
230	case IIO_CHAN_INFO_RAW:
231		switch (chan->type) {
232		case IIO_ACCEL:
233			if (iio_buffer_enabled(indio_dev))
234				return -EBUSY;
235
236			ret = mxc4005_read_axis(data, chan->address);
237			if (ret < 0)
238				return ret;
239			*val = sign_extend32(ret >> chan->scan_type.shift,
240					     chan->scan_type.realbits - 1);
241			return IIO_VAL_INT;
242		default:
243			return -EINVAL;
244		}
245	case IIO_CHAN_INFO_SCALE:
246		ret = mxc4005_read_scale(data);
247		if (ret < 0)
248			return ret;
249
250		*val = 0;
251		*val2 = ret;
252		return IIO_VAL_INT_PLUS_MICRO;
253	default:
254		return -EINVAL;
255	}
256}
257
258static int mxc4005_write_raw(struct iio_dev *indio_dev,
259			     struct iio_chan_spec const *chan,
260			     int val, int val2, long mask)
261{
262	struct mxc4005_data *data = iio_priv(indio_dev);
263
264	switch (mask) {
265	case IIO_CHAN_INFO_SCALE:
266		if (val != 0)
267			return -EINVAL;
268
269		return mxc4005_set_scale(data, val2);
270	default:
271		return -EINVAL;
272	}
273}
274
275static const struct iio_info mxc4005_info = {
276	.read_raw	= mxc4005_read_raw,
277	.write_raw	= mxc4005_write_raw,
278	.attrs		= &mxc4005_attrs_group,
279};
280
281static const unsigned long mxc4005_scan_masks[] = {
282	BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
283	0
284};
285
286#define MXC4005_CHANNEL(_axis, _addr) {				\
287	.type = IIO_ACCEL,					\
288	.modified = 1,						\
289	.channel2 = IIO_MOD_##_axis,				\
290	.address = _addr,					\
291	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
292	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
293	.scan_index = AXIS_##_axis,				\
294	.scan_type = {						\
295		.sign = 's',					\
296		.realbits = 12,					\
297		.storagebits = 16,				\
298		.shift = 4,					\
299		.endianness = IIO_BE,				\
300	},							\
301}
302
303static const struct iio_chan_spec mxc4005_channels[] = {
304	MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER),
305	MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER),
306	MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER),
307	IIO_CHAN_SOFT_TIMESTAMP(3),
308};
309
310static irqreturn_t mxc4005_trigger_handler(int irq, void *private)
311{
312	struct iio_poll_func *pf = private;
313	struct iio_dev *indio_dev = pf->indio_dev;
314	struct mxc4005_data *data = iio_priv(indio_dev);
315	int ret;
316
317	ret = mxc4005_read_xyz(data);
318	if (ret < 0)
319		goto err;
320
321	iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
322					   pf->timestamp);
323
324err:
325	iio_trigger_notify_done(indio_dev->trig);
326
327	return IRQ_HANDLED;
328}
329
330static void mxc4005_clr_intr(struct mxc4005_data *data)
331{
332	int ret;
333
334	/* clear interrupt */
335	ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1,
336			   MXC4005_REG_INT_CLR1_BIT_DRDYC);
337	if (ret < 0)
338		dev_err(data->dev, "failed to write to reg_int_clr1\n");
339}
340
341static int mxc4005_set_trigger_state(struct iio_trigger *trig,
342				     bool state)
343{
344	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
345	struct mxc4005_data *data = iio_priv(indio_dev);
346	unsigned int val;
347	int ret;
348
349	mutex_lock(&data->mutex);
350
351	val = state ? MXC4005_REG_INT_MASK1_BIT_DRDYE : 0;
352	ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, val);
353	if (ret < 0) {
354		mutex_unlock(&data->mutex);
355		dev_err(data->dev, "failed to update reg_int_mask1");
356		return ret;
357	}
358
359	data->int_mask1 = val;
360	data->trigger_enabled = state;
361	mutex_unlock(&data->mutex);
362
363	return 0;
364}
365
366static void mxc4005_trigger_reen(struct iio_trigger *trig)
367{
368	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
369	struct mxc4005_data *data = iio_priv(indio_dev);
370
371	if (!data->dready_trig)
372		return;
373
374	mxc4005_clr_intr(data);
375}
376
377static const struct iio_trigger_ops mxc4005_trigger_ops = {
378	.set_trigger_state = mxc4005_set_trigger_state,
379	.reenable = mxc4005_trigger_reen,
380};
381
382static int mxc4005_chip_init(struct mxc4005_data *data)
383{
384	int ret;
385	unsigned int reg;
386
387	ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, &reg);
388	if (ret < 0) {
389		dev_err(data->dev, "failed to read chip id\n");
390		return ret;
391	}
392
393	dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg);
394
395	ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1,
396			   MXC4005_REG_INT_CLR1_SW_RST);
397	if (ret < 0)
398		return dev_err_probe(data->dev, ret, "resetting chip\n");
399
400	fsleep(MXC4005_RESET_TIME_US);
401
402	ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK0, 0);
403	if (ret < 0)
404		return dev_err_probe(data->dev, ret, "writing INT_MASK0\n");
405
406	ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, 0);
407	if (ret < 0)
408		return dev_err_probe(data->dev, ret, "writing INT_MASK1\n");
409
410	return 0;
411}
412
413static int mxc4005_probe(struct i2c_client *client)
414{
415	struct mxc4005_data *data;
416	struct iio_dev *indio_dev;
417	struct regmap *regmap;
418	int ret;
419
420	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
421	if (!indio_dev)
422		return -ENOMEM;
423
424	regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config);
425	if (IS_ERR(regmap)) {
426		dev_err(&client->dev, "failed to initialize regmap\n");
427		return PTR_ERR(regmap);
428	}
429
430	data = iio_priv(indio_dev);
431	i2c_set_clientdata(client, indio_dev);
432	data->dev = &client->dev;
433	data->regmap = regmap;
434
435	ret = mxc4005_chip_init(data);
436	if (ret < 0) {
437		dev_err(&client->dev, "failed to initialize chip\n");
438		return ret;
439	}
440
441	mutex_init(&data->mutex);
442
443	indio_dev->channels = mxc4005_channels;
444	indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels);
445	indio_dev->available_scan_masks = mxc4005_scan_masks;
446	indio_dev->name = MXC4005_DRV_NAME;
447	indio_dev->modes = INDIO_DIRECT_MODE;
448	indio_dev->info = &mxc4005_info;
449
450	ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev,
451					 iio_pollfunc_store_time,
452					 mxc4005_trigger_handler,
453					 NULL);
454	if (ret < 0) {
455		dev_err(&client->dev,
456			"failed to setup iio triggered buffer\n");
457		return ret;
458	}
459
460	if (client->irq > 0) {
461		data->dready_trig = devm_iio_trigger_alloc(&client->dev,
462							   "%s-dev%d",
463							   indio_dev->name,
464							   iio_device_id(indio_dev));
465		if (!data->dready_trig)
466			return -ENOMEM;
467
468		ret = devm_request_threaded_irq(&client->dev, client->irq,
469						iio_trigger_generic_data_rdy_poll,
470						NULL,
471						IRQF_TRIGGER_FALLING |
472						IRQF_ONESHOT,
473						MXC4005_IRQ_NAME,
474						data->dready_trig);
475		if (ret) {
476			dev_err(&client->dev,
477				"failed to init threaded irq\n");
478			return ret;
479		}
480
481		data->dready_trig->ops = &mxc4005_trigger_ops;
482		iio_trigger_set_drvdata(data->dready_trig, indio_dev);
483		ret = devm_iio_trigger_register(&client->dev,
484						data->dready_trig);
485		if (ret) {
486			dev_err(&client->dev,
487				"failed to register trigger\n");
488			return ret;
489		}
490
491		indio_dev->trig = iio_trigger_get(data->dready_trig);
492	}
493
494	return devm_iio_device_register(&client->dev, indio_dev);
495}
496
497static int mxc4005_suspend(struct device *dev)
498{
499	struct iio_dev *indio_dev = dev_get_drvdata(dev);
500	struct mxc4005_data *data = iio_priv(indio_dev);
501	int ret;
502
503	/* Save control to restore it on resume */
504	ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, &data->control);
505	if (ret < 0)
506		dev_err(data->dev, "failed to read reg_control\n");
507
508	return ret;
509}
510
511static int mxc4005_resume(struct device *dev)
512{
513	struct iio_dev *indio_dev = dev_get_drvdata(dev);
514	struct mxc4005_data *data = iio_priv(indio_dev);
515	int ret;
516
517	ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1,
518			   MXC4005_REG_INT_CLR1_SW_RST);
519	if (ret) {
520		dev_err(data->dev, "failed to reset chip: %d\n", ret);
521		return ret;
522	}
523
524	fsleep(MXC4005_RESET_TIME_US);
525
526	ret = regmap_write(data->regmap, MXC4005_REG_CONTROL, data->control);
527	if (ret) {
528		dev_err(data->dev, "failed to restore control register\n");
529		return ret;
530	}
531
532	ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK0, 0);
533	if (ret) {
534		dev_err(data->dev, "failed to restore interrupt 0 mask\n");
535		return ret;
536	}
537
538	ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, data->int_mask1);
539	if (ret) {
540		dev_err(data->dev, "failed to restore interrupt 1 mask\n");
541		return ret;
542	}
543
544	return 0;
545}
546
547static DEFINE_SIMPLE_DEV_PM_OPS(mxc4005_pm_ops, mxc4005_suspend, mxc4005_resume);
548
549static const struct acpi_device_id mxc4005_acpi_match[] = {
550	{"MXC4005",	0},
551	{"MXC6655",	0},
552	{"MDA6655",	0},
553	{ },
554};
555MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match);
556
557static const struct of_device_id mxc4005_of_match[] = {
558	{ .compatible = "memsic,mxc4005", },
559	{ .compatible = "memsic,mxc6655", },
560	{ },
561};
562MODULE_DEVICE_TABLE(of, mxc4005_of_match);
563
564static const struct i2c_device_id mxc4005_id[] = {
565	{"mxc4005",	0},
566	{"mxc6655",	0},
567	{ },
568};
569MODULE_DEVICE_TABLE(i2c, mxc4005_id);
570
571static struct i2c_driver mxc4005_driver = {
572	.driver = {
573		.name = MXC4005_DRV_NAME,
574		.acpi_match_table = mxc4005_acpi_match,
575		.of_match_table = mxc4005_of_match,
576		.pm = pm_sleep_ptr(&mxc4005_pm_ops),
577	},
578	.probe		= mxc4005_probe,
579	.id_table	= mxc4005_id,
580};
581
582module_i2c_driver(mxc4005_driver);
583
584MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>");
585MODULE_LICENSE("GPL v2");
586MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver");
587