1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10*/ 11 12/* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes 68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes 79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes 80 * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes 81 * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes 82 * Birch Stream (SOC) 0x5796 32 hard yes yes yes 83 * 84 * Features supported by this driver: 85 * Software PEC no 86 * Hardware PEC yes 87 * Block buffer yes 88 * Block process call transaction yes 89 * I2C block read transaction yes (doesn't use the block buffer) 90 * Slave mode no 91 * SMBus Host Notify yes 92 * Interrupt processing yes 93 * 94 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 95 */ 96 97#define DRV_NAME "i801_smbus" 98 99#include <linux/interrupt.h> 100#include <linux/module.h> 101#include <linux/pci.h> 102#include <linux/kernel.h> 103#include <linux/stddef.h> 104#include <linux/delay.h> 105#include <linux/ioport.h> 106#include <linux/init.h> 107#include <linux/i2c.h> 108#include <linux/i2c-smbus.h> 109#include <linux/acpi.h> 110#include <linux/io.h> 111#include <linux/dmi.h> 112#include <linux/slab.h> 113#include <linux/string.h> 114#include <linux/completion.h> 115#include <linux/err.h> 116#include <linux/platform_device.h> 117#include <linux/platform_data/itco_wdt.h> 118#include <linux/platform_data/x86/p2sb.h> 119#include <linux/pm_runtime.h> 120#include <linux/mutex.h> 121 122#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 123#include <linux/gpio/machine.h> 124#include <linux/platform_data/i2c-mux-gpio.h> 125#endif 126 127/* I801 SMBus address offsets */ 128#define SMBHSTSTS(p) (0 + (p)->smba) 129#define SMBHSTCNT(p) (2 + (p)->smba) 130#define SMBHSTCMD(p) (3 + (p)->smba) 131#define SMBHSTADD(p) (4 + (p)->smba) 132#define SMBHSTDAT0(p) (5 + (p)->smba) 133#define SMBHSTDAT1(p) (6 + (p)->smba) 134#define SMBBLKDAT(p) (7 + (p)->smba) 135#define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 136#define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 137#define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 138#define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 139#define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 140#define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 141 142/* PCI Address Constants */ 143#define SMBBAR 4 144#define SMBHSTCFG 0x040 145#define TCOBASE 0x050 146#define TCOCTL 0x054 147 148#define SBREG_SMBCTRL 0xc6000c 149#define SBREG_SMBCTRL_DNV 0xcf000c 150 151/* Host configuration bits for SMBHSTCFG */ 152#define SMBHSTCFG_HST_EN BIT(0) 153#define SMBHSTCFG_SMB_SMI_EN BIT(1) 154#define SMBHSTCFG_I2C_EN BIT(2) 155#define SMBHSTCFG_SPD_WD BIT(4) 156 157/* TCO configuration bits for TCOCTL */ 158#define TCOCTL_EN BIT(8) 159 160/* Auxiliary status register bits, ICH4+ only */ 161#define SMBAUXSTS_CRCE BIT(0) 162#define SMBAUXSTS_STCO BIT(1) 163 164/* Auxiliary control register bits, ICH4+ only */ 165#define SMBAUXCTL_CRC BIT(0) 166#define SMBAUXCTL_E32B BIT(1) 167 168/* I801 command constants */ 169#define I801_QUICK 0x00 170#define I801_BYTE 0x04 171#define I801_BYTE_DATA 0x08 172#define I801_WORD_DATA 0x0C 173#define I801_PROC_CALL 0x10 174#define I801_BLOCK_DATA 0x14 175#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 176#define I801_BLOCK_PROC_CALL 0x1C 177 178/* I801 Host Control register bits */ 179#define SMBHSTCNT_INTREN BIT(0) 180#define SMBHSTCNT_KILL BIT(1) 181#define SMBHSTCNT_LAST_BYTE BIT(5) 182#define SMBHSTCNT_START BIT(6) 183#define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 184 185/* I801 Hosts Status register bits */ 186#define SMBHSTSTS_BYTE_DONE BIT(7) 187#define SMBHSTSTS_INUSE_STS BIT(6) 188#define SMBHSTSTS_SMBALERT_STS BIT(5) 189#define SMBHSTSTS_FAILED BIT(4) 190#define SMBHSTSTS_BUS_ERR BIT(3) 191#define SMBHSTSTS_DEV_ERR BIT(2) 192#define SMBHSTSTS_INTR BIT(1) 193#define SMBHSTSTS_HOST_BUSY BIT(0) 194 195/* Host Notify Status register bits */ 196#define SMBSLVSTS_HST_NTFY_STS BIT(0) 197 198/* Host Notify Command register bits */ 199#define SMBSLVCMD_SMBALERT_DISABLE BIT(2) 200#define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 201 202#define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 203 SMBHSTSTS_DEV_ERR) 204 205#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 206 STATUS_ERROR_FLAGS) 207 208#define SMBUS_LEN_SENTINEL (I2C_SMBUS_BLOCK_MAX + 1) 209 210/* Older devices have their ID defined in <linux/pci_ids.h> */ 211#define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 212#define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 213#define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 214#define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 215#define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 216#define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 217#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 218#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 219/* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 220#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 221#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 222#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 223#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 224#define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 225#define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 226#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 227#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 228#define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 229#define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 230#define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3 231#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 232#define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 233#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 234#define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 235#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 236#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 237#define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS 0x5796 238#define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 239#define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23 240#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 241#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22 242#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23 243#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 244#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 245#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 246#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 247#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 248#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 249#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 250#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 251#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 252#define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 253#define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 254#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 255#define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 256#define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 257#define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 258#define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 259#define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 260#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22 261 262struct i801_mux_config { 263 char *gpio_chip; 264 unsigned values[3]; 265 int n_values; 266 unsigned classes[3]; 267 unsigned gpios[2]; /* Relative to gpio_chip->base */ 268 int n_gpios; 269}; 270 271struct i801_priv { 272 struct i2c_adapter adapter; 273 unsigned long smba; 274 unsigned char original_hstcfg; 275 unsigned char original_hstcnt; 276 unsigned char original_slvcmd; 277 struct pci_dev *pci_dev; 278 unsigned int features; 279 280 /* isr processing */ 281 struct completion done; 282 u8 status; 283 284 /* Command state used by isr for byte-by-byte block transactions */ 285 u8 cmd; 286 bool is_read; 287 int count; 288 int len; 289 u8 *data; 290 291#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 292 struct platform_device *mux_pdev; 293 struct gpiod_lookup_table *lookup; 294#endif 295 struct platform_device *tco_pdev; 296 297 /* 298 * If set to true the host controller registers are reserved for 299 * ACPI AML use. 300 */ 301 bool acpi_reserved; 302}; 303 304#define FEATURE_SMBUS_PEC BIT(0) 305#define FEATURE_BLOCK_BUFFER BIT(1) 306#define FEATURE_BLOCK_PROC BIT(2) 307#define FEATURE_I2C_BLOCK_READ BIT(3) 308#define FEATURE_IRQ BIT(4) 309#define FEATURE_HOST_NOTIFY BIT(5) 310/* Not really a feature, but it's convenient to handle it as such */ 311#define FEATURE_IDF BIT(15) 312#define FEATURE_TCO_SPT BIT(16) 313#define FEATURE_TCO_CNL BIT(17) 314 315static const char *i801_feature_names[] = { 316 "SMBus PEC", 317 "Block buffer", 318 "Block process call", 319 "I2C block read", 320 "Interrupt", 321 "SMBus Host Notify", 322}; 323 324static unsigned int disable_features; 325module_param(disable_features, uint, S_IRUGO | S_IWUSR); 326MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 327 "\t\t 0x01 disable SMBus PEC\n" 328 "\t\t 0x02 disable the block buffer\n" 329 "\t\t 0x08 disable the I2C block read functionality\n" 330 "\t\t 0x10 don't use interrupts\n" 331 "\t\t 0x20 disable SMBus Host Notify "); 332 333static int i801_get_block_len(struct i801_priv *priv) 334{ 335 u8 len = inb_p(SMBHSTDAT0(priv)); 336 337 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 338 pci_err(priv->pci_dev, "Illegal SMBus block read size %u\n", len); 339 return -EPROTO; 340 } 341 342 return len; 343} 344 345static int i801_check_and_clear_pec_error(struct i801_priv *priv) 346{ 347 u8 status; 348 349 if (!(priv->features & FEATURE_SMBUS_PEC)) 350 return 0; 351 352 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 353 if (status) { 354 outb_p(status, SMBAUXSTS(priv)); 355 return -EBADMSG; 356 } 357 358 return 0; 359} 360 361/* Make sure the SMBus host is ready to start transmitting. 362 Return 0 if it is, -EBUSY if it is not. */ 363static int i801_check_pre(struct i801_priv *priv) 364{ 365 int status, result; 366 367 status = inb_p(SMBHSTSTS(priv)); 368 if (status & SMBHSTSTS_HOST_BUSY) { 369 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n"); 370 return -EBUSY; 371 } 372 373 status &= STATUS_FLAGS; 374 if (status) { 375 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status); 376 outb_p(status, SMBHSTSTS(priv)); 377 } 378 379 /* 380 * Clear CRC status if needed. 381 * During normal operation, i801_check_post() takes care 382 * of it after every operation. We do it here only in case 383 * the hardware was already in this state when the driver 384 * started. 385 */ 386 result = i801_check_and_clear_pec_error(priv); 387 if (result) 388 pci_dbg(priv->pci_dev, "Clearing aux status flag CRCE\n"); 389 390 return 0; 391} 392 393static int i801_check_post(struct i801_priv *priv, int status) 394{ 395 int result = 0; 396 397 /* 398 * If the SMBus is still busy, we give up 399 */ 400 if (unlikely(status < 0)) { 401 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 402 /* try to stop the current command */ 403 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 404 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 405 usleep_range(1000, 2000); 406 outb_p(0, SMBHSTCNT(priv)); 407 408 /* Check if it worked */ 409 status = inb_p(SMBHSTSTS(priv)); 410 if ((status & SMBHSTSTS_HOST_BUSY) || 411 !(status & SMBHSTSTS_FAILED)) 412 dev_err(&priv->pci_dev->dev, 413 "Failed terminating the transaction\n"); 414 return -ETIMEDOUT; 415 } 416 417 if (status & SMBHSTSTS_FAILED) { 418 result = -EIO; 419 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 420 } 421 if (status & SMBHSTSTS_DEV_ERR) { 422 /* 423 * This may be a PEC error, check and clear it. 424 * 425 * AUXSTS is handled differently from HSTSTS. 426 * For HSTSTS, i801_isr() or i801_wait_intr() 427 * has already cleared the error bits in hardware, 428 * and we are passed a copy of the original value 429 * in "status". 430 * For AUXSTS, the hardware register is left 431 * for us to handle here. 432 * This is asymmetric, slightly iffy, but safe, 433 * since all this code is serialized and the CRCE 434 * bit is harmless as long as it's cleared before 435 * the next operation. 436 */ 437 result = i801_check_and_clear_pec_error(priv); 438 if (result) { 439 pci_dbg(priv->pci_dev, "PEC error\n"); 440 } else { 441 result = -ENXIO; 442 pci_dbg(priv->pci_dev, "No response\n"); 443 } 444 } 445 if (status & SMBHSTSTS_BUS_ERR) { 446 result = -EAGAIN; 447 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 448 } 449 450 return result; 451} 452 453/* Wait for BUSY being cleared and either INTR or an error flag being set */ 454static int i801_wait_intr(struct i801_priv *priv) 455{ 456 unsigned long timeout = jiffies + priv->adapter.timeout; 457 int status, busy; 458 459 do { 460 usleep_range(250, 500); 461 status = inb_p(SMBHSTSTS(priv)); 462 busy = status & SMBHSTSTS_HOST_BUSY; 463 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 464 if (!busy && status) 465 return status & STATUS_ERROR_FLAGS; 466 } while (time_is_after_eq_jiffies(timeout)); 467 468 return -ETIMEDOUT; 469} 470 471/* Wait for either BYTE_DONE or an error flag being set */ 472static int i801_wait_byte_done(struct i801_priv *priv) 473{ 474 unsigned long timeout = jiffies + priv->adapter.timeout; 475 int status; 476 477 do { 478 usleep_range(250, 500); 479 status = inb_p(SMBHSTSTS(priv)); 480 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) 481 return status & STATUS_ERROR_FLAGS; 482 } while (time_is_after_eq_jiffies(timeout)); 483 484 return -ETIMEDOUT; 485} 486 487static int i801_transaction(struct i801_priv *priv, int xact) 488{ 489 unsigned long result; 490 const struct i2c_adapter *adap = &priv->adapter; 491 492 if (priv->features & FEATURE_IRQ) { 493 reinit_completion(&priv->done); 494 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 495 SMBHSTCNT(priv)); 496 result = wait_for_completion_timeout(&priv->done, adap->timeout); 497 return result ? priv->status : -ETIMEDOUT; 498 } 499 500 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 501 502 return i801_wait_intr(priv); 503} 504 505static int i801_block_transaction_by_block(struct i801_priv *priv, 506 union i2c_smbus_data *data, 507 char read_write, int command) 508{ 509 int i, len, status, xact; 510 511 switch (command) { 512 case I2C_SMBUS_BLOCK_PROC_CALL: 513 xact = I801_BLOCK_PROC_CALL; 514 break; 515 case I2C_SMBUS_BLOCK_DATA: 516 xact = I801_BLOCK_DATA; 517 break; 518 default: 519 return -EOPNOTSUPP; 520 } 521 522 /* Set block buffer mode */ 523 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 524 525 if (read_write == I2C_SMBUS_WRITE) { 526 len = data->block[0]; 527 outb_p(len, SMBHSTDAT0(priv)); 528 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 529 for (i = 0; i < len; i++) 530 outb_p(data->block[i+1], SMBBLKDAT(priv)); 531 } 532 533 status = i801_transaction(priv, xact); 534 if (status) 535 goto out; 536 537 if (read_write == I2C_SMBUS_READ || 538 command == I2C_SMBUS_BLOCK_PROC_CALL) { 539 len = i801_get_block_len(priv); 540 if (len < 0) { 541 status = len; 542 goto out; 543 } 544 545 data->block[0] = len; 546 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 547 for (i = 0; i < len; i++) 548 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 549 } 550out: 551 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv)); 552 return status; 553} 554 555static void i801_isr_byte_done(struct i801_priv *priv) 556{ 557 if (priv->is_read) { 558 /* 559 * At transfer start i801_smbus_block_transaction() marks 560 * the block length as invalid. Check for this sentinel value 561 * and read the block length from SMBHSTDAT0. 562 */ 563 if (priv->len == SMBUS_LEN_SENTINEL) { 564 priv->len = i801_get_block_len(priv); 565 if (priv->len < 0) 566 /* FIXME: Recover */ 567 priv->len = I2C_SMBUS_BLOCK_MAX; 568 569 priv->data[-1] = priv->len; 570 } 571 572 /* Read next byte */ 573 if (priv->count < priv->len) 574 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 575 else 576 dev_dbg(&priv->pci_dev->dev, 577 "Discarding extra byte on block read\n"); 578 579 /* Set LAST_BYTE for last byte of read transaction */ 580 if (priv->count == priv->len - 1) 581 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 582 SMBHSTCNT(priv)); 583 } else if (priv->count < priv->len - 1) { 584 /* Write next byte, except for IRQ after last byte */ 585 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 586 } 587} 588 589static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 590{ 591 unsigned short addr; 592 593 addr = inb_p(SMBNTFDADD(priv)) >> 1; 594 595 /* 596 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 597 * always returns 0. Our current implementation doesn't provide 598 * data, so we just ignore it. 599 */ 600 i2c_handle_smbus_host_notify(&priv->adapter, addr); 601 602 /* clear Host Notify bit and return */ 603 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 604 return IRQ_HANDLED; 605} 606 607/* 608 * There are three kinds of interrupts: 609 * 610 * 1) i801 signals transaction completion with one of these interrupts: 611 * INTR - Success 612 * DEV_ERR - Invalid command, NAK or communication timeout 613 * BUS_ERR - SMI# transaction collision 614 * FAILED - transaction was canceled due to a KILL request 615 * When any of these occur, update ->status and signal completion. 616 * 617 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 618 * occurs for each byte of a byte-by-byte to prepare the next byte. 619 * 620 * 3) Host Notify interrupts 621 */ 622static irqreturn_t i801_isr(int irq, void *dev_id) 623{ 624 struct i801_priv *priv = dev_id; 625 u16 pcists; 626 u8 status; 627 628 /* Confirm this is our interrupt */ 629 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 630 if (!(pcists & PCI_STATUS_INTERRUPT)) 631 return IRQ_NONE; 632 633 if (priv->features & FEATURE_HOST_NOTIFY) { 634 status = inb_p(SMBSLVSTS(priv)); 635 if (status & SMBSLVSTS_HST_NTFY_STS) 636 return i801_host_notify_isr(priv); 637 } 638 639 status = inb_p(SMBHSTSTS(priv)); 640 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE) 641 i801_isr_byte_done(priv); 642 643 /* 644 * Clear IRQ sources: SMB_ALERT status is set after signal assertion 645 * independently of the interrupt generation being blocked or not 646 * so clear it always when the status is set. 647 */ 648 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS; 649 outb_p(status, SMBHSTSTS(priv)); 650 651 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 652 if (status) { 653 priv->status = status & STATUS_ERROR_FLAGS; 654 complete(&priv->done); 655 } 656 657 return IRQ_HANDLED; 658} 659 660/* 661 * For "byte-by-byte" block transactions: 662 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 663 * I2C read uses cmd=I801_I2C_BLOCK_DATA 664 */ 665static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 666 union i2c_smbus_data *data, 667 char read_write, int command) 668{ 669 int i, len; 670 int smbcmd; 671 int status; 672 unsigned long result; 673 const struct i2c_adapter *adap = &priv->adapter; 674 675 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 676 return -EOPNOTSUPP; 677 678 len = data->block[0]; 679 680 if (read_write == I2C_SMBUS_WRITE) { 681 outb_p(len, SMBHSTDAT0(priv)); 682 outb_p(data->block[1], SMBBLKDAT(priv)); 683 } 684 685 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 686 read_write == I2C_SMBUS_READ) 687 smbcmd = I801_I2C_BLOCK_DATA; 688 else 689 smbcmd = I801_BLOCK_DATA; 690 691 if (priv->features & FEATURE_IRQ) { 692 priv->is_read = (read_write == I2C_SMBUS_READ); 693 if (len == 1 && priv->is_read) 694 smbcmd |= SMBHSTCNT_LAST_BYTE; 695 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 696 priv->len = len; 697 priv->count = 0; 698 priv->data = &data->block[1]; 699 700 reinit_completion(&priv->done); 701 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 702 result = wait_for_completion_timeout(&priv->done, adap->timeout); 703 return result ? priv->status : -ETIMEDOUT; 704 } 705 706 if (len == 1 && read_write == I2C_SMBUS_READ) 707 smbcmd |= SMBHSTCNT_LAST_BYTE; 708 outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 709 710 for (i = 1; i <= len; i++) { 711 status = i801_wait_byte_done(priv); 712 if (status) 713 return status; 714 715 /* 716 * At transfer start i801_smbus_block_transaction() marks 717 * the block length as invalid. Check for this sentinel value 718 * and read the block length from SMBHSTDAT0. 719 */ 720 if (len == SMBUS_LEN_SENTINEL) { 721 len = i801_get_block_len(priv); 722 if (len < 0) { 723 /* Recover */ 724 while (inb_p(SMBHSTSTS(priv)) & 725 SMBHSTSTS_HOST_BUSY) 726 outb_p(SMBHSTSTS_BYTE_DONE, 727 SMBHSTSTS(priv)); 728 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 729 return -EPROTO; 730 } 731 data->block[0] = len; 732 } 733 734 if (read_write == I2C_SMBUS_READ) { 735 data->block[i] = inb_p(SMBBLKDAT(priv)); 736 if (i == len - 1) 737 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv)); 738 } 739 740 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 741 outb_p(data->block[i+1], SMBBLKDAT(priv)); 742 743 /* signals SMBBLKDAT ready */ 744 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 745 } 746 747 return i801_wait_intr(priv); 748} 749 750static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write) 751{ 752 outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv)); 753} 754 755/* Single value transaction function */ 756static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 757 u8 addr, u8 hstcmd, char read_write, int command) 758{ 759 int xact, ret; 760 761 switch (command) { 762 case I2C_SMBUS_QUICK: 763 i801_set_hstadd(priv, addr, read_write); 764 xact = I801_QUICK; 765 break; 766 case I2C_SMBUS_BYTE: 767 i801_set_hstadd(priv, addr, read_write); 768 if (read_write == I2C_SMBUS_WRITE) 769 outb_p(hstcmd, SMBHSTCMD(priv)); 770 xact = I801_BYTE; 771 break; 772 case I2C_SMBUS_BYTE_DATA: 773 i801_set_hstadd(priv, addr, read_write); 774 if (read_write == I2C_SMBUS_WRITE) 775 outb_p(data->byte, SMBHSTDAT0(priv)); 776 outb_p(hstcmd, SMBHSTCMD(priv)); 777 xact = I801_BYTE_DATA; 778 break; 779 case I2C_SMBUS_WORD_DATA: 780 i801_set_hstadd(priv, addr, read_write); 781 if (read_write == I2C_SMBUS_WRITE) { 782 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 783 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 784 } 785 outb_p(hstcmd, SMBHSTCMD(priv)); 786 xact = I801_WORD_DATA; 787 break; 788 case I2C_SMBUS_PROC_CALL: 789 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 790 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 791 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 792 outb_p(hstcmd, SMBHSTCMD(priv)); 793 read_write = I2C_SMBUS_READ; 794 xact = I801_PROC_CALL; 795 break; 796 default: 797 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command); 798 return -EOPNOTSUPP; 799 } 800 801 ret = i801_transaction(priv, xact); 802 if (ret || read_write == I2C_SMBUS_WRITE) 803 return ret; 804 805 switch (command) { 806 case I2C_SMBUS_BYTE: 807 case I2C_SMBUS_BYTE_DATA: 808 data->byte = inb_p(SMBHSTDAT0(priv)); 809 break; 810 case I2C_SMBUS_WORD_DATA: 811 case I2C_SMBUS_PROC_CALL: 812 data->word = inb_p(SMBHSTDAT0(priv)) + 813 (inb_p(SMBHSTDAT1(priv)) << 8); 814 break; 815 } 816 817 return 0; 818} 819 820static int i801_smbus_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 821 u8 addr, u8 hstcmd, char read_write, int command) 822{ 823 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA) 824 /* Mark block length as invalid */ 825 data->block[0] = SMBUS_LEN_SENTINEL; 826 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 827 return -EPROTO; 828 829 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 830 /* Needs to be flagged as write transaction */ 831 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 832 else 833 i801_set_hstadd(priv, addr, read_write); 834 outb_p(hstcmd, SMBHSTCMD(priv)); 835 836 if (priv->features & FEATURE_BLOCK_BUFFER) 837 return i801_block_transaction_by_block(priv, data, read_write, command); 838 else 839 return i801_block_transaction_byte_by_byte(priv, data, read_write, command); 840} 841 842static int i801_i2c_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 843 u8 addr, u8 hstcmd, char read_write, int command) 844{ 845 int result; 846 u8 hostc; 847 848 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 849 return -EPROTO; 850 /* 851 * NB: page 240 of ICH5 datasheet shows that the R/#W bit should be cleared here, 852 * even when reading. However if SPD Write Disable is set (Lynx Point and later), 853 * the read will fail if we don't set the R/#W bit. 854 */ 855 i801_set_hstadd(priv, addr, 856 priv->original_hstcfg & SMBHSTCFG_SPD_WD ? read_write : I2C_SMBUS_WRITE); 857 858 /* NB: page 240 of ICH5 datasheet shows that DATA1 is the cmd field when reading */ 859 if (read_write == I2C_SMBUS_READ) 860 outb_p(hstcmd, SMBHSTDAT1(priv)); 861 else 862 outb_p(hstcmd, SMBHSTCMD(priv)); 863 864 if (read_write == I2C_SMBUS_WRITE) { 865 /* set I2C_EN bit in configuration register */ 866 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 867 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc | SMBHSTCFG_I2C_EN); 868 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 869 pci_err(priv->pci_dev, "I2C block read is unsupported!\n"); 870 return -EOPNOTSUPP; 871 } 872 873 /* Block buffer isn't supported for I2C block transactions */ 874 result = i801_block_transaction_byte_by_byte(priv, data, read_write, command); 875 876 /* restore saved configuration register value */ 877 if (read_write == I2C_SMBUS_WRITE) 878 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 879 880 return result; 881} 882 883/* Return negative errno on error. */ 884static s32 i801_access(struct i2c_adapter *adap, u16 addr, 885 unsigned short flags, char read_write, u8 command, 886 int size, union i2c_smbus_data *data) 887{ 888 int hwpec, ret; 889 struct i801_priv *priv = i2c_get_adapdata(adap); 890 891 if (priv->acpi_reserved) 892 return -EBUSY; 893 894 pm_runtime_get_sync(&priv->pci_dev->dev); 895 896 ret = i801_check_pre(priv); 897 if (ret) 898 goto out; 899 900 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 901 && size != I2C_SMBUS_QUICK 902 && size != I2C_SMBUS_I2C_BLOCK_DATA; 903 904 if (hwpec) /* enable/disable hardware PEC */ 905 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 906 else 907 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 908 SMBAUXCTL(priv)); 909 910 if (size == I2C_SMBUS_BLOCK_DATA || size == I2C_SMBUS_BLOCK_PROC_CALL) 911 ret = i801_smbus_block_transaction(priv, data, addr, command, read_write, size); 912 else if (size == I2C_SMBUS_I2C_BLOCK_DATA) 913 ret = i801_i2c_block_transaction(priv, data, addr, command, read_write, size); 914 else 915 ret = i801_simple_transaction(priv, data, addr, command, read_write, size); 916 917 ret = i801_check_post(priv, ret); 918 919 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 920 * time, so we forcibly disable it after every transaction. 921 */ 922 if (hwpec) 923 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv)); 924out: 925 /* 926 * Unlock the SMBus device for use by BIOS/ACPI, 927 * and clear status flags if not done already. 928 */ 929 outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv)); 930 931 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 932 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 933 return ret; 934} 935 936 937static u32 i801_func(struct i2c_adapter *adapter) 938{ 939 struct i801_priv *priv = i2c_get_adapdata(adapter); 940 941 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 942 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 943 I2C_FUNC_SMBUS_PROC_CALL | 944 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 945 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 946 ((priv->features & FEATURE_BLOCK_PROC) ? 947 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 948 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 949 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 950 ((priv->features & FEATURE_HOST_NOTIFY) ? 951 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 952} 953 954static void i801_enable_host_notify(struct i2c_adapter *adapter) 955{ 956 struct i801_priv *priv = i2c_get_adapdata(adapter); 957 958 if (!(priv->features & FEATURE_HOST_NOTIFY)) 959 return; 960 961 /* 962 * Enable host notify interrupt and block the generation of interrupt 963 * from the SMB_ALERT signal because the driver does not support 964 * SMBus Alert. 965 */ 966 outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE | 967 priv->original_slvcmd, SMBSLVCMD(priv)); 968 969 /* clear Host Notify bit to allow a new notification */ 970 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 971} 972 973static void i801_disable_host_notify(struct i801_priv *priv) 974{ 975 if (!(priv->features & FEATURE_HOST_NOTIFY)) 976 return; 977 978 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 979} 980 981static const struct i2c_algorithm smbus_algorithm = { 982 .smbus_xfer = i801_access, 983 .functionality = i801_func, 984}; 985 986#define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \ 987 FEATURE_HOST_NOTIFY) 988#define FEATURES_ICH5 (FEATURES_ICH4 | FEATURE_BLOCK_PROC | \ 989 FEATURE_I2C_BLOCK_READ | FEATURE_IRQ) 990 991static const struct pci_device_id i801_ids[] = { 992 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) }, 993 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) }, 994 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) }, 995 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) }, 996 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) }, 997 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) }, 998 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) }, 999 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) }, 1000 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) }, 1001 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) }, 1002 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) }, 1003 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) }, 1004 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) }, 1005 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) }, 1006 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) }, 1007 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) }, 1008 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) }, 1009 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) }, 1010 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) }, 1011 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) }, 1012 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) }, 1013 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) }, 1014 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) }, 1015 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) }, 1016 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) }, 1017 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) }, 1018 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) }, 1019 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) }, 1020 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) }, 1021 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) }, 1022 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) }, 1023 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) }, 1024 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) }, 1025 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) }, 1026 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) }, 1027 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) }, 1028 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1029 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1030 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1031 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1032 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1033 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) }, 1034 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1035 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1036 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1037 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1038 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1039 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1040 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1041 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1042 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1043 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1044 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1045 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1046 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1047 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1048 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1049 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1050 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1051 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1052 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1053 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1054 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1055 { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1056 { 0, } 1057}; 1058 1059MODULE_DEVICE_TABLE(pci, i801_ids); 1060 1061#if defined CONFIG_X86 && defined CONFIG_DMI 1062static unsigned char apanel_addr; 1063 1064/* Scan the system ROM for the signature "FJKEYINF" */ 1065static __init const void __iomem *bios_signature(const void __iomem *bios) 1066{ 1067 ssize_t offset; 1068 const unsigned char signature[] = "FJKEYINF"; 1069 1070 for (offset = 0; offset < 0x10000; offset += 0x10) { 1071 if (check_signature(bios + offset, signature, 1072 sizeof(signature)-1)) 1073 return bios + offset; 1074 } 1075 return NULL; 1076} 1077 1078static void __init input_apanel_init(void) 1079{ 1080 void __iomem *bios; 1081 const void __iomem *p; 1082 1083 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1084 p = bios_signature(bios); 1085 if (p) { 1086 /* just use the first address */ 1087 apanel_addr = readb(p + 8 + 3) >> 1; 1088 } 1089 iounmap(bios); 1090} 1091 1092struct dmi_onboard_device_info { 1093 const char *name; 1094 u8 type; 1095 unsigned short i2c_addr; 1096 const char *i2c_type; 1097}; 1098 1099static const struct dmi_onboard_device_info dmi_devices[] = { 1100 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1101 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1102 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1103}; 1104 1105static void dmi_check_onboard_device(u8 type, const char *name, 1106 struct i2c_adapter *adap) 1107{ 1108 int i; 1109 struct i2c_board_info info; 1110 1111 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1112 /* & ~0x80, ignore enabled/disabled bit */ 1113 if ((type & ~0x80) != dmi_devices[i].type) 1114 continue; 1115 if (strcasecmp(name, dmi_devices[i].name)) 1116 continue; 1117 1118 memset(&info, 0, sizeof(struct i2c_board_info)); 1119 info.addr = dmi_devices[i].i2c_addr; 1120 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1121 i2c_new_client_device(adap, &info); 1122 break; 1123 } 1124} 1125 1126/* We use our own function to check for onboard devices instead of 1127 dmi_find_device() as some buggy BIOS's have the devices we are interested 1128 in marked as disabled */ 1129static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1130{ 1131 int i, count; 1132 1133 if (dm->type != DMI_ENTRY_ONBOARD_DEVICE) 1134 return; 1135 1136 count = (dm->length - sizeof(struct dmi_header)) / 2; 1137 for (i = 0; i < count; i++) { 1138 const u8 *d = (char *)(dm + 1) + (i * 2); 1139 const char *name = ((char *) dm) + dm->length; 1140 u8 type = d[0]; 1141 u8 s = d[1]; 1142 1143 if (!s) 1144 continue; 1145 s--; 1146 while (s > 0 && name[0]) { 1147 name += strlen(name) + 1; 1148 s--; 1149 } 1150 if (name[0] == 0) /* Bogus string reference */ 1151 continue; 1152 1153 dmi_check_onboard_device(type, name, adap); 1154 } 1155} 1156 1157/* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1158static const char *const acpi_smo8800_ids[] = { 1159 "SMO8800", 1160 "SMO8801", 1161 "SMO8810", 1162 "SMO8811", 1163 "SMO8820", 1164 "SMO8821", 1165 "SMO8830", 1166 "SMO8831", 1167}; 1168 1169static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1170 u32 nesting_level, 1171 void *context, 1172 void **return_value) 1173{ 1174 struct acpi_device_info *info; 1175 acpi_status status; 1176 char *hid; 1177 int i; 1178 1179 status = acpi_get_object_info(obj_handle, &info); 1180 if (ACPI_FAILURE(status)) 1181 return AE_OK; 1182 1183 if (!(info->valid & ACPI_VALID_HID)) 1184 goto smo88xx_not_found; 1185 1186 hid = info->hardware_id.string; 1187 if (!hid) 1188 goto smo88xx_not_found; 1189 1190 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1191 if (i < 0) 1192 goto smo88xx_not_found; 1193 1194 kfree(info); 1195 1196 *return_value = NULL; 1197 return AE_CTRL_TERMINATE; 1198 1199smo88xx_not_found: 1200 kfree(info); 1201 return AE_OK; 1202} 1203 1204static bool is_dell_system_with_lis3lv02d(void) 1205{ 1206 void *err = ERR_PTR(-ENOENT); 1207 1208 if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc.")) 1209 return false; 1210 1211 /* 1212 * Check that ACPI device SMO88xx is present and is functioning. 1213 * Function acpi_get_devices() already filters all ACPI devices 1214 * which are not present or are not functioning. 1215 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1216 * accelerometer but unfortunately ACPI does not provide any other 1217 * information (like I2C address). 1218 */ 1219 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err); 1220 1221 return !IS_ERR(err); 1222} 1223 1224/* 1225 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1226 * so it is needed to define mapping table based on DMI product names. 1227 */ 1228static const struct { 1229 const char *dmi_product_name; 1230 unsigned short i2c_addr; 1231} dell_lis3lv02d_devices[] = { 1232 /* 1233 * Dell platform team told us that these Latitude devices have 1234 * ST microelectronics accelerometer at I2C address 0x29. 1235 */ 1236 { "Latitude E5250", 0x29 }, 1237 { "Latitude E5450", 0x29 }, 1238 { "Latitude E5550", 0x29 }, 1239 { "Latitude E6440", 0x29 }, 1240 { "Latitude E6440 ATG", 0x29 }, 1241 { "Latitude E6540", 0x29 }, 1242 /* 1243 * Additional individual entries were added after verification. 1244 */ 1245 { "Latitude 5480", 0x29 }, 1246 { "Precision 3540", 0x29 }, 1247 { "Vostro V131", 0x1d }, 1248 { "Vostro 5568", 0x29 }, 1249 { "XPS 15 7590", 0x29 }, 1250}; 1251 1252static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1253{ 1254 struct i2c_board_info info; 1255 const char *dmi_product_name; 1256 int i; 1257 1258 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1259 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1260 if (strcmp(dmi_product_name, 1261 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1262 break; 1263 } 1264 1265 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1266 dev_warn(&priv->pci_dev->dev, 1267 "Accelerometer lis3lv02d is present on SMBus but its" 1268 " address is unknown, skipping registration\n"); 1269 return; 1270 } 1271 1272 memset(&info, 0, sizeof(struct i2c_board_info)); 1273 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1274 strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1275 i2c_new_client_device(&priv->adapter, &info); 1276} 1277 1278/* Register optional slaves */ 1279static void i801_probe_optional_slaves(struct i801_priv *priv) 1280{ 1281 /* Only register slaves on main SMBus channel */ 1282 if (priv->features & FEATURE_IDF) 1283 return; 1284 1285 if (apanel_addr) { 1286 struct i2c_board_info info = { 1287 .addr = apanel_addr, 1288 .type = "fujitsu_apanel", 1289 }; 1290 1291 i2c_new_client_device(&priv->adapter, &info); 1292 } 1293 1294 if (dmi_name_in_vendors("FUJITSU")) 1295 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1296 1297 if (is_dell_system_with_lis3lv02d()) 1298 register_dell_lis3lv02d_i2c_device(priv); 1299 1300 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1301#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) 1302 if (!priv->mux_pdev) 1303#endif 1304 i2c_register_spd(&priv->adapter); 1305} 1306#else 1307static void __init input_apanel_init(void) {} 1308static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1309#endif /* CONFIG_X86 && CONFIG_DMI */ 1310 1311#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1312static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1313 .gpio_chip = "gpio_ich", 1314 .values = { 0x02, 0x03 }, 1315 .n_values = 2, 1316 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1317 .gpios = { 52, 53 }, 1318 .n_gpios = 2, 1319}; 1320 1321static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1322 .gpio_chip = "gpio_ich", 1323 .values = { 0x02, 0x03, 0x01 }, 1324 .n_values = 3, 1325 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1326 .gpios = { 52, 53 }, 1327 .n_gpios = 2, 1328}; 1329 1330static const struct dmi_system_id mux_dmi_table[] = { 1331 { 1332 .matches = { 1333 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1334 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1335 }, 1336 .driver_data = &i801_mux_config_asus_z8_d12, 1337 }, 1338 { 1339 .matches = { 1340 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1341 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1342 }, 1343 .driver_data = &i801_mux_config_asus_z8_d12, 1344 }, 1345 { 1346 .matches = { 1347 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1348 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1349 }, 1350 .driver_data = &i801_mux_config_asus_z8_d12, 1351 }, 1352 { 1353 .matches = { 1354 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1355 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1356 }, 1357 .driver_data = &i801_mux_config_asus_z8_d12, 1358 }, 1359 { 1360 .matches = { 1361 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1362 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1363 }, 1364 .driver_data = &i801_mux_config_asus_z8_d12, 1365 }, 1366 { 1367 .matches = { 1368 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1369 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1370 }, 1371 .driver_data = &i801_mux_config_asus_z8_d12, 1372 }, 1373 { 1374 .matches = { 1375 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1376 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1377 }, 1378 .driver_data = &i801_mux_config_asus_z8_d18, 1379 }, 1380 { 1381 .matches = { 1382 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1383 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1384 }, 1385 .driver_data = &i801_mux_config_asus_z8_d18, 1386 }, 1387 { 1388 .matches = { 1389 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1390 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1391 }, 1392 .driver_data = &i801_mux_config_asus_z8_d12, 1393 }, 1394 { } 1395}; 1396 1397/* Setup multiplexing if needed */ 1398static void i801_add_mux(struct i801_priv *priv) 1399{ 1400 struct device *dev = &priv->adapter.dev; 1401 const struct i801_mux_config *mux_config; 1402 struct i2c_mux_gpio_platform_data gpio_data; 1403 struct gpiod_lookup_table *lookup; 1404 const struct dmi_system_id *id; 1405 int i; 1406 1407 id = dmi_first_match(mux_dmi_table); 1408 if (!id) 1409 return; 1410 1411 mux_config = id->driver_data; 1412 1413 /* Prepare the platform data */ 1414 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1415 gpio_data.parent = priv->adapter.nr; 1416 gpio_data.values = mux_config->values; 1417 gpio_data.n_values = mux_config->n_values; 1418 gpio_data.classes = mux_config->classes; 1419 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1420 1421 /* Register GPIO descriptor lookup table */ 1422 lookup = devm_kzalloc(dev, 1423 struct_size(lookup, table, mux_config->n_gpios + 1), 1424 GFP_KERNEL); 1425 if (!lookup) 1426 return; 1427 lookup->dev_id = "i2c-mux-gpio"; 1428 for (i = 0; i < mux_config->n_gpios; i++) 1429 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip, 1430 mux_config->gpios[i], "mux", 0); 1431 gpiod_add_lookup_table(lookup); 1432 1433 /* 1434 * Register the mux device, we use PLATFORM_DEVID_NONE here 1435 * because since we are referring to the GPIO chip by name we are 1436 * anyways in deep trouble if there is more than one of these 1437 * devices, and there should likely only be one platform controller 1438 * hub. 1439 */ 1440 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1441 PLATFORM_DEVID_NONE, &gpio_data, 1442 sizeof(struct i2c_mux_gpio_platform_data)); 1443 if (IS_ERR(priv->mux_pdev)) { 1444 gpiod_remove_lookup_table(lookup); 1445 devm_kfree(dev, lookup); 1446 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1447 } else { 1448 priv->lookup = lookup; 1449 } 1450} 1451 1452static void i801_del_mux(struct i801_priv *priv) 1453{ 1454 platform_device_unregister(priv->mux_pdev); 1455 gpiod_remove_lookup_table(priv->lookup); 1456} 1457#else 1458static inline void i801_add_mux(struct i801_priv *priv) { } 1459static inline void i801_del_mux(struct i801_priv *priv) { } 1460#endif 1461 1462static struct platform_device * 1463i801_add_tco_spt(struct pci_dev *pci_dev, struct resource *tco_res) 1464{ 1465 static const struct itco_wdt_platform_data pldata = { 1466 .name = "Intel PCH", 1467 .version = 4, 1468 }; 1469 struct resource *res; 1470 int ret; 1471 1472 /* 1473 * We must access the NO_REBOOT bit over the Primary to Sideband 1474 * (P2SB) bridge. 1475 */ 1476 1477 res = &tco_res[1]; 1478 ret = p2sb_bar(pci_dev->bus, 0, res); 1479 if (ret) 1480 return ERR_PTR(ret); 1481 1482 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1483 res->start += SBREG_SMBCTRL_DNV; 1484 else 1485 res->start += SBREG_SMBCTRL; 1486 1487 res->end = res->start + 3; 1488 1489 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1490 tco_res, 2, &pldata, sizeof(pldata)); 1491} 1492 1493static struct platform_device * 1494i801_add_tco_cnl(struct pci_dev *pci_dev, struct resource *tco_res) 1495{ 1496 static const struct itco_wdt_platform_data pldata = { 1497 .name = "Intel PCH", 1498 .version = 6, 1499 }; 1500 1501 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1502 tco_res, 1, &pldata, sizeof(pldata)); 1503} 1504 1505static void i801_add_tco(struct i801_priv *priv) 1506{ 1507 struct pci_dev *pci_dev = priv->pci_dev; 1508 struct resource tco_res[2], *res; 1509 u32 tco_base, tco_ctl; 1510 1511 /* If we have ACPI based watchdog use that instead */ 1512 if (acpi_has_watchdog()) 1513 return; 1514 1515 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1516 return; 1517 1518 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1519 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1520 if (!(tco_ctl & TCOCTL_EN)) 1521 return; 1522 1523 memset(tco_res, 0, sizeof(tco_res)); 1524 /* 1525 * Always populate the main iTCO IO resource here. The second entry 1526 * for NO_REBOOT MMIO is filled by the SPT specific function. 1527 */ 1528 res = &tco_res[0]; 1529 res->start = tco_base & ~1; 1530 res->end = res->start + 32 - 1; 1531 res->flags = IORESOURCE_IO; 1532 1533 if (priv->features & FEATURE_TCO_CNL) 1534 priv->tco_pdev = i801_add_tco_cnl(pci_dev, tco_res); 1535 else 1536 priv->tco_pdev = i801_add_tco_spt(pci_dev, tco_res); 1537 1538 if (IS_ERR(priv->tco_pdev)) 1539 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1540} 1541 1542#ifdef CONFIG_ACPI 1543static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1544 acpi_physical_address address) 1545{ 1546 return address >= priv->smba && 1547 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1548} 1549 1550static acpi_status 1551i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1552 u64 *value, void *handler_context, void *region_context) 1553{ 1554 struct i801_priv *priv = handler_context; 1555 struct pci_dev *pdev = priv->pci_dev; 1556 acpi_status status; 1557 1558 /* 1559 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1560 * further access from the driver itself. This device is now owned 1561 * by the system firmware. 1562 */ 1563 i2c_lock_bus(&priv->adapter, I2C_LOCK_SEGMENT); 1564 1565 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1566 priv->acpi_reserved = true; 1567 1568 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1569 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1570 1571 /* 1572 * BIOS is accessing the host controller so prevent it from 1573 * suspending automatically from now on. 1574 */ 1575 pm_runtime_get_sync(&pdev->dev); 1576 } 1577 1578 if ((function & ACPI_IO_MASK) == ACPI_READ) 1579 status = acpi_os_read_port(address, (u32 *)value, bits); 1580 else 1581 status = acpi_os_write_port(address, (u32)*value, bits); 1582 1583 i2c_unlock_bus(&priv->adapter, I2C_LOCK_SEGMENT); 1584 1585 return status; 1586} 1587 1588static int i801_acpi_probe(struct i801_priv *priv) 1589{ 1590 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1591 acpi_status status; 1592 1593 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, 1594 i801_acpi_io_handler, NULL, priv); 1595 if (ACPI_SUCCESS(status)) 1596 return 0; 1597 1598 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1599} 1600 1601static void i801_acpi_remove(struct i801_priv *priv) 1602{ 1603 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1604 1605 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1606} 1607#else 1608static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1609static inline void i801_acpi_remove(struct i801_priv *priv) { } 1610#endif 1611 1612static void i801_setup_hstcfg(struct i801_priv *priv) 1613{ 1614 unsigned char hstcfg = priv->original_hstcfg; 1615 1616 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1617 hstcfg |= SMBHSTCFG_HST_EN; 1618 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1619} 1620 1621static void i801_restore_regs(struct i801_priv *priv) 1622{ 1623 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1624 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1625} 1626 1627static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1628{ 1629 int err, i; 1630 struct i801_priv *priv; 1631 1632 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1633 if (!priv) 1634 return -ENOMEM; 1635 1636 i2c_set_adapdata(&priv->adapter, priv); 1637 priv->adapter.owner = THIS_MODULE; 1638 priv->adapter.class = I2C_CLASS_HWMON; 1639 priv->adapter.algo = &smbus_algorithm; 1640 priv->adapter.dev.parent = &dev->dev; 1641 acpi_use_parent_companion(&priv->adapter.dev); 1642 priv->adapter.retries = 3; 1643 1644 priv->pci_dev = dev; 1645 priv->features = id->driver_data; 1646 1647 /* Disable features on user request */ 1648 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1649 if (priv->features & disable_features & (1 << i)) 1650 dev_notice(&dev->dev, "%s disabled by user\n", 1651 i801_feature_names[i]); 1652 } 1653 priv->features &= ~disable_features; 1654 1655 /* The block process call uses block buffer mode */ 1656 if (!(priv->features & FEATURE_BLOCK_BUFFER)) 1657 priv->features &= ~FEATURE_BLOCK_PROC; 1658 1659 err = pcim_enable_device(dev); 1660 if (err) { 1661 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1662 err); 1663 return err; 1664 } 1665 pcim_pin_device(dev); 1666 1667 /* Determine the address of the SMBus area */ 1668 priv->smba = pci_resource_start(dev, SMBBAR); 1669 if (!priv->smba) { 1670 dev_err(&dev->dev, 1671 "SMBus base address uninitialized, upgrade BIOS\n"); 1672 return -ENODEV; 1673 } 1674 1675 if (i801_acpi_probe(priv)) 1676 return -ENODEV; 1677 1678 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME); 1679 if (err) { 1680 dev_err(&dev->dev, 1681 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1682 priv->smba, 1683 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1684 i801_acpi_remove(priv); 1685 return err; 1686 } 1687 1688 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); 1689 i801_setup_hstcfg(priv); 1690 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1691 dev_info(&dev->dev, "Enabling SMBus device\n"); 1692 1693 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) { 1694 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1695 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1696 priv->features &= ~FEATURE_IRQ; 1697 } 1698 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) 1699 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1700 1701 /* Clear special mode bits */ 1702 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1703 outb_p(inb_p(SMBAUXCTL(priv)) & 1704 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1705 1706 /* Default timeout in interrupt mode: 200 ms */ 1707 priv->adapter.timeout = HZ / 5; 1708 1709 if (dev->irq == IRQ_NOTCONNECTED) 1710 priv->features &= ~FEATURE_IRQ; 1711 1712 if (priv->features & FEATURE_IRQ) { 1713 u16 pcists; 1714 1715 /* Complain if an interrupt is already pending */ 1716 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 1717 if (pcists & PCI_STATUS_INTERRUPT) 1718 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1719 } 1720 1721 if (priv->features & FEATURE_IRQ) { 1722 init_completion(&priv->done); 1723 1724 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1725 IRQF_SHARED, DRV_NAME, priv); 1726 if (err) { 1727 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1728 dev->irq, err); 1729 priv->features &= ~FEATURE_IRQ; 1730 } 1731 } 1732 dev_info(&dev->dev, "SMBus using %s\n", 1733 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1734 1735 /* Host notification uses an interrupt */ 1736 if (!(priv->features & FEATURE_IRQ)) 1737 priv->features &= ~FEATURE_HOST_NOTIFY; 1738 1739 /* Remember original Interrupt and Host Notify settings */ 1740 priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL; 1741 if (priv->features & FEATURE_HOST_NOTIFY) 1742 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1743 1744 i801_add_tco(priv); 1745 1746 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1747 "SMBus I801 adapter at %04lx", priv->smba); 1748 err = i2c_add_adapter(&priv->adapter); 1749 if (err) { 1750 platform_device_unregister(priv->tco_pdev); 1751 i801_acpi_remove(priv); 1752 i801_restore_regs(priv); 1753 return err; 1754 } 1755 1756 i801_enable_host_notify(&priv->adapter); 1757 1758 /* We ignore errors - multiplexing is optional */ 1759 i801_add_mux(priv); 1760 i801_probe_optional_slaves(priv); 1761 1762 pci_set_drvdata(dev, priv); 1763 1764 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1765 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1766 pm_runtime_use_autosuspend(&dev->dev); 1767 pm_runtime_put_autosuspend(&dev->dev); 1768 pm_runtime_allow(&dev->dev); 1769 1770 return 0; 1771} 1772 1773static void i801_remove(struct pci_dev *dev) 1774{ 1775 struct i801_priv *priv = pci_get_drvdata(dev); 1776 1777 i801_disable_host_notify(priv); 1778 i801_del_mux(priv); 1779 i2c_del_adapter(&priv->adapter); 1780 i801_acpi_remove(priv); 1781 1782 platform_device_unregister(priv->tco_pdev); 1783 1784 /* if acpi_reserved is set then usage_count is incremented already */ 1785 if (!priv->acpi_reserved) 1786 pm_runtime_get_noresume(&dev->dev); 1787 1788 i801_restore_regs(priv); 1789 1790 /* 1791 * do not call pci_disable_device(dev) since it can cause hard hangs on 1792 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1793 */ 1794} 1795 1796static void i801_shutdown(struct pci_dev *dev) 1797{ 1798 struct i801_priv *priv = pci_get_drvdata(dev); 1799 1800 i801_disable_host_notify(priv); 1801 /* Restore config registers to avoid hard hang on some systems */ 1802 i801_restore_regs(priv); 1803} 1804 1805static int i801_suspend(struct device *dev) 1806{ 1807 struct i801_priv *priv = dev_get_drvdata(dev); 1808 1809 i2c_mark_adapter_suspended(&priv->adapter); 1810 i801_restore_regs(priv); 1811 1812 return 0; 1813} 1814 1815static int i801_resume(struct device *dev) 1816{ 1817 struct i801_priv *priv = dev_get_drvdata(dev); 1818 1819 i801_setup_hstcfg(priv); 1820 i801_enable_host_notify(&priv->adapter); 1821 i2c_mark_adapter_resumed(&priv->adapter); 1822 1823 return 0; 1824} 1825 1826static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1827 1828static struct pci_driver i801_driver = { 1829 .name = DRV_NAME, 1830 .id_table = i801_ids, 1831 .probe = i801_probe, 1832 .remove = i801_remove, 1833 .shutdown = i801_shutdown, 1834 .driver = { 1835 .pm = pm_sleep_ptr(&i801_pm_ops), 1836 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1837 }, 1838}; 1839 1840static int __init i2c_i801_init(struct pci_driver *drv) 1841{ 1842 if (dmi_name_in_vendors("FUJITSU")) 1843 input_apanel_init(); 1844 return pci_register_driver(drv); 1845} 1846 1847MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 1848MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 1849MODULE_DESCRIPTION("I801 SMBus driver"); 1850MODULE_LICENSE("GPL"); 1851 1852module_driver(i801_driver, i2c_i801_init, pci_unregister_driver); 1853