1262395Sbapt/* SPDX-License-Identifier: GPL-2.0-or-later */ 2262395Sbapt/* 3262395Sbapt * AMD MP2 PCIe communication driver 4262395Sbapt * Copyright 2020-2021 Advanced Micro Devices, Inc. 5262395Sbapt * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 6262395Sbapt * Sandeep Singh <Sandeep.singh@amd.com> 7262395Sbapt * Basavaraj Natikar <Basavaraj.Natikar@amd.com> 8262395Sbapt */ 9262395Sbapt 10262395Sbapt#ifndef PCIE_MP2_AMD_H 11262395Sbapt#define PCIE_MP2_AMD_H 12262395Sbapt 13262395Sbapt#include "amd_sfh_common.h" 14262395Sbapt 15262395Sbapt/* MP2 C2P Message Registers */ 16262395Sbapt#define AMD_C2P_MSG0 0x10500 17262395Sbapt#define AMD_C2P_MSG1 0x10504 18262395Sbapt#define AMD_C2P_MSG2 0x10508 19262395Sbapt 20262395Sbapt/* MP2 P2C Message Registers */ 21262395Sbapt#define AMD_P2C_MSG3 0x1068C /* Supported Sensors info */ 22262395Sbapt 23262395Sbapt#define V2_STATUS 0x2 24262395Sbapt 25262395Sbapt#define HPD_IDX 16 26262395Sbapt#define ACS_IDX 22 27262395Sbapt 28262395Sbapt#define SENSOR_DISCOVERY_STATUS_MASK GENMASK(5, 3) 29262395Sbapt#define SENSOR_DISCOVERY_STATUS_SHIFT 3 30262395Sbapt 31262395Sbapt/* SFH Command register */ 32262395Sbaptunion sfh_cmd_base { 33262395Sbapt u32 ul; 34262395Sbapt struct { 35262395Sbapt u32 cmd_id : 8; 36262395Sbapt u32 sensor_id : 8; 37262395Sbapt u32 period : 16; 38262395Sbapt } s; 39262395Sbapt struct { 40262395Sbapt u32 cmd_id : 4; 41262395Sbapt u32 intr_disable : 1; 42262395Sbapt u32 rsvd1 : 3; 43262395Sbapt u32 length : 7; 44262395Sbapt u32 mem_type : 1; 45262395Sbapt u32 sensor_id : 8; 46262395Sbapt u32 period : 8; 47262395Sbapt } cmd_v2; 48262395Sbapt}; 49262395Sbapt 50262395Sbaptunion cmd_response { 51262395Sbapt u32 resp; 52262395Sbapt struct { 53262395Sbapt u32 status : 2; 54262395Sbapt u32 out_in_c2p : 1; 55262395Sbapt u32 rsvd1 : 1; 56262395Sbapt u32 response : 4; 57262395Sbapt u32 sub_cmd : 8; 58262395Sbapt u32 sensor_id : 6; 59262395Sbapt u32 rsvd2 : 10; 60262395Sbapt } response_v2; 61262395Sbapt}; 62262395Sbapt 63262395Sbaptunion sfh_cmd_param { 64262395Sbapt u32 ul; 65262395Sbapt struct { 66262395Sbapt u32 buf_layout : 2; 67262395Sbapt u32 buf_length : 6; 68262395Sbapt u32 rsvd : 24; 69262395Sbapt } s; 70262395Sbapt}; 71262395Sbapt 72262395Sbaptstruct sfh_cmd_reg { 73262395Sbapt union sfh_cmd_base cmd_base; 74262395Sbapt union sfh_cmd_param cmd_param; 75262395Sbapt phys_addr_t phys_addr; 76262395Sbapt}; 77262395Sbapt 78262395Sbaptenum sensor_idx { 79262395Sbapt accel_idx = 0, 80262395Sbapt gyro_idx = 1, 81262395Sbapt mag_idx = 2, 82262395Sbapt als_idx = 19 83262395Sbapt}; 84262395Sbapt 85262395Sbaptenum mem_use_type { 86262395Sbapt USE_DRAM, 87262395Sbapt USE_C2P_REG, 88262395Sbapt}; 89262395Sbapt 90262395Sbaptstruct hpd_status { 91262395Sbapt union { 92262395Sbapt struct { 93262395Sbapt u32 object_distance : 16; 94262395Sbapt u32 probablity : 8; 95262395Sbapt u32 human_presence_actual : 4; 96262395Sbapt u32 human_presence_report : 4; 97262395Sbapt } shpd; 98262395Sbapt u32 val; 99262395Sbapt }; 100262395Sbapt}; 101262395Sbapt 102262395Sbaptint amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id); 103262395Sbaptint amd_sfh_hid_client_init(struct amd_mp2_dev *privdata); 104262395Sbaptint amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata); 105262395Sbaptvoid amd_sfh_set_desc_ops(struct amd_mp2_ops *mp2_ops); 106262395Sbapt 107262395Sbapt#endif 108262395Sbapt