1// SPDX-License-Identifier: MIT 2/* 3 * Copyright �� 2021-2024 Intel Corporation 4 */ 5 6#include <linux/pci.h> 7 8#include <drm/drm_managed.h> 9#include <drm/drm_print.h> 10 11#include "regs/xe_bars.h" 12#include "regs/xe_gt_regs.h" 13#include "regs/xe_regs.h" 14#include "xe_assert.h" 15#include "xe_device.h" 16#include "xe_force_wake.h" 17#include "xe_gt_mcr.h" 18#include "xe_gt_sriov_vf.h" 19#include "xe_mmio.h" 20#include "xe_module.h" 21#include "xe_sriov.h" 22#include "xe_vram.h" 23 24#define BAR_SIZE_SHIFT 20 25 26static void 27_resize_bar(struct xe_device *xe, int resno, resource_size_t size) 28{ 29 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 30 int bar_size = pci_rebar_bytes_to_size(size); 31 int ret; 32 33 if (pci_resource_len(pdev, resno)) 34 pci_release_resource(pdev, resno); 35 36 ret = pci_resize_resource(pdev, resno, bar_size); 37 if (ret) { 38 drm_info(&xe->drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support in your BIOS\n", 39 resno, 1 << bar_size, ERR_PTR(ret)); 40 return; 41 } 42 43 drm_info(&xe->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size); 44} 45 46/* 47 * if force_vram_bar_size is set, attempt to set to the requested size 48 * else set to maximum possible size 49 */ 50static void resize_vram_bar(struct xe_device *xe) 51{ 52 u64 force_vram_bar_size = xe_modparam.force_vram_bar_size; 53 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 54 struct pci_bus *root = pdev->bus; 55 resource_size_t current_size; 56 resource_size_t rebar_size; 57 struct resource *root_res; 58 u32 bar_size_mask; 59 u32 pci_cmd; 60 int i; 61 62 /* gather some relevant info */ 63 current_size = pci_resource_len(pdev, LMEM_BAR); 64 bar_size_mask = pci_rebar_get_possible_sizes(pdev, LMEM_BAR); 65 66 if (!bar_size_mask) 67 return; 68 69 /* set to a specific size? */ 70 if (force_vram_bar_size) { 71 u32 bar_size_bit; 72 73 rebar_size = force_vram_bar_size * (resource_size_t)SZ_1M; 74 75 bar_size_bit = bar_size_mask & BIT(pci_rebar_bytes_to_size(rebar_size)); 76 77 if (!bar_size_bit) { 78 drm_info(&xe->drm, 79 "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leaving default: %lluMiB\n", 80 (u64)rebar_size >> 20, bar_size_mask, (u64)current_size >> 20); 81 return; 82 } 83 84 rebar_size = 1ULL << (__fls(bar_size_bit) + BAR_SIZE_SHIFT); 85 86 if (rebar_size == current_size) 87 return; 88 } else { 89 rebar_size = 1ULL << (__fls(bar_size_mask) + BAR_SIZE_SHIFT); 90 91 /* only resize if larger than current */ 92 if (rebar_size <= current_size) 93 return; 94 } 95 96 drm_info(&xe->drm, "Attempting to resize bar from %lluMiB -> %lluMiB\n", 97 (u64)current_size >> 20, (u64)rebar_size >> 20); 98 99 while (root->parent) 100 root = root->parent; 101 102 pci_bus_for_each_resource(root, root_res, i) { 103 if (root_res && root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && 104 (u64)root_res->start > 0x100000000ul) 105 break; 106 } 107 108 if (!root_res) { 109 drm_info(&xe->drm, "Can't resize VRAM BAR - platform support is missing. Consider enabling 'Resizable BAR' support in your BIOS\n"); 110 return; 111 } 112 113 pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd); 114 pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd & ~PCI_COMMAND_MEMORY); 115 116 _resize_bar(xe, LMEM_BAR, rebar_size); 117 118 pci_assign_unassigned_bus_resources(pdev->bus); 119 pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); 120} 121 122static bool resource_is_valid(struct pci_dev *pdev, int bar) 123{ 124 if (!pci_resource_flags(pdev, bar)) 125 return false; 126 127 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 128 return false; 129 130 if (!pci_resource_len(pdev, bar)) 131 return false; 132 133 return true; 134} 135 136static int determine_lmem_bar_size(struct xe_device *xe) 137{ 138 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 139 140 if (!resource_is_valid(pdev, LMEM_BAR)) { 141 drm_err(&xe->drm, "pci resource is not valid\n"); 142 return -ENXIO; 143 } 144 145 resize_vram_bar(xe); 146 147 xe->mem.vram.io_start = pci_resource_start(pdev, LMEM_BAR); 148 xe->mem.vram.io_size = pci_resource_len(pdev, LMEM_BAR); 149 if (!xe->mem.vram.io_size) 150 return -EIO; 151 152 /* XXX: Need to change when xe link code is ready */ 153 xe->mem.vram.dpa_base = 0; 154 155 /* set up a map to the total memory area. */ 156 xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.io_size); 157 158 return 0; 159} 160 161static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size) 162{ 163 struct xe_device *xe = gt_to_xe(gt); 164 u64 offset; 165 u32 reg; 166 167 if (GRAPHICS_VER(xe) >= 20) { 168 u64 ccs_size = tile_size / 512; 169 u64 offset_hi, offset_lo; 170 u32 nodes, num_enabled; 171 172 reg = xe_mmio_read32(gt, MIRROR_FUSE3); 173 nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg); 174 num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */ 175 176 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER); 177 offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg); 178 179 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER); 180 offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg); 181 182 offset = offset_hi << 32; /* HW view bits 39:32 */ 183 offset |= offset_lo << 6; /* HW view bits 31:6 */ 184 offset *= num_enabled; /* convert to SW view */ 185 186 /* We don't expect any holes */ 187 xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size), 188 "Hole between CCS and GSM.\n"); 189 } else { 190 reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR); 191 offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K; 192 } 193 194 return offset; 195} 196 197/* 198 * tile_vram_size() - Collect vram size and offset information 199 * @tile: tile to get info for 200 * @vram_size: available vram (size - device reserved portions) 201 * @tile_size: actual vram size 202 * @tile_offset: physical start point in the vram address space 203 * 204 * There are 4 places for size information: 205 * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1) 206 * - TILEx size (actual vram size) 207 * - GSMBASE offset (TILEx - "stolen") 208 * - CSSBASE offset (TILEx - CSS space necessary) 209 * 210 * CSSBASE is always a lower/smaller offset then GSMBASE. 211 * 212 * The actual available size of memory is to the CCS or GSM base. 213 * NOTE: multi-tile bases will include the tile offset. 214 * 215 */ 216static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, 217 u64 *tile_size, u64 *tile_offset) 218{ 219 struct xe_device *xe = tile_to_xe(tile); 220 struct xe_gt *gt = tile->primary_gt; 221 u64 offset; 222 int err; 223 u32 reg; 224 225 if (IS_SRIOV_VF(xe)) { 226 struct xe_tile *t; 227 int id; 228 229 offset = 0; 230 for_each_tile(t, xe, id) 231 for_each_if(t->id < tile->id) 232 offset += xe_gt_sriov_vf_lmem(t->primary_gt); 233 234 *tile_size = xe_gt_sriov_vf_lmem(gt); 235 *vram_size = *tile_size; 236 *tile_offset = offset; 237 238 return 0; 239 } 240 241 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 242 if (err) 243 return err; 244 245 /* actual size */ 246 if (unlikely(xe->info.platform == XE_DG1)) { 247 *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR); 248 *tile_offset = 0; 249 } else { 250 reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE_ADDR_RANGE(gt->info.id)); 251 *tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G; 252 *tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G; 253 } 254 255 /* minus device usage */ 256 if (xe->info.has_flat_ccs) { 257 offset = get_flat_ccs_offset(gt, *tile_size); 258 } else { 259 offset = xe_mmio_read64_2x32(gt, GSMBASE); 260 } 261 262 /* remove the tile offset so we have just the available size */ 263 *vram_size = offset - *tile_offset; 264 265 return xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 266} 267 268static void vram_fini(void *arg) 269{ 270 struct xe_device *xe = arg; 271 struct xe_tile *tile; 272 int id; 273 274 if (xe->mem.vram.mapping) 275 iounmap(xe->mem.vram.mapping); 276 277 xe->mem.vram.mapping = NULL; 278 279 for_each_tile(tile, xe, id) 280 tile->mem.vram.mapping = NULL; 281} 282 283/** 284 * xe_vram_probe() - Probe VRAM configuration 285 * @xe: the &xe_device 286 * 287 * Collect VRAM size and offset information for all tiles. 288 * 289 * Return: 0 on success, error code on failure 290 */ 291int xe_vram_probe(struct xe_device *xe) 292{ 293 struct xe_tile *tile; 294 resource_size_t io_size; 295 u64 available_size = 0; 296 u64 total_size = 0; 297 u64 tile_offset; 298 u64 tile_size; 299 u64 vram_size; 300 int err; 301 u8 id; 302 303 if (!IS_DGFX(xe)) 304 return 0; 305 306 /* Get the size of the root tile's vram for later accessibility comparison */ 307 tile = xe_device_get_root_tile(xe); 308 err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset); 309 if (err) 310 return err; 311 312 err = determine_lmem_bar_size(xe); 313 if (err) 314 return err; 315 316 drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &xe->mem.vram.io_start, 317 &xe->mem.vram.io_size); 318 319 io_size = xe->mem.vram.io_size; 320 321 /* tile specific ranges */ 322 for_each_tile(tile, xe, id) { 323 err = tile_vram_size(tile, &vram_size, &tile_size, &tile_offset); 324 if (err) 325 return err; 326 327 tile->mem.vram.actual_physical_size = tile_size; 328 tile->mem.vram.io_start = xe->mem.vram.io_start + tile_offset; 329 tile->mem.vram.io_size = min_t(u64, vram_size, io_size); 330 331 if (!tile->mem.vram.io_size) { 332 drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n"); 333 return -ENODEV; 334 } 335 336 tile->mem.vram.dpa_base = xe->mem.vram.dpa_base + tile_offset; 337 tile->mem.vram.usable_size = vram_size; 338 tile->mem.vram.mapping = xe->mem.vram.mapping + tile_offset; 339 340 if (tile->mem.vram.io_size < tile->mem.vram.usable_size) 341 drm_info(&xe->drm, "Small BAR device\n"); 342 drm_info(&xe->drm, "VRAM[%u, %u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", id, 343 tile->id, &tile->mem.vram.actual_physical_size, &tile->mem.vram.usable_size, &tile->mem.vram.io_size); 344 drm_info(&xe->drm, "VRAM[%u, %u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", id, tile->id, 345 &tile->mem.vram.dpa_base, tile->mem.vram.dpa_base + (u64)tile->mem.vram.actual_physical_size, 346 &tile->mem.vram.io_start, tile->mem.vram.io_start + (u64)tile->mem.vram.io_size); 347 348 /* calculate total size using tile size to get the correct HW sizing */ 349 total_size += tile_size; 350 available_size += vram_size; 351 352 if (total_size > xe->mem.vram.io_size) { 353 drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n", 354 &total_size, &xe->mem.vram.io_size); 355 } 356 357 io_size -= min_t(u64, tile_size, io_size); 358 } 359 360 xe->mem.vram.actual_physical_size = total_size; 361 362 drm_info(&xe->drm, "Total VRAM: %pa, %pa\n", &xe->mem.vram.io_start, 363 &xe->mem.vram.actual_physical_size); 364 drm_info(&xe->drm, "Available VRAM: %pa, %pa\n", &xe->mem.vram.io_start, 365 &available_size); 366 367 return devm_add_action_or_reset(xe->drm.dev, vram_fini, xe); 368} 369