1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright �� 2023 Intel Corporation
4 */
5
6#ifndef _XE_GPU_SCHEDULER_TYPES_H_
7#define _XE_GPU_SCHEDULER_TYPES_H_
8
9#include <drm/gpu_scheduler.h>
10
11/**
12 * struct xe_sched_msg - an in-band (relative to GPU scheduler run queue)
13 * message
14 *
15 * Generic enough for backend defined messages, backend can expand if needed.
16 */
17struct xe_sched_msg {
18	/** @link: list link into the gpu scheduler list of messages */
19	struct list_head		link;
20	/**
21	 * @private_data: opaque pointer to message private data (backend defined)
22	 */
23	void				*private_data;
24	/** @opcode: opcode of message (backend defined) */
25	unsigned int			opcode;
26};
27
28/**
29 * struct xe_sched_backend_ops - Define the backend operations called by the
30 * scheduler
31 */
32struct xe_sched_backend_ops {
33	/**
34	 * @process_msg: Process a message. Allowed to block, it is this
35	 * function's responsibility to free message if dynamically allocated.
36	 */
37	void (*process_msg)(struct xe_sched_msg *msg);
38};
39
40/**
41 * struct xe_gpu_scheduler - Xe GPU scheduler
42 */
43struct xe_gpu_scheduler {
44	/** @base: DRM GPU scheduler */
45	struct drm_gpu_scheduler		base;
46	/** @ops: Xe scheduler ops */
47	const struct xe_sched_backend_ops	*ops;
48	/** @msgs: list of messages to be processed in @work_process_msg */
49	struct list_head			msgs;
50	/** @work_process_msg: processes messages */
51	struct work_struct		work_process_msg;
52};
53
54#define xe_sched_entity		drm_sched_entity
55#define xe_sched_policy		drm_sched_policy
56
57#endif
58