1/* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2/* 3 * Copyright 1998-2021 VMware, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person 6 * obtaining a copy of this software and associated documentation 7 * files (the "Software"), to deal in the Software without 8 * restriction, including without limitation the rights to use, copy, 9 * modify, merge, publish, distribute, sublicense, and/or sell copies 10 * of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be 14 * included in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 19 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 20 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 21 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 */ 26 27/* 28 * svga_reg.h -- 29 * 30 * Virtual hardware definitions for the VMware SVGA II device. 31 */ 32 33 34 35#ifndef _SVGA_REG_H_ 36#define _SVGA_REG_H_ 37 38#include "vm_basic_types.h" 39 40typedef enum { 41 SVGA_REG_ENABLE_DISABLE = 0, 42 SVGA_REG_ENABLE_ENABLE = (1 << 0), 43 SVGA_REG_ENABLE_HIDE = (1 << 1), 44} SvgaRegEnable; 45 46typedef uint32 SVGAMobId; 47 48#define SVGA_MAX_WIDTH 2560 49#define SVGA_MAX_HEIGHT 1600 50 51#define SVGA_MAX_BITS_PER_PIXEL 32 52#define SVGA_MAX_DEPTH 24 53#define SVGA_MAX_DISPLAYS 10 54#define SVGA_MAX_SCREEN_SIZE 8192 55#define SVGA_SCREEN_ROOT_LIMIT (SVGA_MAX_SCREEN_SIZE * SVGA_MAX_DISPLAYS) 56 57#define SVGA_CURSOR_ON_HIDE 0x0 58#define SVGA_CURSOR_ON_SHOW 0x1 59 60#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 61 62#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 63 64#define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000 65 66#define SVGA_MAX_PSEUDOCOLOR_DEPTH 8 67#define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH) 68#define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS) 69 70#define SVGA_MAGIC 0x900000UL 71#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 72 73#define SVGA_VERSION_3 3 74#define SVGA_ID_3 SVGA_MAKE_ID(SVGA_VERSION_3) 75 76#define SVGA_VERSION_2 2 77#define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2) 78 79#define SVGA_VERSION_1 1 80#define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1) 81 82#define SVGA_VERSION_0 0 83#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0) 84 85#define SVGA_ID_INVALID 0xFFFFFFFF 86 87#define SVGA_INDEX_PORT 0x0 88#define SVGA_VALUE_PORT 0x1 89#define SVGA_BIOS_PORT 0x2 90#define SVGA_IRQSTATUS_PORT 0x8 91 92#define SVGA_IRQFLAG_ANY_FENCE (1 << 0) 93#define SVGA_IRQFLAG_FIFO_PROGRESS (1 << 1) 94#define SVGA_IRQFLAG_FENCE_GOAL (1 << 2) 95#define SVGA_IRQFLAG_COMMAND_BUFFER (1 << 3) 96#define SVGA_IRQFLAG_ERROR (1 << 4) 97#define SVGA_IRQFLAG_REG_FENCE_GOAL (1 << 5) 98#define SVGA_IRQFLAG_MAX (1 << 6) 99 100#define SVGA_MAX_CURSOR_CMD_BYTES (40 * 1024) 101#define SVGA_MAX_CURSOR_CMD_DIMENSION 1024 102 103enum { 104 SVGA_REG_ID = 0, 105 SVGA_REG_ENABLE = 1, 106 SVGA_REG_WIDTH = 2, 107 SVGA_REG_HEIGHT = 3, 108 SVGA_REG_MAX_WIDTH = 4, 109 SVGA_REG_MAX_HEIGHT = 5, 110 SVGA_REG_DEPTH = 6, 111 SVGA_REG_BITS_PER_PIXEL = 7, 112 SVGA_REG_PSEUDOCOLOR = 8, 113 SVGA_REG_RED_MASK = 9, 114 SVGA_REG_GREEN_MASK = 10, 115 SVGA_REG_BLUE_MASK = 11, 116 SVGA_REG_BYTES_PER_LINE = 12, 117 SVGA_REG_FB_START = 13, 118 SVGA_REG_FB_OFFSET = 14, 119 SVGA_REG_VRAM_SIZE = 15, 120 SVGA_REG_FB_SIZE = 16, 121 122 SVGA_REG_ID_0_TOP = 17, 123 124 SVGA_REG_CAPABILITIES = 17, 125 SVGA_REG_MEM_START = 18, 126 SVGA_REG_MEM_SIZE = 19, 127 SVGA_REG_CONFIG_DONE = 20, 128 SVGA_REG_SYNC = 21, 129 SVGA_REG_BUSY = 22, 130 SVGA_REG_GUEST_ID = 23, 131 SVGA_REG_DEAD = 24, 132 SVGA_REG_CURSOR_X = 25, 133 SVGA_REG_CURSOR_Y = 26, 134 SVGA_REG_CURSOR_ON = 27, 135 SVGA_REG_HOST_BITS_PER_PIXEL = 28, 136 SVGA_REG_SCRATCH_SIZE = 29, 137 SVGA_REG_MEM_REGS = 30, 138 SVGA_REG_NUM_DISPLAYS = 31, 139 SVGA_REG_PITCHLOCK = 32, 140 SVGA_REG_IRQMASK = 33, 141 142 SVGA_REG_NUM_GUEST_DISPLAYS = 34, 143 SVGA_REG_DISPLAY_ID = 35, 144 SVGA_REG_DISPLAY_IS_PRIMARY = 36, 145 SVGA_REG_DISPLAY_POSITION_X = 37, 146 SVGA_REG_DISPLAY_POSITION_Y = 38, 147 SVGA_REG_DISPLAY_WIDTH = 39, 148 SVGA_REG_DISPLAY_HEIGHT = 40, 149 150 SVGA_REG_GMR_ID = 41, 151 SVGA_REG_GMR_DESCRIPTOR = 42, 152 SVGA_REG_GMR_MAX_IDS = 43, 153 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44, 154 155 SVGA_REG_TRACES = 45, 156 SVGA_REG_GMRS_MAX_PAGES = 46, 157 SVGA_REG_MEMORY_SIZE = 47, 158 SVGA_REG_COMMAND_LOW = 48, 159 SVGA_REG_COMMAND_HIGH = 49, 160 161 SVGA_REG_MAX_PRIMARY_MEM = 50, 162 163 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, 164 165 SVGA_REG_DEV_CAP = 52, 166 SVGA_REG_CMD_PREPEND_LOW = 53, 167 SVGA_REG_CMD_PREPEND_HIGH = 54, 168 SVGA_REG_SCREENTARGET_MAX_WIDTH = 55, 169 SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56, 170 SVGA_REG_MOB_MAX_SIZE = 57, 171 SVGA_REG_BLANK_SCREEN_TARGETS = 58, 172 SVGA_REG_CAP2 = 59, 173 SVGA_REG_DEVEL_CAP = 60, 174 175 SVGA_REG_GUEST_DRIVER_ID = 61, 176 SVGA_REG_GUEST_DRIVER_VERSION1 = 62, 177 SVGA_REG_GUEST_DRIVER_VERSION2 = 63, 178 SVGA_REG_GUEST_DRIVER_VERSION3 = 64, 179 180 SVGA_REG_CURSOR_MOBID = 65, 181 SVGA_REG_CURSOR_MAX_BYTE_SIZE = 66, 182 SVGA_REG_CURSOR_MAX_DIMENSION = 67, 183 184 SVGA_REG_FIFO_CAPS = 68, 185 SVGA_REG_FENCE = 69, 186 187 SVGA_REG_CURSOR4_ON = 70, 188 SVGA_REG_CURSOR4_X = 71, 189 SVGA_REG_CURSOR4_Y = 72, 190 SVGA_REG_CURSOR4_SCREEN_ID = 73, 191 SVGA_REG_CURSOR4_SUBMIT = 74, 192 193 SVGA_REG_SCREENDMA = 75, 194 195 SVGA_REG_GBOBJECT_MEM_SIZE_KB = 76, 196 197 SVGA_REG_REGS_START_HIGH32 = 77, 198 SVGA_REG_REGS_START_LOW32 = 78, 199 SVGA_REG_FB_START_HIGH32 = 79, 200 SVGA_REG_FB_START_LOW32 = 80, 201 202 SVGA_REG_MSHINT = 81, 203 204 SVGA_REG_IRQ_STATUS = 82, 205 206 SVGA_REG_DIRTY_TRACKING = 83, 207 SVGA_REG_FENCE_GOAL = 84, 208 209 SVGA_REG_TOP = 85, 210 211 SVGA_PALETTE_BASE = 1024, 212 213 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS 214 215}; 216 217typedef enum SVGARegGuestDriverId { 218 SVGA_REG_GUEST_DRIVER_ID_UNKNOWN = 0, 219 SVGA_REG_GUEST_DRIVER_ID_WDDM = 1, 220 SVGA_REG_GUEST_DRIVER_ID_LINUX = 2, 221 SVGA_REG_GUEST_DRIVER_ID_MAX, 222 223 SVGA_REG_GUEST_DRIVER_ID_SUBMIT = MAX_UINT32, 224} SVGARegGuestDriverId; 225 226typedef enum SVGARegMSHint { 227 SVGA_REG_MSHINT_DISABLED = 0, 228 SVGA_REG_MSHINT_FULL = 1, 229 SVGA_REG_MSHINT_RESOLVED = 2, 230} SVGARegMSHint; 231 232typedef enum SVGARegDirtyTracking { 233 SVGA_REG_DIRTY_TRACKING_PER_IMAGE = 0, 234 SVGA_REG_DIRTY_TRACKING_PER_SURFACE = 1, 235} SVGARegDirtyTracking; 236 237#define SVGA_GMR_NULL ((uint32)-1) 238#define SVGA_GMR_FRAMEBUFFER ((uint32)-2) 239 240#pragma pack(push, 1) 241typedef struct SVGAGuestMemDescriptor { 242 uint32 ppn; 243 uint32 numPages; 244} SVGAGuestMemDescriptor; 245#pragma pack(pop) 246 247#pragma pack(push, 1) 248typedef struct SVGAGuestPtr { 249 uint32 gmrId; 250 uint32 offset; 251} SVGAGuestPtr; 252#pragma pack(pop) 253 254#define SVGA_CB_MAX_SIZE_DEFAULT (KBYTES_2_BYTES(512)) 255#define SVGA_CB_MAX_SIZE_4MB (MBYTES_2_BYTES(4)) 256#define SVGA_CB_MAX_SIZE SVGA_CB_MAX_SIZE_4MB 257#define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32 258#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) 259 260#define SVGA_CB_CONTEXT_MASK 0x3f 261typedef enum { 262 SVGA_CB_CONTEXT_DEVICE = 0x3f, 263 SVGA_CB_CONTEXT_0 = 0x0, 264 SVGA_CB_CONTEXT_1 = 0x1, 265 SVGA_CB_CONTEXT_MAX = 0x2, 266} SVGACBContext; 267 268typedef enum { 269 270 SVGA_CB_STATUS_NONE = 0, 271 272 SVGA_CB_STATUS_COMPLETED = 1, 273 274 SVGA_CB_STATUS_QUEUE_FULL = 2, 275 276 SVGA_CB_STATUS_COMMAND_ERROR = 3, 277 278 SVGA_CB_STATUS_CB_HEADER_ERROR = 4, 279 280 SVGA_CB_STATUS_PREEMPTED = 5, 281 282 SVGA_CB_STATUS_SUBMISSION_ERROR = 6, 283 284 SVGA_CB_STATUS_PARTIAL_COMPLETE = 7, 285} SVGACBStatus; 286 287typedef enum { 288 SVGA_CB_FLAG_NONE = 0, 289 SVGA_CB_FLAG_NO_IRQ = 1 << 0, 290 SVGA_CB_FLAG_DX_CONTEXT = 1 << 1, 291 SVGA_CB_FLAG_MOB = 1 << 2, 292} SVGACBFlags; 293 294#pragma pack(push, 1) 295typedef struct { 296 volatile SVGACBStatus status; 297 volatile uint32 errorOffset; 298 uint64 id; 299 SVGACBFlags flags; 300 uint32 length; 301 union { 302 PA pa; 303 struct { 304 SVGAMobId mobid; 305 uint32 mobOffset; 306 } mob; 307 } ptr; 308 uint32 offset; 309 uint32 dxContext; 310 uint32 mustBeZero[6]; 311} SVGACBHeader; 312#pragma pack(pop) 313 314typedef enum { 315 SVGA_DC_CMD_NOP = 0, 316 SVGA_DC_CMD_START_STOP_CONTEXT = 1, 317 SVGA_DC_CMD_PREEMPT = 2, 318 SVGA_DC_CMD_START_QUEUE = 3, 319 SVGA_DC_CMD_ASYNC_STOP_QUEUE = 4, 320 SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE = 5, 321 SVGA_DC_CMD_MAX = 6 322} SVGADeviceContextCmdId; 323 324typedef struct SVGADCCmdStartStop { 325 uint32 enable; 326 SVGACBContext context; 327} SVGADCCmdStartStop; 328 329typedef struct SVGADCCmdPreempt { 330 SVGACBContext context; 331 uint32 ignoreIDZero; 332} SVGADCCmdPreempt; 333 334typedef struct SVGADCCmdStartQueue { 335 SVGACBContext context; 336} SVGADCCmdStartQueue; 337 338typedef struct SVGADCCmdAsyncStopQueue { 339 SVGACBContext context; 340} SVGADCCmdAsyncStopQueue; 341 342typedef struct SVGADCCmdEmptyQueue { 343 SVGACBContext context; 344} SVGADCCmdEmptyQueue; 345 346typedef struct SVGAGMRImageFormat { 347 union { 348 struct { 349 uint32 bitsPerPixel : 8; 350 uint32 colorDepth : 8; 351 uint32 reserved : 16; 352 }; 353 354 uint32 value; 355 }; 356} SVGAGMRImageFormat; 357 358#pragma pack(push, 1) 359typedef struct SVGAGuestImage { 360 SVGAGuestPtr ptr; 361 362 uint32 pitch; 363} SVGAGuestImage; 364#pragma pack(pop) 365 366typedef struct SVGAColorBGRX { 367 union { 368 struct { 369 uint32 b : 8; 370 uint32 g : 8; 371 uint32 r : 8; 372 uint32 x : 8; 373 }; 374 375 uint32 value; 376 }; 377} SVGAColorBGRX; 378 379#pragma pack(push, 1) 380typedef struct { 381 int32 left; 382 int32 top; 383 int32 right; 384 int32 bottom; 385} SVGASignedRect; 386#pragma pack(pop) 387 388#pragma pack(push, 1) 389typedef struct { 390 int32 x; 391 int32 y; 392} SVGASignedPoint; 393#pragma pack(pop) 394 395#pragma pack(push, 1) 396typedef struct { 397 uint32 x; 398 uint32 y; 399} SVGAUnsignedPoint; 400#pragma pack(pop) 401 402#define SVGA_CAP_NONE 0x00000000 403#define SVGA_CAP_RECT_COPY 0x00000002 404#define SVGA_CAP_CURSOR 0x00000020 405#define SVGA_CAP_CURSOR_BYPASS 0x00000040 406#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 407#define SVGA_CAP_8BIT_EMULATION 0x00000100 408#define SVGA_CAP_ALPHA_CURSOR 0x00000200 409#define SVGA_CAP_3D 0x00004000 410#define SVGA_CAP_EXTENDED_FIFO 0x00008000 411#define SVGA_CAP_MULTIMON 0x00010000 412#define SVGA_CAP_PITCHLOCK 0x00020000 413#define SVGA_CAP_IRQMASK 0x00040000 414#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 415#define SVGA_CAP_GMR 0x00100000 416#define SVGA_CAP_TRACES 0x00200000 417#define SVGA_CAP_GMR2 0x00400000 418#define SVGA_CAP_SCREEN_OBJECT_2 0x00800000 419#define SVGA_CAP_COMMAND_BUFFERS 0x01000000 420#define SVGA_CAP_DEAD1 0x02000000 421#define SVGA_CAP_CMD_BUFFERS_2 0x04000000 422#define SVGA_CAP_GBOBJECTS 0x08000000 423#define SVGA_CAP_DX 0x10000000 424#define SVGA_CAP_HP_CMD_QUEUE 0x20000000 425#define SVGA_CAP_NO_BB_RESTRICTION 0x40000000 426#define SVGA_CAP_CAP2_REGISTER 0x80000000 427 428#define SVGA_CAP2_NONE 0x00000000 429#define SVGA_CAP2_GROW_OTABLE 0x00000001 430#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002 431#define SVGA_CAP2_DX2 0x00000004 432#define SVGA_CAP2_GB_MEMSIZE_2 0x00000008 433#define SVGA_CAP2_SCREENDMA_REG 0x00000010 434#define SVGA_CAP2_OTABLE_PTDEPTH_2 0x00000020 435#define SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT 0x00000040 436#define SVGA_CAP2_CURSOR_MOB 0x00000080 437#define SVGA_CAP2_MSHINT 0x00000100 438#define SVGA_CAP2_CB_MAX_SIZE_4MB 0x00000200 439#define SVGA_CAP2_DX3 0x00000400 440#define SVGA_CAP2_FRAME_TYPE 0x00000800 441#define SVGA_CAP2_COTABLE_COPY 0x00001000 442#define SVGA_CAP2_TRACE_FULL_FB 0x00002000 443#define SVGA_CAP2_EXTRA_REGS 0x00004000 444#define SVGA_CAP2_LO_STAGING 0x00008000 445#define SVGA_CAP2_VIDEO_BLT 0x00010000 446#define SVGA_CAP2_RESERVED 0x80000000 447 448typedef enum { 449 SVGABackdoorCapDeviceCaps = 0, 450 SVGABackdoorCapFifoCaps = 1, 451 SVGABackdoorCap3dHWVersion = 2, 452 SVGABackdoorCapDeviceCaps2 = 3, 453 SVGABackdoorCapDevelCaps = 4, 454 SVGABackdoorCapDevCaps = 5, 455 SVGABackdoorDevelRenderer = 6, 456 SVGABackdoorDevelUsingISB = 7, 457 SVGABackdoorCapMax = 8, 458} SVGABackdoorCapType; 459 460enum { 461 462 SVGA_FIFO_MIN = 0, 463 SVGA_FIFO_MAX, 464 SVGA_FIFO_NEXT_CMD, 465 SVGA_FIFO_STOP, 466 467 SVGA_FIFO_CAPABILITIES = 4, 468 SVGA_FIFO_FLAGS, 469 470 SVGA_FIFO_FENCE, 471 472 SVGA_FIFO_3D_HWVERSION, 473 474 SVGA_FIFO_PITCHLOCK, 475 476 SVGA_FIFO_CURSOR_ON, 477 SVGA_FIFO_CURSOR_X, 478 SVGA_FIFO_CURSOR_Y, 479 SVGA_FIFO_CURSOR_COUNT, 480 SVGA_FIFO_CURSOR_LAST_UPDATED, 481 482 SVGA_FIFO_RESERVED, 483 484 SVGA_FIFO_CURSOR_SCREEN_ID, 485 486 SVGA_FIFO_DEAD, 487 488 SVGA_FIFO_3D_HWVERSION_REVISED, 489 490 SVGA_FIFO_3D_CAPS = 32, 491 SVGA_FIFO_3D_CAPS_LAST = 32 + 255, 492 493 SVGA_FIFO_GUEST_3D_HWVERSION, 494 SVGA_FIFO_FENCE_GOAL, 495 SVGA_FIFO_BUSY, 496 497 SVGA_FIFO_NUM_REGS 498}; 499 500#define SVGA_FIFO_3D_CAPS_SIZE (SVGA_FIFO_3D_CAPS_LAST - SVGA_FIFO_3D_CAPS + 1) 501 502#define SVGA3D_FIFO_CAPS_RECORD_DEVCAPS 0x100 503typedef uint32 SVGA3dFifoCapsRecordType; 504 505typedef uint32 SVGA3dFifoCapPair[2]; 506 507#pragma pack(push, 1) 508typedef struct SVGA3dFifoCapsRecordHeader { 509 uint32 length; 510 SVGA3dFifoCapsRecordType type; 511 512} SVGA3dFifoCapsRecordHeader; 513#pragma pack(pop) 514 515#define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1) 516 517#define SVGA_FIFO_CAP_NONE 0 518#define SVGA_FIFO_CAP_FENCE (1 << 0) 519#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) 520#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) 521#define SVGA_FIFO_CAP_VIDEO (1 << 3) 522#define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1 << 4) 523#define SVGA_FIFO_CAP_ESCAPE (1 << 5) 524#define SVGA_FIFO_CAP_RESERVE (1 << 6) 525#define SVGA_FIFO_CAP_SCREEN_OBJECT (1 << 7) 526#define SVGA_FIFO_CAP_GMR2 (1 << 8) 527#define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2 528#define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1 << 9) 529#define SVGA_FIFO_CAP_DEAD (1 << 10) 530 531#define SVGA_FIFO_FLAG_NONE 0 532#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) 533#define SVGA_FIFO_FLAG_RESERVED (1 << 31) 534 535#define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff 536 537#define SVGA_SCREENDMA_REG_UNDEFINED 0 538#define SVGA_SCREENDMA_REG_NOT_PRESENT 1 539#define SVGA_SCREENDMA_REG_PRESENT 2 540#define SVGA_SCREENDMA_REG_MAX 3 541 542#define SVGA_NUM_OVERLAY_UNITS 32 543 544#define SVGA_VIDEO_FLAG_COLORKEY 0x0001 545 546enum { 547 SVGA_VIDEO_ENABLED = 0, 548 SVGA_VIDEO_FLAGS, 549 SVGA_VIDEO_DATA_OFFSET, 550 SVGA_VIDEO_FORMAT, 551 SVGA_VIDEO_COLORKEY, 552 SVGA_VIDEO_SIZE, 553 SVGA_VIDEO_WIDTH, 554 SVGA_VIDEO_HEIGHT, 555 SVGA_VIDEO_SRC_X, 556 SVGA_VIDEO_SRC_Y, 557 SVGA_VIDEO_SRC_WIDTH, 558 SVGA_VIDEO_SRC_HEIGHT, 559 SVGA_VIDEO_DST_X, 560 SVGA_VIDEO_DST_Y, 561 SVGA_VIDEO_DST_WIDTH, 562 SVGA_VIDEO_DST_HEIGHT, 563 SVGA_VIDEO_PITCH_1, 564 SVGA_VIDEO_PITCH_2, 565 SVGA_VIDEO_PITCH_3, 566 SVGA_VIDEO_DATA_GMRID, 567 SVGA_VIDEO_DST_SCREEN_ID, 568 SVGA_VIDEO_NUM_REGS 569}; 570 571#pragma pack(push, 1) 572typedef struct SVGAOverlayUnit { 573 uint32 enabled; 574 uint32 flags; 575 uint32 dataOffset; 576 uint32 format; 577 uint32 colorKey; 578 uint32 size; 579 uint32 width; 580 uint32 height; 581 uint32 srcX; 582 uint32 srcY; 583 uint32 srcWidth; 584 uint32 srcHeight; 585 int32 dstX; 586 int32 dstY; 587 uint32 dstWidth; 588 uint32 dstHeight; 589 uint32 pitches[3]; 590 uint32 dataGMRId; 591 uint32 dstScreenId; 592} SVGAOverlayUnit; 593#pragma pack(pop) 594 595#define SVGA_INVALID_DISPLAY_ID ((uint32)-1) 596 597typedef struct SVGADisplayTopology { 598 uint16 displayId; 599 uint16 isPrimary; 600 uint32 width; 601 uint32 height; 602 uint32 positionX; 603 uint32 positionY; 604} SVGADisplayTopology; 605 606#define SVGA_SCREEN_MUST_BE_SET (1 << 0) 607#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET 608#define SVGA_SCREEN_IS_PRIMARY (1 << 1) 609#define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2) 610 611#define SVGA_SCREEN_DEACTIVATE (1 << 3) 612 613#define SVGA_SCREEN_BLANKING (1 << 4) 614 615#pragma pack(push, 1) 616typedef struct { 617 uint32 structSize; 618 uint32 id; 619 uint32 flags; 620 struct { 621 uint32 width; 622 uint32 height; 623 } size; 624 struct { 625 int32 x; 626 int32 y; 627 } root; 628 629 SVGAGuestImage backingStore; 630 631 uint32 cloneCount; 632} SVGAScreenObject; 633#pragma pack(pop) 634 635typedef enum { 636 SVGA_CMD_INVALID_CMD = 0, 637 SVGA_CMD_UPDATE = 1, 638 SVGA_CMD_RECT_COPY = 3, 639 SVGA_CMD_RECT_ROP_COPY = 14, 640 SVGA_CMD_DEFINE_CURSOR = 19, 641 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 642 SVGA_CMD_UPDATE_VERBOSE = 25, 643 SVGA_CMD_FRONT_ROP_FILL = 29, 644 SVGA_CMD_FENCE = 30, 645 SVGA_CMD_ESCAPE = 33, 646 SVGA_CMD_DEFINE_SCREEN = 34, 647 SVGA_CMD_DESTROY_SCREEN = 35, 648 SVGA_CMD_DEFINE_GMRFB = 36, 649 SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37, 650 SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38, 651 SVGA_CMD_ANNOTATION_FILL = 39, 652 SVGA_CMD_ANNOTATION_COPY = 40, 653 SVGA_CMD_DEFINE_GMR2 = 41, 654 SVGA_CMD_REMAP_GMR2 = 42, 655 SVGA_CMD_DEAD = 43, 656 SVGA_CMD_DEAD_2 = 44, 657 SVGA_CMD_NOP = 45, 658 SVGA_CMD_NOP_ERROR = 46, 659 SVGA_CMD_MAX 660} SVGAFifoCmdId; 661 662#define SVGA_CMD_MAX_DATASIZE (256 * 1024) 663#define SVGA_CMD_MAX_ARGS 64 664 665#pragma pack(push, 1) 666typedef struct { 667 uint32 x; 668 uint32 y; 669 uint32 width; 670 uint32 height; 671} SVGAFifoCmdUpdate; 672#pragma pack(pop) 673 674#pragma pack(push, 1) 675typedef struct { 676 uint32 srcX; 677 uint32 srcY; 678 uint32 destX; 679 uint32 destY; 680 uint32 width; 681 uint32 height; 682} SVGAFifoCmdRectCopy; 683#pragma pack(pop) 684 685#pragma pack(push, 1) 686typedef struct { 687 uint32 srcX; 688 uint32 srcY; 689 uint32 destX; 690 uint32 destY; 691 uint32 width; 692 uint32 height; 693 uint32 rop; 694} SVGAFifoCmdRectRopCopy; 695#pragma pack(pop) 696 697#pragma pack(push, 1) 698typedef struct { 699 uint32 id; 700 uint32 hotspotX; 701 uint32 hotspotY; 702 uint32 width; 703 uint32 height; 704 uint32 andMaskDepth; 705 uint32 xorMaskDepth; 706 707} SVGAFifoCmdDefineCursor; 708#pragma pack(pop) 709 710#pragma pack(push, 1) 711typedef struct { 712 uint32 id; 713 uint32 hotspotX; 714 uint32 hotspotY; 715 uint32 width; 716 uint32 height; 717 718} SVGAFifoCmdDefineAlphaCursor; 719#pragma pack(pop) 720 721#pragma pack(push, 1) 722typedef struct { 723 uint32 hotspotX; 724 uint32 hotspotY; 725 uint32 width; 726 uint32 height; 727 uint32 andMaskDepth; 728 uint32 xorMaskDepth; 729 730} SVGAGBColorCursorHeader; 731#pragma pack(pop) 732 733#pragma pack(push, 1) 734typedef struct { 735 uint32 hotspotX; 736 uint32 hotspotY; 737 uint32 width; 738 uint32 height; 739 740} SVGAGBAlphaCursorHeader; 741#pragma pack(pop) 742 743typedef enum { 744 SVGA_COLOR_CURSOR = 0, 745 SVGA_ALPHA_CURSOR = 1, 746} SVGAGBCursorType; 747 748#pragma pack(push, 1) 749typedef struct { 750 SVGAGBCursorType type; 751 union { 752 SVGAGBColorCursorHeader colorHeader; 753 SVGAGBAlphaCursorHeader alphaHeader; 754 } header; 755 uint32 sizeInBytes; 756 757} SVGAGBCursorHeader; 758#pragma pack(pop) 759 760#pragma pack(push, 1) 761typedef struct { 762 uint32 x; 763 uint32 y; 764 uint32 width; 765 uint32 height; 766 uint32 reason; 767} SVGAFifoCmdUpdateVerbose; 768#pragma pack(pop) 769 770#pragma pack(push, 1) 771typedef struct { 772 uint32 color; 773 uint32 x; 774 uint32 y; 775 uint32 width; 776 uint32 height; 777 uint32 rop; 778} SVGAFifoCmdFrontRopFill; 779#pragma pack(pop) 780 781#pragma pack(push, 1) 782typedef struct { 783 uint32 fence; 784} SVGAFifoCmdFence; 785#pragma pack(pop) 786 787#pragma pack(push, 1) 788typedef struct { 789 uint32 nsid; 790 uint32 size; 791 792} SVGAFifoCmdEscape; 793#pragma pack(pop) 794 795#pragma pack(push, 1) 796typedef struct { 797 SVGAScreenObject screen; 798} SVGAFifoCmdDefineScreen; 799#pragma pack(pop) 800 801#pragma pack(push, 1) 802typedef struct { 803 uint32 screenId; 804} SVGAFifoCmdDestroyScreen; 805#pragma pack(pop) 806 807#pragma pack(push, 1) 808typedef struct { 809 SVGAGuestPtr ptr; 810 uint32 bytesPerLine; 811 SVGAGMRImageFormat format; 812} SVGAFifoCmdDefineGMRFB; 813#pragma pack(pop) 814 815#pragma pack(push, 1) 816typedef struct { 817 SVGASignedPoint srcOrigin; 818 SVGASignedRect destRect; 819 uint32 destScreenId; 820} SVGAFifoCmdBlitGMRFBToScreen; 821#pragma pack(pop) 822 823#pragma pack(push, 1) 824typedef struct { 825 SVGASignedPoint destOrigin; 826 SVGASignedRect srcRect; 827 uint32 srcScreenId; 828} SVGAFifoCmdBlitScreenToGMRFB; 829#pragma pack(pop) 830 831#pragma pack(push, 1) 832typedef struct { 833 SVGAColorBGRX color; 834} SVGAFifoCmdAnnotationFill; 835#pragma pack(pop) 836 837#pragma pack(push, 1) 838typedef struct { 839 SVGASignedPoint srcOrigin; 840 uint32 srcScreenId; 841} SVGAFifoCmdAnnotationCopy; 842#pragma pack(pop) 843 844#pragma pack(push, 1) 845typedef struct { 846 uint32 gmrId; 847 uint32 numPages; 848} SVGAFifoCmdDefineGMR2; 849#pragma pack(pop) 850 851typedef enum { 852 SVGA_REMAP_GMR2_PPN32 = 0, 853 SVGA_REMAP_GMR2_VIA_GMR = (1 << 0), 854 SVGA_REMAP_GMR2_PPN64 = (1 << 1), 855 SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2), 856} SVGARemapGMR2Flags; 857 858#pragma pack(push, 1) 859typedef struct { 860 uint32 gmrId; 861 SVGARemapGMR2Flags flags; 862 uint32 offsetPages; 863 uint32 numPages; 864 865} SVGAFifoCmdRemapGMR2; 866#pragma pack(pop) 867 868#define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) 869#define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024) 870#define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024) 871#define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024) 872#define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024) 873#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024) 874#define SVGA_GRAPHICS_MEMORY_KB_MAX_2GB (2 * 1024 * 1024) 875#define SVGA_GRAPHICS_MEMORY_KB_MAX_3GB (3 * 1024 * 1024) 876#define SVGA_GRAPHICS_MEMORY_KB_MAX_4GB (4 * 1024 * 1024) 877#define SVGA_GRAPHICS_MEMORY_KB_MAX_8GB (8 * 1024 * 1024) 878#define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024) 879 880#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) 881 882#if defined(VMX86_SERVER) 883#define SVGA_VRAM_SIZE (4 * 1024 * 1024) 884#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024) 885#define SVGA_FIFO_SIZE (256 * 1024) 886#define SVGA_FIFO_SIZE_3D (516 * 1024) 887#define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024) 888#define SVGA_AUTODETECT_DEFAULT FALSE 889#else 890#define SVGA_VRAM_SIZE (16 * 1024 * 1024) 891#define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE 892#define SVGA_FIFO_SIZE (2 * 1024 * 1024) 893#define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE 894#define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024) 895#define SVGA_AUTODETECT_DEFAULT TRUE 896#endif 897 898#define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024) 899#define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024) 900 901#endif 902