1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3
4#include <linux/delay.h>
5#include <linux/gpio/consumer.h>
6#include <linux/module.h>
7#include <linux/of.h>
8#include <linux/regulator/consumer.h>
9
10#include <drm/drm_mipi_dsi.h>
11#include <drm/drm_modes.h>
12#include <drm/drm_panel.h>
13
14#include <video/mipi_display.h>
15
16static const char * const regulator_names[] = {
17	"vddi",
18	"avdd",
19	"avee",
20};
21
22static const unsigned long regulator_enable_loads[] = {
23	62000,
24	100000,
25	100000,
26};
27
28struct panel_desc {
29	const struct drm_display_mode *display_mode;
30	u32 width_mm;
31	u32 height_mm;
32	unsigned long mode_flags;
33	enum mipi_dsi_pixel_format format;
34	unsigned int lanes;
35	const char *panel_name;
36	int (*init_sequence)(struct mipi_dsi_device *dsi);
37};
38
39struct nt36672e_panel {
40	struct drm_panel panel;
41	struct mipi_dsi_device *dsi;
42	struct gpio_desc *reset_gpio;
43	struct regulator_bulk_data supplies[3];
44	const struct panel_desc *desc;
45};
46
47static inline struct nt36672e_panel *to_nt36672e_panel(struct drm_panel *panel)
48{
49	return container_of(panel, struct nt36672e_panel, panel);
50}
51
52static int nt36672e_1080x2408_60hz_init(struct mipi_dsi_device *dsi)
53{
54	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x10);
55	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
56	mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00);
57	mipi_dsi_dcs_write_seq(dsi, 0xc0, 0x00);
58	mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x89, 0x28, 0x00, 0x08, 0x00, 0xaa, 0x02,
59				0x0e, 0x00, 0x2b, 0x00, 0x07, 0x0d, 0xb7, 0x0c, 0xb7);
60
61	mipi_dsi_dcs_write_seq(dsi, 0xc2, 0x1b, 0xa0);
62	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x20);
63	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
64	mipi_dsi_dcs_write_seq(dsi, 0x01, 0x66);
65	mipi_dsi_dcs_write_seq(dsi, 0x06, 0x40);
66	mipi_dsi_dcs_write_seq(dsi, 0x07, 0x38);
67	mipi_dsi_dcs_write_seq(dsi, 0x2f, 0x83);
68	mipi_dsi_dcs_write_seq(dsi, 0x69, 0x91);
69	mipi_dsi_dcs_write_seq(dsi, 0x95, 0xd1);
70	mipi_dsi_dcs_write_seq(dsi, 0x96, 0xd1);
71	mipi_dsi_dcs_write_seq(dsi, 0xf2, 0x64);
72	mipi_dsi_dcs_write_seq(dsi, 0xf3, 0x54);
73	mipi_dsi_dcs_write_seq(dsi, 0xf4, 0x64);
74	mipi_dsi_dcs_write_seq(dsi, 0xf5, 0x54);
75	mipi_dsi_dcs_write_seq(dsi, 0xf6, 0x64);
76	mipi_dsi_dcs_write_seq(dsi, 0xf7, 0x54);
77	mipi_dsi_dcs_write_seq(dsi, 0xf8, 0x64);
78	mipi_dsi_dcs_write_seq(dsi, 0xf9, 0x54);
79	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x24);
80	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
81	mipi_dsi_dcs_write_seq(dsi, 0x01, 0x0f);
82	mipi_dsi_dcs_write_seq(dsi, 0x03, 0x0c);
83	mipi_dsi_dcs_write_seq(dsi, 0x05, 0x1d);
84	mipi_dsi_dcs_write_seq(dsi, 0x08, 0x2f);
85	mipi_dsi_dcs_write_seq(dsi, 0x09, 0x2e);
86	mipi_dsi_dcs_write_seq(dsi, 0x0a, 0x2d);
87	mipi_dsi_dcs_write_seq(dsi, 0x0b, 0x2c);
88	mipi_dsi_dcs_write_seq(dsi, 0x11, 0x17);
89	mipi_dsi_dcs_write_seq(dsi, 0x12, 0x13);
90	mipi_dsi_dcs_write_seq(dsi, 0x13, 0x15);
91	mipi_dsi_dcs_write_seq(dsi, 0x15, 0x14);
92	mipi_dsi_dcs_write_seq(dsi, 0x16, 0x16);
93	mipi_dsi_dcs_write_seq(dsi, 0x17, 0x18);
94	mipi_dsi_dcs_write_seq(dsi, 0x1b, 0x01);
95	mipi_dsi_dcs_write_seq(dsi, 0x1d, 0x1d);
96	mipi_dsi_dcs_write_seq(dsi, 0x20, 0x2f);
97	mipi_dsi_dcs_write_seq(dsi, 0x21, 0x2e);
98	mipi_dsi_dcs_write_seq(dsi, 0x22, 0x2d);
99	mipi_dsi_dcs_write_seq(dsi, 0x23, 0x2c);
100	mipi_dsi_dcs_write_seq(dsi, 0x29, 0x17);
101	mipi_dsi_dcs_write_seq(dsi, 0x2a, 0x13);
102	mipi_dsi_dcs_write_seq(dsi, 0x2b, 0x15);
103	mipi_dsi_dcs_write_seq(dsi, 0x2f, 0x14);
104	mipi_dsi_dcs_write_seq(dsi, 0x30, 0x16);
105	mipi_dsi_dcs_write_seq(dsi, 0x31, 0x18);
106	mipi_dsi_dcs_write_seq(dsi, 0x32, 0x04);
107	mipi_dsi_dcs_write_seq(dsi, 0x34, 0x10);
108	mipi_dsi_dcs_write_seq(dsi, 0x35, 0x1f);
109	mipi_dsi_dcs_write_seq(dsi, 0x36, 0x1f);
110	mipi_dsi_dcs_write_seq(dsi, 0x4d, 0x14);
111	mipi_dsi_dcs_write_seq(dsi, 0x4e, 0x36);
112	mipi_dsi_dcs_write_seq(dsi, 0x4f, 0x36);
113	mipi_dsi_dcs_write_seq(dsi, 0x53, 0x36);
114	mipi_dsi_dcs_write_seq(dsi, 0x71, 0x30);
115	mipi_dsi_dcs_write_seq(dsi, 0x79, 0x11);
116	mipi_dsi_dcs_write_seq(dsi, 0x7a, 0x82);
117	mipi_dsi_dcs_write_seq(dsi, 0x7b, 0x8f);
118	mipi_dsi_dcs_write_seq(dsi, 0x7d, 0x04);
119	mipi_dsi_dcs_write_seq(dsi, 0x80, 0x04);
120	mipi_dsi_dcs_write_seq(dsi, 0x81, 0x04);
121	mipi_dsi_dcs_write_seq(dsi, 0x82, 0x13);
122	mipi_dsi_dcs_write_seq(dsi, 0x84, 0x31);
123	mipi_dsi_dcs_write_seq(dsi, 0x85, 0x00);
124	mipi_dsi_dcs_write_seq(dsi, 0x86, 0x00);
125	mipi_dsi_dcs_write_seq(dsi, 0x87, 0x00);
126	mipi_dsi_dcs_write_seq(dsi, 0x90, 0x13);
127	mipi_dsi_dcs_write_seq(dsi, 0x92, 0x31);
128	mipi_dsi_dcs_write_seq(dsi, 0x93, 0x00);
129	mipi_dsi_dcs_write_seq(dsi, 0x94, 0x00);
130	mipi_dsi_dcs_write_seq(dsi, 0x95, 0x00);
131	mipi_dsi_dcs_write_seq(dsi, 0x9c, 0xf4);
132	mipi_dsi_dcs_write_seq(dsi, 0x9d, 0x01);
133	mipi_dsi_dcs_write_seq(dsi, 0xa0, 0x0f);
134	mipi_dsi_dcs_write_seq(dsi, 0xa2, 0x0f);
135	mipi_dsi_dcs_write_seq(dsi, 0xa3, 0x02);
136	mipi_dsi_dcs_write_seq(dsi, 0xa4, 0x04);
137	mipi_dsi_dcs_write_seq(dsi, 0xa5, 0x04);
138	mipi_dsi_dcs_write_seq(dsi, 0xc6, 0xc0);
139	mipi_dsi_dcs_write_seq(dsi, 0xc9, 0x00);
140	mipi_dsi_dcs_write_seq(dsi, 0xd9, 0x80);
141	mipi_dsi_dcs_write_seq(dsi, 0xe9, 0x02);
142	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x25);
143	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
144	mipi_dsi_dcs_write_seq(dsi, 0x18, 0x22);
145	mipi_dsi_dcs_write_seq(dsi, 0x19, 0xe4);
146	mipi_dsi_dcs_write_seq(dsi, 0x21, 0x40);
147	mipi_dsi_dcs_write_seq(dsi, 0x66, 0xd8);
148	mipi_dsi_dcs_write_seq(dsi, 0x68, 0x50);
149	mipi_dsi_dcs_write_seq(dsi, 0x69, 0x10);
150	mipi_dsi_dcs_write_seq(dsi, 0x6b, 0x00);
151	mipi_dsi_dcs_write_seq(dsi, 0x6d, 0x0d);
152	mipi_dsi_dcs_write_seq(dsi, 0x6e, 0x48);
153	mipi_dsi_dcs_write_seq(dsi, 0x72, 0x41);
154	mipi_dsi_dcs_write_seq(dsi, 0x73, 0x4a);
155	mipi_dsi_dcs_write_seq(dsi, 0x74, 0xd0);
156	mipi_dsi_dcs_write_seq(dsi, 0x77, 0x62);
157	mipi_dsi_dcs_write_seq(dsi, 0x79, 0x7e);
158	mipi_dsi_dcs_write_seq(dsi, 0x7d, 0x03);
159	mipi_dsi_dcs_write_seq(dsi, 0x7e, 0x15);
160	mipi_dsi_dcs_write_seq(dsi, 0x7f, 0x00);
161	mipi_dsi_dcs_write_seq(dsi, 0x84, 0x4d);
162	mipi_dsi_dcs_write_seq(dsi, 0xcf, 0x80);
163	mipi_dsi_dcs_write_seq(dsi, 0xd6, 0x80);
164	mipi_dsi_dcs_write_seq(dsi, 0xd7, 0x80);
165	mipi_dsi_dcs_write_seq(dsi, 0xef, 0x20);
166	mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x84);
167	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x26);
168	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
169	mipi_dsi_dcs_write_seq(dsi, 0x81, 0x0f);
170	mipi_dsi_dcs_write_seq(dsi, 0x83, 0x01);
171	mipi_dsi_dcs_write_seq(dsi, 0x84, 0x03);
172	mipi_dsi_dcs_write_seq(dsi, 0x85, 0x01);
173	mipi_dsi_dcs_write_seq(dsi, 0x86, 0x03);
174	mipi_dsi_dcs_write_seq(dsi, 0x87, 0x01);
175	mipi_dsi_dcs_write_seq(dsi, 0x88, 0x05);
176	mipi_dsi_dcs_write_seq(dsi, 0x8a, 0x1a);
177	mipi_dsi_dcs_write_seq(dsi, 0x8b, 0x11);
178	mipi_dsi_dcs_write_seq(dsi, 0x8c, 0x24);
179	mipi_dsi_dcs_write_seq(dsi, 0x8e, 0x42);
180	mipi_dsi_dcs_write_seq(dsi, 0x8f, 0x11);
181	mipi_dsi_dcs_write_seq(dsi, 0x90, 0x11);
182	mipi_dsi_dcs_write_seq(dsi, 0x91, 0x11);
183	mipi_dsi_dcs_write_seq(dsi, 0x9a, 0x80);
184	mipi_dsi_dcs_write_seq(dsi, 0x9b, 0x04);
185	mipi_dsi_dcs_write_seq(dsi, 0x9c, 0x00);
186	mipi_dsi_dcs_write_seq(dsi, 0x9d, 0x00);
187	mipi_dsi_dcs_write_seq(dsi, 0x9e, 0x00);
188	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x27);
189	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
190	mipi_dsi_dcs_write_seq(dsi, 0x01, 0x68);
191	mipi_dsi_dcs_write_seq(dsi, 0x20, 0x81);
192	mipi_dsi_dcs_write_seq(dsi, 0x21, 0x6a);
193	mipi_dsi_dcs_write_seq(dsi, 0x25, 0x81);
194	mipi_dsi_dcs_write_seq(dsi, 0x26, 0x94);
195	mipi_dsi_dcs_write_seq(dsi, 0x6e, 0x00);
196	mipi_dsi_dcs_write_seq(dsi, 0x6f, 0x00);
197	mipi_dsi_dcs_write_seq(dsi, 0x70, 0x00);
198	mipi_dsi_dcs_write_seq(dsi, 0x71, 0x00);
199	mipi_dsi_dcs_write_seq(dsi, 0x72, 0x00);
200	mipi_dsi_dcs_write_seq(dsi, 0x75, 0x00);
201	mipi_dsi_dcs_write_seq(dsi, 0x76, 0x00);
202	mipi_dsi_dcs_write_seq(dsi, 0x77, 0x00);
203	mipi_dsi_dcs_write_seq(dsi, 0x7d, 0x09);
204	mipi_dsi_dcs_write_seq(dsi, 0x7e, 0x67);
205	mipi_dsi_dcs_write_seq(dsi, 0x80, 0x23);
206	mipi_dsi_dcs_write_seq(dsi, 0x82, 0x09);
207	mipi_dsi_dcs_write_seq(dsi, 0x83, 0x67);
208	mipi_dsi_dcs_write_seq(dsi, 0x88, 0x01);
209	mipi_dsi_dcs_write_seq(dsi, 0x89, 0x10);
210	mipi_dsi_dcs_write_seq(dsi, 0xa5, 0x10);
211	mipi_dsi_dcs_write_seq(dsi, 0xa6, 0x23);
212	mipi_dsi_dcs_write_seq(dsi, 0xa7, 0x01);
213	mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x40);
214	mipi_dsi_dcs_write_seq(dsi, 0xe5, 0x02);
215	mipi_dsi_dcs_write_seq(dsi, 0xe6, 0xd3);
216	mipi_dsi_dcs_write_seq(dsi, 0xeb, 0x03);
217	mipi_dsi_dcs_write_seq(dsi, 0xec, 0x28);
218	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x2a);
219	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
220	mipi_dsi_dcs_write_seq(dsi, 0x00, 0x91);
221	mipi_dsi_dcs_write_seq(dsi, 0x03, 0x20);
222	mipi_dsi_dcs_write_seq(dsi, 0x07, 0x50);
223	mipi_dsi_dcs_write_seq(dsi, 0x0a, 0x70);
224	mipi_dsi_dcs_write_seq(dsi, 0x0c, 0x04);
225	mipi_dsi_dcs_write_seq(dsi, 0x0d, 0x40);
226	mipi_dsi_dcs_write_seq(dsi, 0x0f, 0x01);
227	mipi_dsi_dcs_write_seq(dsi, 0x11, 0xe0);
228	mipi_dsi_dcs_write_seq(dsi, 0x15, 0x0f);
229	mipi_dsi_dcs_write_seq(dsi, 0x16, 0xa4);
230	mipi_dsi_dcs_write_seq(dsi, 0x19, 0x0f);
231	mipi_dsi_dcs_write_seq(dsi, 0x1a, 0x78);
232	mipi_dsi_dcs_write_seq(dsi, 0x1b, 0x23);
233	mipi_dsi_dcs_write_seq(dsi, 0x1d, 0x36);
234	mipi_dsi_dcs_write_seq(dsi, 0x1e, 0x3e);
235	mipi_dsi_dcs_write_seq(dsi, 0x1f, 0x3e);
236	mipi_dsi_dcs_write_seq(dsi, 0x20, 0x3e);
237	mipi_dsi_dcs_write_seq(dsi, 0x28, 0xfd);
238	mipi_dsi_dcs_write_seq(dsi, 0x29, 0x12);
239	mipi_dsi_dcs_write_seq(dsi, 0x2a, 0xe1);
240	mipi_dsi_dcs_write_seq(dsi, 0x2d, 0x0a);
241	mipi_dsi_dcs_write_seq(dsi, 0x30, 0x49);
242	mipi_dsi_dcs_write_seq(dsi, 0x33, 0x96);
243	mipi_dsi_dcs_write_seq(dsi, 0x34, 0xff);
244	mipi_dsi_dcs_write_seq(dsi, 0x35, 0x40);
245	mipi_dsi_dcs_write_seq(dsi, 0x36, 0xde);
246	mipi_dsi_dcs_write_seq(dsi, 0x37, 0xf9);
247	mipi_dsi_dcs_write_seq(dsi, 0x38, 0x45);
248	mipi_dsi_dcs_write_seq(dsi, 0x39, 0xd9);
249	mipi_dsi_dcs_write_seq(dsi, 0x3a, 0x49);
250	mipi_dsi_dcs_write_seq(dsi, 0x4a, 0xf0);
251	mipi_dsi_dcs_write_seq(dsi, 0x7a, 0x09);
252	mipi_dsi_dcs_write_seq(dsi, 0x7b, 0x40);
253	mipi_dsi_dcs_write_seq(dsi, 0x7f, 0xf0);
254	mipi_dsi_dcs_write_seq(dsi, 0x83, 0x0f);
255	mipi_dsi_dcs_write_seq(dsi, 0x84, 0xa4);
256	mipi_dsi_dcs_write_seq(dsi, 0x87, 0x0f);
257	mipi_dsi_dcs_write_seq(dsi, 0x88, 0x78);
258	mipi_dsi_dcs_write_seq(dsi, 0x89, 0x23);
259	mipi_dsi_dcs_write_seq(dsi, 0x8b, 0x36);
260	mipi_dsi_dcs_write_seq(dsi, 0x8c, 0x7d);
261	mipi_dsi_dcs_write_seq(dsi, 0x8d, 0x7d);
262	mipi_dsi_dcs_write_seq(dsi, 0x8e, 0x7d);
263	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x20);
264	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
265	mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00, 0x00, 0x00, 0x17, 0x00, 0x49, 0x00,
266				0x6a, 0x00, 0x89, 0x00, 0x9f, 0x00, 0xb6, 0x00, 0xc8);
267	mipi_dsi_dcs_write_seq(dsi, 0xb1, 0x00, 0xd9, 0x01, 0x10, 0x01, 0x3a, 0x01,
268				0x7a, 0x01, 0xa9, 0x01, 0xf2, 0x02, 0x2d, 0x02, 0x2e);
269	mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x02, 0x64, 0x02, 0xa3, 0x02, 0xca, 0x03,
270				0x00, 0x03, 0x1e, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a);
271	mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xab, 0x03,
272				0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00);
273	mipi_dsi_dcs_write_seq(dsi, 0xb4, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x51, 0x00,
274				0x71, 0x00, 0x90, 0x00, 0xa7, 0x00, 0xbf, 0x00, 0xd1);
275	mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x00, 0xe2, 0x01, 0x1a, 0x01, 0x43, 0x01,
276				0x83, 0x01, 0xb2, 0x01, 0xfa, 0x02, 0x34, 0x02, 0x36);
277	mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x02, 0x6b, 0x02, 0xa8, 0x02, 0xd0, 0x03,
278				0x03, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5b, 0x03, 0x6b);
279	mipi_dsi_dcs_write_seq(dsi, 0xb7, 0x03, 0x7e, 0x03, 0x94, 0x03, 0xac, 0x03,
280				0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00);
281	mipi_dsi_dcs_write_seq(dsi, 0xb8, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x51, 0x00,
282				0x72, 0x00, 0x92, 0x00, 0xa8, 0x00, 0xbf, 0x00, 0xd1);
283	mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0xe2, 0x01, 0x18, 0x01, 0x42, 0x01,
284				0x81, 0x01, 0xaf, 0x01, 0xf5, 0x02, 0x2f, 0x02, 0x31);
285	mipi_dsi_dcs_write_seq(dsi, 0xba, 0x02, 0x68, 0x02, 0xa6, 0x02, 0xcd, 0x03,
286				0x01, 0x03, 0x1f, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a);
287	mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xab, 0x03,
288				0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00);
289	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x21);
290	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
291	mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00, 0x00, 0x00, 0x17, 0x00, 0x49, 0x00,
292				0x6a, 0x00, 0x89, 0x00, 0x9f, 0x00, 0xb6, 0x00, 0xc8);
293	mipi_dsi_dcs_write_seq(dsi, 0xb1, 0x00, 0xd9, 0x01, 0x10, 0x01, 0x3a, 0x01,
294				0x7a, 0x01, 0xa9, 0x01, 0xf2, 0x02, 0x2d, 0x02, 0x2e);
295	mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x02, 0x64, 0x02, 0xa3, 0x02, 0xca, 0x03,
296				0x00, 0x03, 0x1e, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a);
297	mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xab, 0x03,
298				0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00);
299	mipi_dsi_dcs_write_seq(dsi, 0xb4, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x51, 0x00,
300				0x71, 0x00, 0x90, 0x00, 0xa7, 0x00, 0xbf, 0x00, 0xd1);
301	mipi_dsi_dcs_write_seq(dsi, 0xb5, 0x00, 0xe2, 0x01, 0x1a, 0x01, 0x43, 0x01,
302				0x83, 0x01, 0xb2, 0x01, 0xfa, 0x02, 0x34, 0x02, 0x36);
303	mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x02, 0x6b, 0x02, 0xa8, 0x02, 0xd0, 0x03,
304				0x03, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5b, 0x03, 0x6b);
305	mipi_dsi_dcs_write_seq(dsi, 0xb7, 0x03, 0x7e, 0x03, 0x94, 0x03, 0xac, 0x03,
306				0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00);
307	mipi_dsi_dcs_write_seq(dsi, 0xb8, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x51, 0x00,
308				0x72, 0x00, 0x92, 0x00, 0xa8, 0x00, 0xbf, 0x00, 0xd1);
309	mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0xe2, 0x01, 0x18, 0x01, 0x42, 0x01,
310				0x81, 0x01, 0xaf, 0x01, 0xf5, 0x02, 0x2f, 0x02, 0x31);
311	mipi_dsi_dcs_write_seq(dsi, 0xba, 0x02, 0x68, 0x02, 0xa6, 0x02, 0xcd, 0x03,
312				0x01, 0x03, 0x1f, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a);
313	mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xab, 0x03,
314				0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00);
315	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x2c);
316	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
317	mipi_dsi_dcs_write_seq(dsi, 0x61, 0x1f);
318	mipi_dsi_dcs_write_seq(dsi, 0x62, 0x1f);
319	mipi_dsi_dcs_write_seq(dsi, 0x7e, 0x03);
320	mipi_dsi_dcs_write_seq(dsi, 0x6a, 0x14);
321	mipi_dsi_dcs_write_seq(dsi, 0x6b, 0x36);
322	mipi_dsi_dcs_write_seq(dsi, 0x6c, 0x36);
323	mipi_dsi_dcs_write_seq(dsi, 0x6d, 0x36);
324	mipi_dsi_dcs_write_seq(dsi, 0x53, 0x04);
325	mipi_dsi_dcs_write_seq(dsi, 0x54, 0x04);
326	mipi_dsi_dcs_write_seq(dsi, 0x55, 0x04);
327	mipi_dsi_dcs_write_seq(dsi, 0x56, 0x0f);
328	mipi_dsi_dcs_write_seq(dsi, 0x58, 0x0f);
329	mipi_dsi_dcs_write_seq(dsi, 0x59, 0x0f);
330	mipi_dsi_dcs_write_seq(dsi, 0xff, 0xf0);
331	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
332	mipi_dsi_dcs_write_seq(dsi, 0x5a, 0x00);
333
334	mipi_dsi_dcs_write_seq(dsi, 0xff, 0x10);
335	mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01);
336	mipi_dsi_dcs_write_seq(dsi, 0x51, 0xff);
337	mipi_dsi_dcs_write_seq(dsi, 0x53, 0x24);
338	mipi_dsi_dcs_write_seq(dsi, 0x55, 0x01);
339
340	return 0;
341}
342
343static int nt36672e_power_on(struct nt36672e_panel *ctx)
344{
345	struct mipi_dsi_device *dsi = ctx->dsi;
346	int ret;
347
348	ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
349	if (ret < 0) {
350		dev_err(&dsi->dev, "regulator bulk enable failed: %d\n", ret);
351		return ret;
352	}
353
354	/*
355	 * Reset sequence of nt36672e panel requires the panel to be out of reset
356	 * for 10ms, followed by being held in reset for 10ms and then out again.
357	 */
358	gpiod_set_value(ctx->reset_gpio, 1);
359	usleep_range(10000, 20000);
360	gpiod_set_value(ctx->reset_gpio, 0);
361	usleep_range(10000, 20000);
362	gpiod_set_value(ctx->reset_gpio, 1);
363	usleep_range(10000, 20000);
364
365	return 0;
366}
367
368static int nt36672e_power_off(struct nt36672e_panel *ctx)
369{
370	struct mipi_dsi_device *dsi = ctx->dsi;
371	int ret = 0;
372
373	gpiod_set_value(ctx->reset_gpio, 0);
374
375	ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
376	if (ret)
377		dev_err(&dsi->dev, "regulator bulk disable failed: %d\n", ret);
378
379	return ret;
380}
381
382static int nt36672e_on(struct nt36672e_panel *ctx)
383{
384	struct mipi_dsi_device *dsi = ctx->dsi;
385	const struct panel_desc *desc = ctx->desc;
386	int ret = 0;
387
388	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
389
390	if (desc->init_sequence) {
391		ret = desc->init_sequence(dsi);
392		if (ret < 0) {
393			dev_err(&dsi->dev, "panel init sequence failed: %d\n", ret);
394			return ret;
395		}
396	}
397
398	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
399	if (ret < 0) {
400		dev_err(&dsi->dev, "Failed to exit sleep mode: %d\n", ret);
401		return ret;
402	}
403	msleep(120);
404
405	ret = mipi_dsi_dcs_set_display_on(dsi);
406	if (ret < 0) {
407		dev_err(&dsi->dev, "Failed to set display on: %d\n", ret);
408		return ret;
409	}
410	msleep(100);
411
412	return 0;
413}
414
415static int nt36672e_off(struct nt36672e_panel *ctx)
416{
417	struct mipi_dsi_device *dsi = ctx->dsi;
418	int ret = 0;
419
420	dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
421
422	ret = mipi_dsi_dcs_set_display_off(dsi);
423	if (ret < 0) {
424		dev_err(&dsi->dev, "Failed to set display off: %d\n", ret);
425		return ret;
426	}
427	msleep(20);
428
429	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
430	if (ret < 0) {
431		dev_err(&dsi->dev, "Failed to enter sleep mode: %d\n", ret);
432		return ret;
433	}
434	msleep(60);
435
436	return 0;
437}
438
439static int nt36672e_panel_prepare(struct drm_panel *panel)
440{
441	struct nt36672e_panel *ctx = to_nt36672e_panel(panel);
442	struct mipi_dsi_device *dsi = ctx->dsi;
443	int ret = 0;
444
445	ret = nt36672e_power_on(ctx);
446	if (ret < 0)
447		return ret;
448
449	ret = nt36672e_on(ctx);
450	if (ret < 0) {
451		dev_err(&dsi->dev, "Failed to initialize panel: %d\n", ret);
452		if (nt36672e_power_off(ctx))
453			dev_err(&dsi->dev, "power off failed\n");
454		return ret;
455	}
456
457	return 0;
458}
459
460static int nt36672e_panel_unprepare(struct drm_panel *panel)
461{
462	struct nt36672e_panel *ctx = to_nt36672e_panel(panel);
463	struct mipi_dsi_device *dsi = ctx->dsi;
464	int ret = 0;
465
466	ret = nt36672e_off(ctx);
467	if (ret < 0)
468		dev_err(&dsi->dev, "Failed to un-initialize panel: %d\n", ret);
469
470	ret = nt36672e_power_off(ctx);
471	if (ret < 0)
472		dev_err(&dsi->dev, "power off failed: %d\n", ret);
473
474	return 0;
475}
476
477static const struct drm_display_mode nt36672e_1080x2408_60hz = {
478	.name = "1080x2408",
479	.clock = 181690,
480	.hdisplay = 1080,
481	.hsync_start = 1080 + 76,
482	.hsync_end = 1080 + 76 + 12,
483	.htotal = 1080 + 76 + 12 + 56,
484	.vdisplay = 2408,
485	.vsync_start = 2408 + 46,
486	.vsync_end = 2408 + 46 + 10,
487	.vtotal = 2408 + 46 + 10 + 10,
488	.flags = 0,
489};
490
491static const struct panel_desc nt36672e_panel_desc = {
492	.display_mode = &nt36672e_1080x2408_60hz,
493	.width_mm = 74,
494	.height_mm = 131,
495	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
496	.format = MIPI_DSI_FMT_RGB888,
497	.lanes = 4,
498	.panel_name = "nt36672e fhd plus panel",
499	.init_sequence = nt36672e_1080x2408_60hz_init,
500};
501
502static int nt36672e_panel_get_modes(struct drm_panel *panel, struct drm_connector *connector)
503{
504	struct nt36672e_panel *ctx = to_nt36672e_panel(panel);
505	struct drm_display_mode *mode;
506
507	mode = drm_mode_duplicate(connector->dev, ctx->desc->display_mode);
508	if (!mode)
509		return -ENOMEM;
510
511	drm_mode_set_name(mode);
512
513	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
514	connector->display_info.width_mm = ctx->desc->width_mm;
515	connector->display_info.height_mm = ctx->desc->height_mm;
516	drm_mode_probed_add(connector, mode);
517
518	return 1;
519}
520
521static const struct drm_panel_funcs nt36672e_drm_funcs = {
522	.prepare = nt36672e_panel_prepare,
523	.unprepare = nt36672e_panel_unprepare,
524	.get_modes = nt36672e_panel_get_modes,
525};
526
527static int nt36672e_panel_probe(struct mipi_dsi_device *dsi)
528{
529	struct device *dev = &dsi->dev;
530	struct nt36672e_panel *ctx;
531	int i, ret = 0;
532
533	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
534	if (!ctx)
535		return -ENOMEM;
536
537	ctx->desc = of_device_get_match_data(dev);
538	if (!ctx->desc) {
539		dev_err(dev, "missing device configuration\n");
540		return -ENODEV;
541	}
542
543	for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++) {
544		ctx->supplies[i].supply = regulator_names[i];
545		ctx->supplies[i].init_load_uA = regulator_enable_loads[i];
546	}
547
548	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
549			ctx->supplies);
550	if (ret < 0)
551		return ret;
552
553	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
554	if (IS_ERR(ctx->reset_gpio))
555		return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "Failed to get reset-gpios\n");
556
557	ctx->dsi = dsi;
558	mipi_dsi_set_drvdata(dsi, ctx);
559
560	dsi->lanes = ctx->desc->lanes;
561	dsi->format = ctx->desc->format;
562	dsi->mode_flags = ctx->desc->mode_flags;
563
564	drm_panel_init(&ctx->panel, dev, &nt36672e_drm_funcs, DRM_MODE_CONNECTOR_DSI);
565
566	ret = drm_panel_of_backlight(&ctx->panel);
567	if (ret)
568		return dev_err_probe(dev, ret, "Failed to get backlight\n");
569
570	ctx->panel.prepare_prev_first = true;
571
572	drm_panel_add(&ctx->panel);
573
574	ret = mipi_dsi_attach(dsi);
575	if (ret < 0) {
576		dev_err(dev, "Failed to attach to DSI host: %d\n", ret);
577		goto err_dsi_attach;
578	}
579
580	return 0;
581
582err_dsi_attach:
583	drm_panel_remove(&ctx->panel);
584	return ret;
585}
586
587static void nt36672e_panel_remove(struct mipi_dsi_device *dsi)
588{
589	struct nt36672e_panel *ctx = mipi_dsi_get_drvdata(dsi);
590
591	mipi_dsi_detach(ctx->dsi);
592	drm_panel_remove(&ctx->panel);
593}
594
595static const struct of_device_id nt36672e_of_match[] = {
596	{
597		.compatible = "novatek,nt36672e",
598		.data = &nt36672e_panel_desc,
599	},
600	{ }
601};
602MODULE_DEVICE_TABLE(of, nt36672e_of_match);
603
604static struct mipi_dsi_driver nt36672e_panel_driver = {
605	.driver = {
606		.name = "panel-novatek-nt36672e",
607		.of_match_table = nt36672e_of_match,
608	},
609	.probe = nt36672e_panel_probe,
610	.remove = nt36672e_panel_remove,
611};
612module_mipi_dsi_driver(nt36672e_panel_driver);
613
614MODULE_AUTHOR("Ritesh Kumar <quic_riteshk@quicinc.com>");
615MODULE_DESCRIPTION("Novatek NT36672E DSI Panel Driver");
616MODULE_LICENSE("GPL");
617