1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#ifndef _DPU_HW_CTL_H
7#define _DPU_HW_CTL_H
8
9#include "dpu_hw_mdss.h"
10#include "dpu_hw_util.h"
11#include "dpu_hw_catalog.h"
12#include "dpu_hw_sspp.h"
13
14/**
15 * dpu_ctl_mode_sel: Interface mode selection
16 * DPU_CTL_MODE_SEL_VID:    Video mode interface
17 * DPU_CTL_MODE_SEL_CMD:    Command mode interface
18 */
19enum dpu_ctl_mode_sel {
20	DPU_CTL_MODE_SEL_VID = 0,
21	DPU_CTL_MODE_SEL_CMD
22};
23
24struct dpu_hw_ctl;
25/**
26 * struct dpu_hw_stage_cfg - blending stage cfg
27 * @stage : SSPP_ID at each stage
28 * @multirect_index: index of the rectangle of SSPP.
29 */
30struct dpu_hw_stage_cfg {
31	enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE];
32	enum dpu_sspp_multirect_index multirect_index
33					[DPU_STAGE_MAX][PIPES_PER_STAGE];
34};
35
36/**
37 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
38 * @intf :                 Interface id
39 * @mode_3d:               3d mux configuration
40 * @merge_3d:              3d merge block used
41 * @intf_mode_sel:         Interface mode, cmd / vid
42 * @cdm:                   CDM block used
43 * @stream_sel:            Stream selection for multi-stream interfaces
44 * @dsc:                   DSC BIT masks used
45 */
46struct dpu_hw_intf_cfg {
47	enum dpu_intf intf;
48	enum dpu_wb wb;
49	enum dpu_3d_blend_mode mode_3d;
50	enum dpu_merge_3d merge_3d;
51	enum dpu_ctl_mode_sel intf_mode_sel;
52	enum dpu_cdm cdm;
53	int stream_sel;
54	unsigned int dsc;
55};
56
57/**
58 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
59 * Assumption is these functions will be called after clocks are enabled
60 */
61struct dpu_hw_ctl_ops {
62	/**
63	 * kickoff hw operation for Sw controlled interfaces
64	 * DSI cmd mode and WB interface are SW controlled
65	 * @ctx       : ctl path ctx pointer
66	 */
67	void (*trigger_start)(struct dpu_hw_ctl *ctx);
68
69	/**
70	 * check if the ctl is started
71	 * @ctx       : ctl path ctx pointer
72	 * @Return: true if started, false if stopped
73	 */
74	bool (*is_started)(struct dpu_hw_ctl *ctx);
75
76	/**
77	 * kickoff prepare is in progress hw operation for sw
78	 * controlled interfaces: DSI cmd mode and WB interface
79	 * are SW controlled
80	 * @ctx       : ctl path ctx pointer
81	 */
82	void (*trigger_pending)(struct dpu_hw_ctl *ctx);
83
84	/**
85	 * Clear the value of the cached pending_flush_mask
86	 * No effect on hardware
87	 * @ctx       : ctl path ctx pointer
88	 */
89	void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);
90
91	/**
92	 * Query the value of the cached pending_flush_mask
93	 * No effect on hardware
94	 * @ctx       : ctl path ctx pointer
95	 */
96	u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx);
97
98	/**
99	 * OR in the given flushbits to the cached pending_flush_mask
100	 * No effect on hardware
101	 * @ctx       : ctl path ctx pointer
102	 * @flushbits : module flushmask
103	 */
104	void (*update_pending_flush)(struct dpu_hw_ctl *ctx,
105		u32 flushbits);
106
107	/**
108	 * OR in the given flushbits to the cached pending_(wb_)flush_mask
109	 * No effect on hardware
110	 * @ctx       : ctl path ctx pointer
111	 * @blk       : writeback block index
112	 */
113	void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx,
114		enum dpu_wb blk);
115
116	/**
117	 * OR in the given flushbits to the cached pending_(intf_)flush_mask
118	 * No effect on hardware
119	 * @ctx       : ctl path ctx pointer
120	 * @blk       : interface block index
121	 */
122	void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,
123		enum dpu_intf blk);
124
125	/**
126	 * OR in the given flushbits to the cached pending_(periph_)flush_mask
127	 * No effect on hardware
128	 * @ctx       : ctl path ctx pointer
129	 * @blk       : interface block index
130	 */
131	void (*update_pending_flush_periph)(struct dpu_hw_ctl *ctx,
132					    enum dpu_intf blk);
133
134	/**
135	 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask
136	 * No effect on hardware
137	 * @ctx       : ctl path ctx pointer
138	 * @blk       : interface block index
139	 */
140	void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx,
141		enum dpu_merge_3d blk);
142
143	/**
144	 * OR in the given flushbits to the cached pending_flush_mask
145	 * No effect on hardware
146	 * @ctx       : ctl path ctx pointer
147	 * @blk       : SSPP block index
148	 */
149	void (*update_pending_flush_sspp)(struct dpu_hw_ctl *ctx,
150		enum dpu_sspp blk);
151
152	/**
153	 * OR in the given flushbits to the cached pending_flush_mask
154	 * No effect on hardware
155	 * @ctx       : ctl path ctx pointer
156	 * @blk       : LM block index
157	 */
158	void (*update_pending_flush_mixer)(struct dpu_hw_ctl *ctx,
159		enum dpu_lm blk);
160
161	/**
162	 * OR in the given flushbits to the cached pending_flush_mask
163	 * No effect on hardware
164	 * @ctx       : ctl path ctx pointer
165	 * @blk       : DSPP block index
166	 * @dspp_sub_blk : DSPP sub-block index
167	 */
168	void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx,
169		enum dpu_dspp blk, u32 dspp_sub_blk);
170
171	/**
172	 * OR in the given flushbits to the cached pending_(dsc_)flush_mask
173	 * No effect on hardware
174	 * @ctx: ctl path ctx pointer
175	 * @blk: interface block index
176	 */
177	void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx,
178					 enum dpu_dsc blk);
179
180	/**
181	 * OR in the given flushbits to the cached pending_(cdm_)flush_mask
182	 * No effect on hardware
183	 * @ctx: ctl path ctx pointer
184	 * @cdm_num: idx of cdm to be flushed
185	 */
186	void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num);
187
188	/**
189	 * Write the value of the pending_flush_mask to hardware
190	 * @ctx       : ctl path ctx pointer
191	 */
192	void (*trigger_flush)(struct dpu_hw_ctl *ctx);
193
194	/**
195	 * Read the value of the flush register
196	 * @ctx       : ctl path ctx pointer
197	 * @Return: value of the ctl flush register.
198	 */
199	u32 (*get_flush_register)(struct dpu_hw_ctl *ctx);
200
201	/**
202	 * Setup ctl_path interface config
203	 * @ctx
204	 * @cfg    : interface config structure pointer
205	 */
206	void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx,
207		struct dpu_hw_intf_cfg *cfg);
208
209	/**
210	 * reset ctl_path interface config
211	 * @ctx    : ctl path ctx pointer
212	 * @cfg    : interface config structure pointer
213	 */
214	void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx,
215			struct dpu_hw_intf_cfg *cfg);
216
217	int (*reset)(struct dpu_hw_ctl *c);
218
219	/*
220	 * wait_reset_status - checks ctl reset status
221	 * @ctx       : ctl path ctx pointer
222	 *
223	 * This function checks the ctl reset status bit.
224	 * If the reset bit is set, it keeps polling the status till the hw
225	 * reset is complete.
226	 * Returns: 0 on success or -error if reset incomplete within interval
227	 */
228	int (*wait_reset_status)(struct dpu_hw_ctl *ctx);
229
230	/**
231	 * Set all blend stages to disabled
232	 * @ctx       : ctl path ctx pointer
233	 */
234	void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
235
236	/**
237	 * Configure layer mixer to pipe configuration
238	 * @ctx       : ctl path ctx pointer
239	 * @lm        : layer mixer enumeration
240	 * @cfg       : blend stage configuration
241	 */
242	void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
243		enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
244
245	void (*set_active_pipes)(struct dpu_hw_ctl *ctx,
246		unsigned long *fetch_active);
247};
248
249/**
250 * struct dpu_hw_ctl : CTL PATH driver object
251 * @base: hardware block base structure
252 * @hw: block register map object
253 * @idx: control path index
254 * @caps: control path capabilities
255 * @mixer_count: number of mixers
256 * @mixer_hw_caps: mixer hardware capabilities
257 * @pending_flush_mask: storage for pending ctl_flush managed via ops
258 * @pending_intf_flush_mask: pending INTF flush
259 * @pending_wb_flush_mask: pending WB flush
260 * @pending_dsc_flush_mask: pending DSC flush
261 * @pending_cdm_flush_mask: pending CDM flush
262 * @ops: operation list
263 */
264struct dpu_hw_ctl {
265	struct dpu_hw_blk base;
266	struct dpu_hw_blk_reg_map hw;
267
268	/* ctl path */
269	int idx;
270	const struct dpu_ctl_cfg *caps;
271	int mixer_count;
272	const struct dpu_lm_cfg *mixer_hw_caps;
273	u32 pending_flush_mask;
274	u32 pending_intf_flush_mask;
275	u32 pending_wb_flush_mask;
276	u32 pending_periph_flush_mask;
277	u32 pending_merge_3d_flush_mask;
278	u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];
279	u32 pending_dsc_flush_mask;
280	u32 pending_cdm_flush_mask;
281
282	/* ops */
283	struct dpu_hw_ctl_ops ops;
284};
285
286/**
287 * dpu_hw_ctl - convert base object dpu_hw_base to container
288 * @hw: Pointer to base hardware block
289 * return: Pointer to hardware block container
290 */
291static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
292{
293	return container_of(hw, struct dpu_hw_ctl, base);
294}
295
296/**
297 * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object.
298 * Should be called before accessing any ctl_path register.
299 * @dev:  Corresponding device for devres management
300 * @cfg:  ctl_path catalog entry for which driver object is required
301 * @addr: mapped register io address of MDP
302 * @mixer_count: Number of mixers in @mixer
303 * @mixer: Pointer to an array of Layer Mixers defined in the catalog
304 */
305struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
306				   const struct dpu_ctl_cfg *cfg,
307				   void __iomem *addr,
308				   u32 mixer_count,
309				   const struct dpu_lm_cfg *mixer);
310
311#endif /*_DPU_HW_CTL_H */
312