1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
5 */
6
7#ifndef __DPU_ENCODER_PHYS_H__
8#define __DPU_ENCODER_PHYS_H__
9
10#include <drm/drm_writeback.h>
11#include <linux/jiffies.h>
12
13#include "dpu_kms.h"
14#include "dpu_hw_intf.h"
15#include "dpu_hw_wb.h"
16#include "dpu_hw_pingpong.h"
17#include "dpu_hw_cdm.h"
18#include "dpu_hw_ctl.h"
19#include "dpu_hw_top.h"
20#include "dpu_hw_util.h"
21#include "dpu_encoder.h"
22#include "dpu_crtc.h"
23
24#define DPU_ENCODER_NAME_MAX	16
25
26/* wait for at most 2 vsync for lowest refresh rate (24hz) */
27#define KICKOFF_TIMEOUT_MS		84
28#define KICKOFF_TIMEOUT_JIFFIES		msecs_to_jiffies(KICKOFF_TIMEOUT_MS)
29
30/**
31 * enum dpu_enc_split_role - Role this physical encoder will play in a
32 *	split-panel configuration, where one panel is master, and others slaves.
33 *	Masters have extra responsibilities, like managing the VBLANK IRQ.
34 * @ENC_ROLE_SOLO:	This is the one and only panel. This encoder is master.
35 * @ENC_ROLE_MASTER:	This encoder is the master of a split panel config.
36 * @ENC_ROLE_SLAVE:	This encoder is not the master of a split panel config.
37 */
38enum dpu_enc_split_role {
39	ENC_ROLE_SOLO,
40	ENC_ROLE_MASTER,
41	ENC_ROLE_SLAVE,
42};
43
44/**
45 * enum dpu_enc_enable_state - current enabled state of the physical encoder
46 * @DPU_ENC_DISABLING:	Encoder transitioning to disable state
47 *			Events bounding transition are encoder type specific
48 * @DPU_ENC_DISABLED:	Encoder is disabled
49 * @DPU_ENC_ENABLING:	Encoder transitioning to enabled
50 *			Events bounding transition are encoder type specific
51 * @DPU_ENC_ENABLED:	Encoder is enabled
52 * @DPU_ENC_ERR_NEEDS_HW_RESET:	Encoder is enabled, but requires a hw_reset
53 *				to recover from a previous error
54 */
55enum dpu_enc_enable_state {
56	DPU_ENC_DISABLING,
57	DPU_ENC_DISABLED,
58	DPU_ENC_ENABLING,
59	DPU_ENC_ENABLED,
60	DPU_ENC_ERR_NEEDS_HW_RESET
61};
62
63struct dpu_encoder_phys;
64
65/**
66 * struct dpu_encoder_phys_ops - Interface the physical encoders provide to
67 *	the containing virtual encoder.
68 * @prepare_commit:		MSM Atomic Call, start of atomic commit sequence
69 * @is_master:			Whether this phys_enc is the current master
70 *				encoder. Can be switched at enable time. Based
71 *				on split_role and current mode (CMD/VID).
72 * @enable:			DRM Call. Enable a DRM mode.
73 * @disable:			DRM Call. Disable mode.
74 * @control_vblank_irq		Register/Deregister for VBLANK IRQ
75 * @wait_for_commit_done:	Wait for hardware to have flushed the
76 *				current pending frames to hardware
77 * @wait_for_tx_complete:	Wait for hardware to transfer the pixels
78 *				to the panel
79 * @wait_for_vblank:		Wait for VBLANK, for sub-driver internal use
80 * @prepare_for_kickoff:	Do any work necessary prior to a kickoff
81 *				For CMD encoder, may wait for previous tx done
82 * @handle_post_kickoff:	Do any work necessary post-kickoff work
83 * @trigger_start:		Process start event on physical encoder
84 * @needs_single_flush:		Whether encoder slaves need to be flushed
85 * @irq_enable:			Handler to enable all the encoder IRQs
86 * @irq_disable:		Handler to disable all the encoder IRQs
87 * @prepare_idle_pc:		phys encoder can update the vsync_enable status
88 *                              on idle power collapse prepare
89 * @restore:			Restore all the encoder configs.
90 * @get_line_count:		Obtain current vertical line count
91 */
92
93struct dpu_encoder_phys_ops {
94	void (*prepare_commit)(struct dpu_encoder_phys *encoder);
95	bool (*is_master)(struct dpu_encoder_phys *encoder);
96	void (*enable)(struct dpu_encoder_phys *encoder);
97	void (*disable)(struct dpu_encoder_phys *encoder);
98	int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
99	int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
100	int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
101	void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
102	void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
103	void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
104	bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
105	void (*irq_enable)(struct dpu_encoder_phys *phys);
106	void (*irq_disable)(struct dpu_encoder_phys *phys);
107	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
108	void (*restore)(struct dpu_encoder_phys *phys);
109	int (*get_line_count)(struct dpu_encoder_phys *phys);
110	int (*get_frame_count)(struct dpu_encoder_phys *phys);
111	void (*prepare_wb_job)(struct dpu_encoder_phys *phys_enc,
112			struct drm_writeback_job *job);
113	void (*cleanup_wb_job)(struct dpu_encoder_phys *phys_enc,
114			struct drm_writeback_job *job);
115	bool (*is_valid_for_commit)(struct dpu_encoder_phys *phys_enc);
116};
117
118/**
119 * enum dpu_intr_idx - dpu encoder interrupt index
120 * @INTR_IDX_VSYNC:    Vsync interrupt for video mode panel
121 * @INTR_IDX_PINGPONG: Pingpong done interrupt for cmd mode panel
122 * @INTR_IDX_UNDERRUN: Underrun interrupt for video and cmd mode panel
123 * @INTR_IDX_RDPTR:    Readpointer done interrupt for cmd mode panel
124 * @INTR_IDX_WB_DONE:  Writeback done interrupt for virtual connector
125 */
126enum dpu_intr_idx {
127	INTR_IDX_VSYNC,
128	INTR_IDX_PINGPONG,
129	INTR_IDX_UNDERRUN,
130	INTR_IDX_CTL_START,
131	INTR_IDX_RDPTR,
132	INTR_IDX_WB_DONE,
133	INTR_IDX_MAX,
134};
135
136/**
137 * struct dpu_encoder_phys - physical encoder that drives a single INTF block
138 *	tied to a specific panel / sub-panel. Abstract type, sub-classed by
139 *	phys_vid or phys_cmd for video mode or command mode encs respectively.
140 * @parent:		Pointer to the containing virtual encoder
141 * @ops:		Operations exposed to the virtual encoder
142 * @parent_ops:		Callbacks exposed by the parent to the phys_enc
143 * @hw_mdptop:		Hardware interface to the top registers
144 * @hw_ctl:		Hardware interface to the ctl registers
145 * @hw_pp:		Hardware interface to the ping pong registers
146 * @hw_intf:		Hardware interface to the intf registers
147 * @hw_wb:		Hardware interface to the wb registers
148 * @hw_cdm:		Hardware interface to the CDM registers
149 * @dpu_kms:		Pointer to the dpu_kms top level
150 * @cdm_cfg:		CDM block config needed to store WB/DP block's CDM configuration
151 * @cached_mode:	DRM mode cached at mode_set time, acted on in enable
152 * @vblank_ctl_lock:	Vblank ctl mutex lock to protect vblank_refcount
153 * @enabled:		Whether the encoder has enabled and running a mode
154 * @split_role:		Role to play in a split-panel configuration
155 * @intf_mode:		Interface mode
156 * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
157 * @enable_state:	Enable state tracking
158 * @vblank_refcount:	Reference count of vblank request
159 * @vsync_cnt:		Vsync count for the physical encoder
160 * @underrun_cnt:	Underrun count for the physical encoder
161 * @pending_kickoff_cnt:	Atomic counter tracking the number of kickoffs
162 *				vs. the number of done/vblank irqs. Should hover
163 *				between 0-2 Incremented when a new kickoff is
164 *				scheduled. Decremented in irq handler
165 * @pending_ctlstart_cnt:	Atomic counter tracking the number of ctl start
166 *                              pending.
167 * @pending_kickoff_wq:		Wait queue for blocking until kickoff completes
168 * @irq:			IRQ indices
169 * @has_intf_te:		Interface TE configuration support
170 */
171struct dpu_encoder_phys {
172	struct drm_encoder *parent;
173	struct dpu_encoder_phys_ops ops;
174	struct dpu_hw_mdp *hw_mdptop;
175	struct dpu_hw_ctl *hw_ctl;
176	struct dpu_hw_pingpong *hw_pp;
177	struct dpu_hw_intf *hw_intf;
178	struct dpu_hw_wb *hw_wb;
179	struct dpu_hw_cdm *hw_cdm;
180	struct dpu_kms *dpu_kms;
181	struct dpu_hw_cdm_cfg cdm_cfg;
182	struct drm_display_mode cached_mode;
183	struct mutex vblank_ctl_lock;
184	enum dpu_enc_split_role split_role;
185	enum dpu_intf_mode intf_mode;
186	spinlock_t *enc_spinlock;
187	enum dpu_enc_enable_state enable_state;
188	int vblank_refcount;
189	atomic_t vsync_cnt;
190	atomic_t underrun_cnt;
191	atomic_t pending_ctlstart_cnt;
192	atomic_t pending_kickoff_cnt;
193	wait_queue_head_t pending_kickoff_wq;
194	unsigned int irq[INTR_IDX_MAX];
195	bool has_intf_te;
196};
197
198static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys)
199{
200	atomic_inc_return(&phys->pending_ctlstart_cnt);
201	return atomic_inc_return(&phys->pending_kickoff_cnt);
202}
203
204/**
205 * struct dpu_encoder_phys_wb - sub-class of dpu_encoder_phys to handle command
206 *	mode specific operations
207 * @base:	Baseclass physical encoder structure
208 * @wbirq_refcount:     Reference count of writeback interrupt
209 * @wb_done_timeout_cnt: number of wb done irq timeout errors
210 * @wb_cfg:  writeback block config to store fb related details
211 * @wb_conn: backpointer to writeback connector
212 * @wb_job: backpointer to current writeback job
213 * @dest:   dpu buffer layout for current writeback output buffer
214 */
215struct dpu_encoder_phys_wb {
216	struct dpu_encoder_phys base;
217	atomic_t wbirq_refcount;
218	int wb_done_timeout_cnt;
219	struct dpu_hw_wb_cfg wb_cfg;
220	struct drm_writeback_connector *wb_conn;
221	struct drm_writeback_job *wb_job;
222	struct dpu_hw_fmt_layout dest;
223};
224
225/**
226 * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command
227 *	mode specific operations
228 * @base:	Baseclass physical encoder structure
229 * @intf_idx:	Intf Block index used by this phys encoder
230 * @stream_sel:	Stream selection for multi-stream interfaces
231 * @serialize_wait4pp:	serialize wait4pp feature waits for pp_done interrupt
232 *			after ctl_start instead of before next frame kickoff
233 * @pp_timeout_report_cnt: number of pingpong done irq timeout errors
234 * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK
235 * @pending_vblank_wq: Wait queue for blocking until VBLANK received
236 */
237struct dpu_encoder_phys_cmd {
238	struct dpu_encoder_phys base;
239	int stream_sel;
240	bool serialize_wait4pp;
241	int pp_timeout_report_cnt;
242	atomic_t pending_vblank_cnt;
243	wait_queue_head_t pending_vblank_wq;
244};
245
246/**
247 * struct dpu_enc_phys_init_params - initialization parameters for phys encs
248 * @dpu_kms:		Pointer to the dpu_kms top level
249 * @parent:		Pointer to the containing virtual encoder
250 * @parent_ops:		Callbacks exposed by the parent to the phys_enc
251 * @split_role:		Role to play in a split-panel configuration
252 * @hw_intf:		Hardware interface to the intf registers
253 * @hw_wb:		Hardware interface to the wb registers
254 * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
255 */
256struct dpu_enc_phys_init_params {
257	struct dpu_kms *dpu_kms;
258	struct drm_encoder *parent;
259	enum dpu_enc_split_role split_role;
260	struct dpu_hw_intf *hw_intf;
261	struct dpu_hw_wb *hw_wb;
262	spinlock_t *enc_spinlock;
263};
264
265/**
266 * dpu_encoder_wait_info - container for passing arguments to irq wait functions
267 * @wq: wait queue structure
268 * @atomic_cnt: wait until atomic_cnt equals zero
269 * @timeout_ms: timeout value in milliseconds
270 */
271struct dpu_encoder_wait_info {
272	wait_queue_head_t *wq;
273	atomic_t *atomic_cnt;
274	s64 timeout_ms;
275};
276
277/**
278 * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder
279 * @p:	Pointer to init params structure
280 * Return: Error code or newly allocated encoder
281 */
282struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev,
283		struct dpu_enc_phys_init_params *p);
284
285/**
286 * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder
287 * @dev:  Corresponding device for devres management
288 * @p:	Pointer to init params structure
289 * Return: Error code or newly allocated encoder
290 */
291struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev,
292		struct dpu_enc_phys_init_params *p);
293
294/**
295 * dpu_encoder_phys_wb_init - initialize writeback encoder
296 * @dev:  Corresponding device for devres management
297 * @init:	Pointer to init info structure with initialization params
298 */
299struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev,
300		struct dpu_enc_phys_init_params *p);
301
302/**
303 * dpu_encoder_helper_trigger_start - control start helper function
304 *	This helper function may be optionally specified by physical
305 *	encoders if they require ctl_start triggering.
306 * @phys_enc: Pointer to physical encoder structure
307 */
308void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
309
310static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
311		struct dpu_encoder_phys *phys_enc)
312{
313	struct dpu_crtc_state *dpu_cstate;
314
315	if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
316		return BLEND_3D_NONE;
317
318	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
319
320	/* Use merge_3d unless DSC MERGE topology is used */
321	if (phys_enc->split_role == ENC_ROLE_SOLO &&
322	    dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&
323	    !dpu_encoder_use_dsc_merge(phys_enc->parent))
324		return BLEND_3D_H_ROW_INT;
325
326	return BLEND_3D_NONE;
327}
328
329/**
330 * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
331 *   This helper function is used by physical encoder to get DSC blocks mask
332 *   used for this encoder.
333 * @phys_enc: Pointer to physical encoder structure
334 */
335unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
336
337/**
338 * dpu_encoder_get_drm_fmt - return DRM fourcc format
339 * @phys_enc: Pointer to physical encoder structure
340 */
341u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc);
342
343/**
344 * dpu_encoder_needs_periph_flush - return true if physical encoder requires
345 *	peripheral flush
346 * @phys_enc: Pointer to physical encoder structure
347 */
348bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc);
349
350/**
351 * dpu_encoder_helper_split_config - split display configuration helper function
352 *	This helper function may be used by physical encoders to configure
353 *	the split display related registers.
354 * @phys_enc: Pointer to physical encoder structure
355 * @interface: enum dpu_intf setting
356 */
357void dpu_encoder_helper_split_config(
358		struct dpu_encoder_phys *phys_enc,
359		enum dpu_intf interface);
360
361/**
362 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has
363 *	timed out, including reporting frame error event to crtc and debug dump
364 * @phys_enc: Pointer to physical encoder structure
365 * @intr_idx: Failing interrupt index
366 */
367void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
368		enum dpu_intr_idx intr_idx);
369
370/**
371 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq.
372 *	note: will call dpu_encoder_helper_wait_for_irq on timeout
373 * @phys_enc: Pointer to physical encoder structure
374 * @irq: IRQ index
375 * @func: IRQ callback to be called in case of timeout
376 * @wait_info: wait info struct
377 * @Return: 0 or -ERROR
378 */
379int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
380		unsigned int irq,
381		void (*func)(void *arg),
382		struct dpu_encoder_wait_info *wait_info);
383
384/**
385 * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline
386 * @phys_enc: Pointer to physical encoder structure
387 */
388void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc);
389
390/**
391 * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block
392 * @phys_enc: Pointer to physical encoder
393 * @output_type: HDMI/WB
394 */
395void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
396				       const struct dpu_format *dpu_fmt,
397				       u32 output_type);
398
399/**
400 * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception
401 * @drm_enc:    Pointer to drm encoder structure
402 * @phys_enc:	Pointer to physical encoder
403 * Note: This is called from IRQ handler context.
404 */
405void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
406				 struct dpu_encoder_phys *phy_enc);
407
408/** dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception
409 * @drm_enc:    Pointer to drm encoder structure
410 * @phys_enc:	Pointer to physical encoder
411 * Note: This is called from IRQ handler context.
412 */
413void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
414				   struct dpu_encoder_phys *phy_enc);
415
416/** dpu_encoder_frame_done_callback -- Notify virtual encoder that this phys encoder completes last request frame
417 * @drm_enc:    Pointer to drm encoder structure
418 * @phys_enc:	Pointer to physical encoder
419 * @event:	Event to process
420 */
421void dpu_encoder_frame_done_callback(
422		struct drm_encoder *drm_enc,
423		struct dpu_encoder_phys *ready_phys, u32 event);
424
425void dpu_encoder_phys_init(struct dpu_encoder_phys *phys,
426			   struct dpu_enc_phys_init_params *p);
427
428#endif /* __dpu_encoder_phys_H__ */
429