1178172Simp/* SPDX-License-Identifier: GPL-2.0-only */ 2178172Simp/* 3178172Simp * Copyright (c) 2014 MediaTek Inc. 4178172Simp * Author: Jie Qiu <jie.qiu@mediatek.com> 5178172Simp */ 6178172Simp#ifndef __MTK_DPI_REGS_H 7178172Simp#define __MTK_DPI_REGS_H 8178172Simp 9178172Simp#define DPI_EN 0x00 10178172Simp#define EN BIT(0) 11178172Simp 12178172Simp#define DPI_RET 0x04 13178172Simp#define RST BIT(0) 14178172Simp 15178172Simp#define DPI_INTEN 0x08 16178172Simp#define INT_VSYNC_EN BIT(0) 17178172Simp#define INT_VDE_EN BIT(1) 18178172Simp#define INT_UNDERFLOW_EN BIT(2) 19178172Simp 20178172Simp#define DPI_INTSTA 0x0C 21178172Simp#define INT_VSYNC_STA BIT(0) 22178172Simp#define INT_VDE_STA BIT(1) 23178172Simp#define INT_UNDERFLOW_STA BIT(2) 24178172Simp 25178172Simp#define DPI_CON 0x10 26178172Simp#define BG_ENABLE BIT(0) 27178172Simp#define IN_RB_SWAP BIT(1) 28178172Simp#define INTL_EN BIT(2) 29178172Simp#define TDFP_EN BIT(3) 30178172Simp#define CLPF_EN BIT(4) 31178172Simp#define YUV422_EN BIT(5) 32178172Simp#define CSC_ENABLE BIT(6) 33178172Simp#define R601_SEL BIT(7) 34178172Simp#define EMBSYNC_EN BIT(8) 35178172Simp#define VS_LODD_EN BIT(16) 36178172Simp#define VS_LEVEN_EN BIT(17) 37178172Simp#define VS_RODD_EN BIT(18) 38178172Simp#define VS_REVEN BIT(19) 39178172Simp#define FAKE_DE_LODD BIT(20) 40178172Simp#define FAKE_DE_LEVEN BIT(21) 41178172Simp#define FAKE_DE_RODD BIT(22) 42178172Simp#define FAKE_DE_REVEN BIT(23) 43178172Simp#define DPINTF_YUV422_EN BIT(24) 44178172Simp#define DPINTF_CSC_ENABLE BIT(26) 45178172Simp#define DPINTF_INPUT_2P_EN BIT(29) 46178172Simp 47178172Simp#define DPI_OUTPUT_SETTING 0x14 48178172Simp#define CH_SWAP 0 49178172Simp#define DPINTF_CH_SWAP 1 50178172Simp#define CH_SWAP_MASK (0x7 << 0) 51178172Simp#define SWAP_RGB 0x00 52178172Simp#define SWAP_GBR 0x01 53178172Simp#define SWAP_BRG 0x02 54178172Simp#define SWAP_RBG 0x03 55178172Simp#define SWAP_GRB 0x04 56178172Simp#define SWAP_BGR 0x05 57178172Simp#define BIT_SWAP BIT(3) 58178172Simp#define B_MASK BIT(4) 59178172Simp#define G_MASK BIT(5) 60178172Simp#define R_MASK BIT(6) 61178172Simp#define DE_MASK BIT(8) 62178172Simp#define HS_MASK BIT(9) 63178172Simp#define VS_MASK BIT(10) 64178172Simp#define DE_POL BIT(12) 65178172Simp#define HSYNC_POL BIT(13) 66178172Simp#define VSYNC_POL BIT(14) 67178172Simp#define CK_POL BIT(15) 68178172Simp#define OEN_OFF BIT(16) 69178172Simp#define EDGE_SEL BIT(17) 70178172Simp#define OUT_BIT 18 71178172Simp#define OUT_BIT_MASK (0x3 << 18) 72178172Simp#define OUT_BIT_8 0x00 73211453Sjchandra#define OUT_BIT_10 0x01 74211453Sjchandra#define OUT_BIT_12 0x02 75211453Sjchandra#define OUT_BIT_16 0x03 76211453Sjchandra#define YC_MAP 20 77209928Sjchandra#define YC_MAP_MASK (0x7 << 20) 78210009Simp#define YC_MAP_RGB 0x00 79206829Sjmallett#define YC_MAP_CYCY 0x04 80206829Sjmallett#define YC_MAP_YCYC 0x05 81206829Sjmallett#define YC_MAP_CY 0x06 82206829Sjmallett#define YC_MAP_YC 0x07 83206829Sjmallett 84206829Sjmallett#define DPI_SIZE 0x18 85206829Sjmallett#define HSIZE 0 86206829Sjmallett#define HSIZE_MASK (0x1FFF << 0) 87206829Sjmallett#define DPINTF_HSIZE_MASK (0xFFFF << 0) 88178172Simp#define VSIZE 16 89178172Simp#define VSIZE_MASK (0x1FFF << 16) 90210009Simp#define DPINTF_VSIZE_MASK (0xFFFF << 16) 91178172Simp 92209928Sjchandra#define DPI_DDR_SETTING 0x1C 93209928Sjchandra#define DDR_EN BIT(0) 94211453Sjchandra#define DDDR_SEL BIT(1) 95211453Sjchandra#define DDR_4PHASE BIT(2) 96209928Sjchandra#define DDR_WIDTH (0x3 << 4) 97209928Sjchandra#define DDR_PAD_MODE (0x1 << 8) 98209928Sjchandra 99209928Sjchandra#define DPI_TGEN_HWIDTH 0x20 100209928Sjchandra#define HPW 0 101209928Sjchandra#define HPW_MASK (0xFFF << 0) 102209928Sjchandra#define DPINTF_HPW_MASK (0xFFFF << 0) 103209928Sjchandra 104209928Sjchandra#define DPI_TGEN_HPORCH 0x24 105209928Sjchandra#define HBP 0 106210986Sneel#define HBP_MASK (0xFFF << 0) 107210986Sneel#define DPINTF_HBP_MASK (0xFFFF << 0) 108210986Sneel#define HFP 16 109210986Sneel#define HFP_MASK (0xFFF << 16) 110210986Sneel#define DPINTF_HFP_MASK (0xFFFF << 16) 111210986Sneel 112210986Sneel#define DPI_TGEN_VWIDTH 0x28 113295150Sadrian#define DPI_TGEN_VPORCH 0x2C 114210986Sneel 115210986Sneel#define VSYNC_WIDTH_SHIFT 0 116210986Sneel#define VSYNC_WIDTH_MASK (0xFFF << 0) 117210986Sneel#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) 118210986Sneel#define VSYNC_HALF_LINE_SHIFT 16 119210986Sneel#define VSYNC_HALF_LINE_MASK BIT(16) 120210986Sneel#define VSYNC_BACK_PORCH_SHIFT 0 121210986Sneel#define VSYNC_BACK_PORCH_MASK (0xFFF << 0) 122210986Sneel#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) 123210986Sneel#define VSYNC_FRONT_PORCH_SHIFT 16 124210986Sneel#define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) 125210986Sneel#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) 126210986Sneel 127210986Sneel#define DPI_BG_HCNTL 0x30 128210986Sneel#define BG_RIGHT (0x1FFF << 0) 129206829Sjmallett#define BG_LEFT (0x1FFF << 16) 130210986Sneel 131210986Sneel#define DPI_BG_VCNTL 0x34 132210986Sneel#define BG_BOT (0x1FFF << 0) 133210986Sneel#define BG_TOP (0x1FFF << 16) 134210986Sneel 135210986Sneel#define DPI_BG_COLOR 0x38 136210986Sneel#define BG_B (0xF << 0) 137210986Sneel#define BG_G (0xF << 8) 138210986Sneel#define BG_R (0xF << 16) 139210986Sneel 140210986Sneel#define DPI_FIFO_CTL 0x3C 141210986Sneel#define FIFO_VALID_SET (0x1F << 0) 142210986Sneel#define FIFO_RST_SEL (0x1 << 8) 143210986Sneel 144210986Sneel#define DPI_STATUS 0x40 145210986Sneel#define VCOUNTER (0x1FFF << 0) 146210986Sneel#define DPI_BUSY BIT(16) 147210986Sneel#define OUTEN BIT(17) 148210986Sneel#define FIELD BIT(20) 149210986Sneel#define TDLR BIT(21) 150210986Sneel 151210986Sneel#define DPI_TMODE 0x44 152210986Sneel#define DPI_OEN_ON BIT(0) 153295138Sadrian 154256172Sadrian#define DPI_CHECKSUM 0x48 155290218Sadrian#define DPI_CHECKSUM_MASK (0xFFFFFF << 0) 156256172Sadrian#define DPI_CHECKSUM_READY BIT(30) 157256172Sadrian#define DPI_CHECKSUM_EN BIT(31) 158295150Sadrian 159295150Sadrian#define DPI_DUMMY 0x50 160295150Sadrian#define DPI_DUMMY_MASK (0xFFFFFFFF << 0) 161295150Sadrian 162295150Sadrian#define DPI_TGEN_VWIDTH_LEVEN 0x68 163295150Sadrian#define DPI_TGEN_VPORCH_LEVEN 0x6C 164295150Sadrian#define DPI_TGEN_VWIDTH_RODD 0x70 165295150Sadrian#define DPI_TGEN_VPORCH_RODD 0x74 166295150Sadrian#define DPI_TGEN_VWIDTH_REVEN 0x78 167295150Sadrian#define DPI_TGEN_VPORCH_REVEN 0x7C 168295150Sadrian 169295150Sadrian#define DPI_ESAV_VTIMING_LODD 0x80 170295150Sadrian#define ESAV_VOFST_LODD (0xFFF << 0) 171295150Sadrian#define ESAV_VWID_LODD (0xFFF << 16) 172292692Sadrian 173292692Sadrian#define DPI_ESAV_VTIMING_LEVEN 0x84 174210986Sneel#define ESAV_VOFST_LEVEN (0xFFF << 0) 175210986Sneel#define ESAV_VWID_LEVEN (0xFFF << 16) 176210986Sneel 177210986Sneel#define DPI_ESAV_VTIMING_RODD 0x88 178210986Sneel#define ESAV_VOFST_RODD (0xFFF << 0) 179210986Sneel#define ESAV_VWID_RODD (0xFFF << 16) 180210986Sneel 181210986Sneel#define DPI_ESAV_VTIMING_REVEN 0x8C 182210986Sneel#define ESAV_VOFST_REVEN (0xFFF << 0) 183210986Sneel#define ESAV_VWID_REVEN (0xFFF << 16) 184210986Sneel 185210986Sneel#define DPI_ESAV_FTIMING 0x90 186210986Sneel#define ESAV_FOFST_ODD (0xFFF << 0) 187210986Sneel#define ESAV_FOFST_EVEN (0xFFF << 16) 188210986Sneel 189210986Sneel#define DPI_CLPF_SETTING 0x94 190210986Sneel#define CLPF_TYPE (0x3 << 0) 191178172Simp#define ROUND_EN BIT(4) 192178172Simp 193209928Sjchandra#define DPI_Y_LIMIT 0x98 194210986Sneel#define Y_LIMINT_BOT 0 195209928Sjchandra#define Y_LIMINT_BOT_MASK (0xFFF << 0) 196210986Sneel#define Y_LIMINT_TOP 16 197178172Simp#define Y_LIMINT_TOP_MASK (0xFFF << 16) 198211453Sjchandra 199209928Sjchandra#define DPI_C_LIMIT 0x9C 200211453Sjchandra#define C_LIMIT_BOT 0 201211453Sjchandra#define C_LIMIT_BOT_MASK (0xFFF << 0) 202206829Sjmallett#define C_LIMIT_TOP 16 203206829Sjmallett#define C_LIMIT_TOP_MASK (0xFFF << 16) 204206829Sjmallett 205206829Sjmallett#define DPI_YUV422_SETTING 0xA0 206214903Sgonzo#define UV_SWAP BIT(0) 207214903Sgonzo#define CR_DELSEL BIT(4) 208214903Sgonzo#define CB_DELSEL BIT(5) 209206829Sjmallett#define Y_DELSEL BIT(6) 210211453Sjchandra#define DE_DELSEL BIT(7) 211211453Sjchandra 212211453Sjchandra#define DPI_EMBSYNC_SETTING 0xA4 213211453Sjchandra#define EMBSYNC_R_CR_EN BIT(0) 214211453Sjchandra#define EMPSYNC_G_Y_EN BIT(1) 215211453Sjchandra#define EMPSYNC_B_CB_EN BIT(2) 216211453Sjchandra#define ESAV_F_INV BIT(4) 217211453Sjchandra#define ESAV_V_INV BIT(5) 218211453Sjchandra#define ESAV_H_INV BIT(6) 219211453Sjchandra#define ESAV_CODE_MAN BIT(8) 220211453Sjchandra#define VS_OUT_SEL (0x7 << 12) 221211453Sjchandra 222178172Simp#define DPI_ESAV_CODE_SET0 0xA8 223219693Sjmallett#define ESAV_CODE0 (0xFFF << 0) 224219693Sjmallett#define ESAV_CODE1 (0xFFF << 16) 225227658Sjchandra 226227658Sjchandra#define DPI_ESAV_CODE_SET1 0xAC 227202031Simp#define ESAV_CODE2 (0xFFF << 0) 228202031Simp#define ESAV_CODE3_MSB BIT(16) 229295150Sadrian 230295150Sadrian#define EDGE_SEL_EN BIT(5) 231295150Sadrian#define H_FRE_2N BIT(25) 232295150Sadrian 233295150Sadrian#define DPI_MATRIX_SET 0xB4 234295150Sadrian#define INT_MATRIX_SEL_MASK GENMASK(4, 0) 235295150Sadrian#define MATRIX_SEL_RGB_TO_JPEG 0 236295150Sadrian#define MATRIX_SEL_RGB_TO_BT601 2 237295150Sadrian 238295150Sadrian#endif /* __MTK_DPI_REGS_H */ 239295150Sadrian