1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2/* Copyright (c) 2023 Imagination Technologies Ltd. */ 3 4#ifndef PVR_ROGUE_FWIF_CLIENT_H 5#define PVR_ROGUE_FWIF_CLIENT_H 6 7#include <linux/bits.h> 8#include <linux/kernel.h> 9#include <linux/sizes.h> 10#include <linux/types.h> 11 12#include "pvr_rogue_fwif_shared.h" 13 14/* 15 * Page size used for Parameter Management. 16 */ 17#define ROGUE_PM_PAGE_SIZE SZ_4K 18 19/* 20 * Minimum/Maximum PB size. 21 * 22 * Base page size is dependent on core: 23 * S6/S6XT/S7 = 50 pages 24 * S8XE = 40 pages 25 * S8XE with BRN66011 fixed = 25 pages 26 * 27 * Minimum PB = Base Pages + (NUM_TE_PIPES-1)*16K + (NUM_VCE_PIPES-1)*64K + 28 * IF_PM_PREALLOC(NUM_TE_PIPES*16K + NUM_VCE_PIPES*16K) 29 * 30 * Maximum PB size must ensure that no PM address space can be fully used, 31 * because if the full address space was used it would wrap and corrupt itself. 32 * Since there are two freelists (local is always minimum sized) this can be 33 * described as following three conditions being met: 34 * 35 * (Minimum PB + Maximum PB) < ALIST PM address space size (16GB) 36 * (Minimum PB + Maximum PB) < TE PM address space size (16GB) / NUM_TE_PIPES 37 * (Minimum PB + Maximum PB) < VCE PM address space size (16GB) / NUM_VCE_PIPES 38 * 39 * Since the max of NUM_TE_PIPES and NUM_VCE_PIPES is 4, we have a hard limit 40 * of 4GB minus the Minimum PB. For convenience we take the smaller power-of-2 41 * value of 2GB. This is far more than any current applications use. 42 */ 43#define ROGUE_PM_MAX_FREELIST_SIZE SZ_2G 44 45/* 46 * Flags supported by the geometry DM command i.e. &struct rogue_fwif_cmd_geom. 47 */ 48 49#define ROGUE_GEOM_FLAGS_FIRSTKICK BIT_MASK(0) 50#define ROGUE_GEOM_FLAGS_LASTKICK BIT_MASK(1) 51/* Use single core in a multi core setup. */ 52#define ROGUE_GEOM_FLAGS_SINGLE_CORE BIT_MASK(3) 53 54/* 55 * Flags supported by the fragment DM command i.e. &struct rogue_fwif_cmd_frag. 56 */ 57 58/* Use single core in a multi core setup. */ 59#define ROGUE_FRAG_FLAGS_SINGLE_CORE BIT_MASK(3) 60/* Indicates whether this render produces visibility results. */ 61#define ROGUE_FRAG_FLAGS_GET_VIS_RESULTS BIT_MASK(5) 62/* Indicates whether a depth buffer is present. */ 63#define ROGUE_FRAG_FLAGS_DEPTHBUFFER BIT_MASK(7) 64/* Indicates whether a stencil buffer is present. */ 65#define ROGUE_FRAG_FLAGS_STENCILBUFFER BIT_MASK(8) 66/* Disable pixel merging for this render. */ 67#define ROGUE_FRAG_FLAGS_DISABLE_PIXELMERGE BIT_MASK(15) 68/* Indicates whether a scratch buffer is present. */ 69#define ROGUE_FRAG_FLAGS_SCRATCHBUFFER BIT_MASK(19) 70/* Disallow compute overlapped with this render. */ 71#define ROGUE_FRAG_FLAGS_PREVENT_CDM_OVERLAP BIT_MASK(26) 72 73/* 74 * Flags supported by the compute DM command i.e. &struct rogue_fwif_cmd_compute. 75 */ 76 77#define ROGUE_COMPUTE_FLAG_PREVENT_ALL_OVERLAP BIT_MASK(2) 78/*!< Use single core in a multi core setup. */ 79#define ROGUE_COMPUTE_FLAG_SINGLE_CORE BIT_MASK(5) 80 81/* 82 * Flags supported by the transfer DM command i.e. &struct rogue_fwif_cmd_transfer. 83 */ 84 85/*!< Use single core in a multi core setup. */ 86#define ROGUE_TRANSFER_FLAGS_SINGLE_CORE BIT_MASK(1) 87 88/* 89 ************************************************ 90 * Parameter/HWRTData control structures. 91 ************************************************ 92 */ 93 94/* 95 * Configuration registers which need to be loaded by the firmware before a geometry 96 * job can be started. 97 */ 98struct rogue_fwif_geom_regs { 99 u64 vdm_ctrl_stream_base; 100 u64 tpu_border_colour_table; 101 102 /* Only used when feature VDM_DRAWINDIRECT present. */ 103 u64 vdm_draw_indirect0; 104 /* Only used when feature VDM_DRAWINDIRECT present. */ 105 u32 vdm_draw_indirect1; 106 107 u32 ppp_ctrl; 108 u32 te_psg; 109 /* Only used when BRN 49927 present. */ 110 u32 tpu; 111 112 u32 vdm_context_resume_task0_size; 113 /* Only used when feature VDM_OBJECT_LEVEL_LLS present. */ 114 u32 vdm_context_resume_task3_size; 115 116 /* Only used when BRN 56279 or BRN 67381 present. */ 117 u32 pds_ctrl; 118 119 u32 view_idx; 120 121 /* Only used when feature TESSELLATION present */ 122 u32 pds_coeff_free_prog; 123 124 u32 padding; 125}; 126 127/* Only used when BRN 44455 or BRN 63027 present. */ 128struct rogue_fwif_dummy_rgnhdr_init_geom_regs { 129 u64 te_psgregion_addr; 130}; 131 132/* 133 * Represents a geometry command that can be used to tile a whole scene's objects as 134 * per TA behavior. 135 */ 136struct rogue_fwif_cmd_geom { 137 /* 138 * rogue_fwif_cmd_geom_frag_shared field must always be at the beginning of the 139 * struct. 140 * 141 * The command struct (rogue_fwif_cmd_geom) is shared between Client and 142 * Firmware. Kernel is unable to perform read/write operations on the 143 * command struct, the SHARED region is the only exception from this rule. 144 * This region must be the first member so that Kernel can easily access it. 145 * For more info, see rogue_fwif_cmd_geom_frag_shared definition. 146 */ 147 struct rogue_fwif_cmd_geom_frag_shared cmd_shared; 148 149 struct rogue_fwif_geom_regs regs __aligned(8); 150 u32 flags __aligned(8); 151 152 /* 153 * Holds the geometry/fragment fence value to allow the fragment partial render command 154 * to go through. 155 */ 156 struct rogue_fwif_ufo partial_render_geom_frag_fence; 157 158 /* Only used when BRN 44455 or BRN 63027 present. */ 159 struct rogue_fwif_dummy_rgnhdr_init_geom_regs dummy_rgnhdr_init_geom_regs __aligned(8); 160 161 /* Only used when BRN 61484 or BRN 66333 present. */ 162 u32 brn61484_66333_live_rt; 163 164 u32 padding; 165}; 166 167/* 168 * Configuration registers which need to be loaded by the firmware before ISP 169 * can be started. 170 */ 171struct rogue_fwif_frag_regs { 172 u32 usc_pixel_output_ctrl; 173 174#define ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL 8U 175 u32 usc_clear_register[ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL]; 176 177 u32 isp_bgobjdepth; 178 u32 isp_bgobjvals; 179 u32 isp_aa; 180 /* Only used when feature S7_TOP_INFRASTRUCTURE present. */ 181 u32 isp_xtp_pipe_enable; 182 183 u32 isp_ctl; 184 185 /* Only used when BRN 49927 present. */ 186 u32 tpu; 187 188 u32 event_pixel_pds_info; 189 190 /* Only used when feature CLUSTER_GROUPING present. */ 191 u32 pixel_phantom; 192 193 u32 view_idx; 194 195 u32 event_pixel_pds_data; 196 197 /* Only used when BRN 65101 present. */ 198 u32 brn65101_event_pixel_pds_data; 199 200 /* Only used when feature GPU_MULTICORE_SUPPORT or BRN 47217 present. */ 201 u32 isp_oclqry_stride; 202 203 /* Only used when feature ZLS_SUBTILE present. */ 204 u32 isp_zls_pixels; 205 206 /* Only used when feature ISP_ZLS_D24_S8_PACKING_OGL_MODE present. */ 207 u32 rgx_cr_blackpearl_fix; 208 209 /* All values below the ALIGN(8) must be 64 bit. */ 210 aligned_u64 isp_scissor_base; 211 u64 isp_dbias_base; 212 u64 isp_oclqry_base; 213 u64 isp_zlsctl; 214 u64 isp_zload_store_base; 215 u64 isp_stencil_load_store_base; 216 217 /* 218 * Only used when feature FBCDC_ALGORITHM present and value < 3 or feature 219 * FB_CDC_V4 present. Additionally, BRNs 48754, 60227, 72310 and 72311 must 220 * not be present. 221 */ 222 u64 fb_cdc_zls; 223 224#define ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS 3U 225 u64 pbe_word[8U][ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS]; 226 u64 tpu_border_colour_table; 227 u64 pds_bgnd[3U]; 228 229 /* Only used when BRN 65101 present. */ 230 u64 pds_bgnd_brn65101[3U]; 231 232 u64 pds_pr_bgnd[3U]; 233 234 /* Only used when BRN 62850 or 62865 present. */ 235 u64 isp_dummy_stencil_store_base; 236 237 /* Only used when BRN 66193 present. */ 238 u64 isp_dummy_depth_store_base; 239 240 /* Only used when BRN 67182 present. */ 241 u32 rgnhdr_single_rt_size; 242 /* Only used when BRN 67182 present. */ 243 u32 rgnhdr_scratch_offset; 244}; 245 246struct rogue_fwif_cmd_frag { 247 struct rogue_fwif_cmd_geom_frag_shared cmd_shared __aligned(8); 248 249 struct rogue_fwif_frag_regs regs __aligned(8); 250 /* command control flags. */ 251 u32 flags; 252 /* Stride IN BYTES for Z-Buffer in case of RTAs. */ 253 u32 zls_stride; 254 /* Stride IN BYTES for S-Buffer in case of RTAs. */ 255 u32 sls_stride; 256 257 /* Only used if feature GPU_MULTICORE_SUPPORT present. */ 258 u32 execute_count; 259}; 260 261/* 262 * Configuration registers which need to be loaded by the firmware before CDM 263 * can be started. 264 */ 265struct rogue_fwif_compute_regs { 266 u64 tpu_border_colour_table; 267 268 /* Only used when feature CDM_USER_MODE_QUEUE present. */ 269 u64 cdm_cb_queue; 270 271 /* Only used when feature CDM_USER_MODE_QUEUE present. */ 272 u64 cdm_cb_base; 273 /* Only used when feature CDM_USER_MODE_QUEUE present. */ 274 u64 cdm_cb; 275 276 /* Only used when feature CDM_USER_MODE_QUEUE is not present. */ 277 u64 cdm_ctrl_stream_base; 278 279 u64 cdm_context_state_base_addr; 280 281 /* Only used when BRN 49927 is present. */ 282 u32 tpu; 283 u32 cdm_resume_pds1; 284 285 /* Only used when feature COMPUTE_MORTON_CAPABLE present. */ 286 u32 cdm_item; 287 288 /* Only used when feature CLUSTER_GROUPING present. */ 289 u32 compute_cluster; 290 291 /* Only used when feature TPU_DM_GLOBAL_REGISTERS present. */ 292 u32 tpu_tag_cdm_ctrl; 293 294 u32 padding; 295}; 296 297struct rogue_fwif_cmd_compute { 298 /* Common command attributes */ 299 struct rogue_fwif_cmd_common common __aligned(8); 300 301 /* CDM registers */ 302 struct rogue_fwif_compute_regs regs; 303 304 /* Control flags */ 305 u32 flags __aligned(8); 306 307 /* Only used when feature UNIFIED_STORE_VIRTUAL_PARTITIONING present. */ 308 u32 num_temp_regions; 309 310 /* Only used when feature CDM_USER_MODE_QUEUE present. */ 311 u32 stream_start_offset; 312 313 /* Only used when feature GPU_MULTICORE_SUPPORT present. */ 314 u32 execute_count; 315}; 316 317struct rogue_fwif_transfer_regs { 318 /* 319 * All 32 bit values should be added in the top section. This then requires only a 320 * single RGXFW_ALIGN to align all the 64 bit values in the second section. 321 */ 322 u32 isp_bgobjvals; 323 324 u32 usc_pixel_output_ctrl; 325 u32 usc_clear_register0; 326 u32 usc_clear_register1; 327 u32 usc_clear_register2; 328 u32 usc_clear_register3; 329 330 u32 isp_mtile_size; 331 u32 isp_render_origin; 332 u32 isp_ctl; 333 334 /* Only used when feature S7_TOP_INFRASTRUCTURE present. */ 335 u32 isp_xtp_pipe_enable; 336 u32 isp_aa; 337 338 u32 event_pixel_pds_info; 339 340 u32 event_pixel_pds_code; 341 u32 event_pixel_pds_data; 342 343 u32 isp_render; 344 u32 isp_rgn; 345 346 /* Only used when feature GPU_MULTICORE_SUPPORT present. */ 347 u32 frag_screen; 348 349 /* All values below the aligned_u64 must be 64 bit. */ 350 aligned_u64 pds_bgnd0_base; 351 u64 pds_bgnd1_base; 352 u64 pds_bgnd3_sizeinfo; 353 354 u64 isp_mtile_base; 355#define ROGUE_PBE_WORDS_REQUIRED_FOR_TQS 3 356 /* TQ_MAX_RENDER_TARGETS * PBE_STATE_SIZE */ 357 u64 pbe_wordx_mrty[3U * ROGUE_PBE_WORDS_REQUIRED_FOR_TQS]; 358}; 359 360struct rogue_fwif_cmd_transfer { 361 /* Common command attributes */ 362 struct rogue_fwif_cmd_common common __aligned(8); 363 364 struct rogue_fwif_transfer_regs regs __aligned(8); 365 366 u32 flags; 367 368 u32 padding; 369}; 370 371#include "pvr_rogue_fwif_client_check.h" 372 373#endif /* PVR_ROGUE_FWIF_CLIENT_H */ 374