138776Snsouch/* 293023Snsouch * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 338776Snsouch * 438776Snsouch * Permission is hereby granted, free of charge, to any person obtaining a 538776Snsouch * copy of this software and associated documentation files (the "Software"), 638776Snsouch * to deal in the Software without restriction, including without limitation 738776Snsouch * the rights to use, copy, modify, merge, publish, distribute, sublicense, 838776Snsouch * and/or sell copies of the Software, and to permit persons to whom the 938776Snsouch * Software is furnished to do so, subject to the following conditions: 1038776Snsouch * 1138776Snsouch * The above copyright notice and this permission notice (including the next 1238776Snsouch * paragraph) shall be included in all copies or substantial portions of the 1338776Snsouch * Software. 1438776Snsouch * 1538776Snsouch * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1638776Snsouch * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1738776Snsouch * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1838776Snsouch * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1938776Snsouch * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2038776Snsouch * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 2138776Snsouch * SOFTWARE. 2238776Snsouch */ 2338776Snsouch 2438776Snsouch#ifndef _GVT_REG_H 2538776Snsouch#define _GVT_REG_H 2638776Snsouch 2738776Snsouch#define INTEL_GVT_PCI_CLASS_VGA_OTHER 0x80 28119419Sobrien 29119419Sobrien#define INTEL_GVT_PCI_GMCH_CONTROL 0x50 30119419Sobrien#define BDW_GMCH_GMS_SHIFT 8 3138776Snsouch#define BDW_GMCH_GMS_MASK 0xff 3238776Snsouch 33162234Sjhb#define INTEL_GVT_PCI_SWSCI 0xe8 3438776Snsouch#define SWSCI_SCI_SELECT (1 << 15) 35162234Sjhb#define SWSCI_SCI_TRIGGER 1 3638776Snsouch 3738776Snsouch#define INTEL_GVT_PCI_OPREGION 0xfc 3838776Snsouch 3938776Snsouch#define INTEL_GVT_OPREGION_CLID 0x1AC 4038776Snsouch#define INTEL_GVT_OPREGION_SCIC 0x200 4138776Snsouch#define OPREGION_SCIC_FUNC_MASK 0x1E 4238776Snsouch#define OPREGION_SCIC_FUNC_SHIFT 1 4338776Snsouch#define OPREGION_SCIC_SUBFUNC_MASK 0xFF00 4438776Snsouch#define OPREGION_SCIC_SUBFUNC_SHIFT 8 4538776Snsouch#define OPREGION_SCIC_EXIT_MASK 0xE0 4638776Snsouch#define INTEL_GVT_OPREGION_SCIC_F_GETBIOSDATA 4 4738776Snsouch#define INTEL_GVT_OPREGION_SCIC_F_GETBIOSCALLBACKS 6 48162234Sjhb#define INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS 0 4938776Snsouch#define INTEL_GVT_OPREGION_SCIC_SF_REQEUSTEDCALLBACKS 1 5038776Snsouch#define INTEL_GVT_OPREGION_PARM 0x204 51162234Sjhb 5238776Snsouch#define INTEL_GVT_OPREGION_PAGES 2 5338776Snsouch#define INTEL_GVT_OPREGION_SIZE (INTEL_GVT_OPREGION_PAGES * PAGE_SIZE) 54162234Sjhb#define INTEL_GVT_OPREGION_VBT_OFFSET 0x400 5538776Snsouch#define INTEL_GVT_OPREGION_VBT_SIZE \ 5638776Snsouch (INTEL_GVT_OPREGION_SIZE - INTEL_GVT_OPREGION_VBT_OFFSET) 5738776Snsouch 5843998Snsouch#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B) 5943998Snsouch 6043998Snsouch#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100) 6143998Snsouch#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100) 6243998Snsouch 6343998Snsouch#define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe)) 6443998Snsouch 6543998Snsouch#define REG50080_FLIP_TYPE_MASK 0x3 6643998Snsouch#define REG50080_FLIP_TYPE_ASYNC 0x1 6743998Snsouch 6843998Snsouch#define REG_50080(_pipe, _plane) ({ \ 6943998Snsouch typeof(_pipe) (p) = (_pipe); \ 70162234Sjhb typeof(_plane) (q) = (_plane); \ 7143998Snsouch (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \ 72162234Sjhb (_MMIO(0x50090))) : \ 7343998Snsouch (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \ 74162234Sjhb (_MMIO(0x50098))) : \ 7543998Snsouch (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \ 76162234Sjhb (_MMIO(0x5009C))) : \ 7743998Snsouch (_MMIO(0x50080))))); }) 78162234Sjhb 79162234Sjhb#define REG_50080_TO_PIPE(_reg) ({ \ 80162234Sjhb typeof(_reg) (reg) = (_reg); \ 8143998Snsouch (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \ 8243998Snsouch (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \ 8343998Snsouch (((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \ 8443998Snsouch (INVALID_PIPE)))); }) 8543998Snsouch 8640785Snsouch#define REG_50080_TO_PLANE(_reg) ({ \ 8740785Snsouch typeof(_reg) (reg) = (_reg); \ 8840785Snsouch (((reg) == 0x50080 || (reg) == 0x50088 || (reg) == 0x5008C) ? \ 8940785Snsouch (PLANE_PRIMARY) : \ 9040785Snsouch (((reg) == 0x50090 || (reg) == 0x50098 || (reg) == 0x5009C) ? \ 9140785Snsouch (PLANE_SPRITE0) : (I915_MAX_PLANES))); }) 92162234Sjhb 93162234Sjhb#define GFX_MODE_BIT_SET_IN_MASK(val, bit) \ 9440785Snsouch ((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16)))) 9540785Snsouch 96162234Sjhb#define IS_MASKED_BITS_ENABLED(_val, _b) \ 97162234Sjhb (((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b)) 9840785Snsouch#define IS_MASKED_BITS_DISABLED(_val, _b) \ 9940785Snsouch ((_val) & _MASKED_BIT_DISABLE(_b)) 10040785Snsouch 101162234Sjhb#define FORCEWAKE_RENDER_GEN9_REG 0xa278 10240785Snsouch#define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84 10340785Snsouch#define FORCEWAKE_GT_GEN9_REG 0xa188 10440785Snsouch#define FORCEWAKE_ACK_GT_GEN9_REG 0x130044 10540785Snsouch#define FORCEWAKE_MEDIA_GEN9_REG 0xa270 10640785Snsouch#define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88 10740785Snsouch#define FORCEWAKE_ACK_HSW_REG 0x130044 10838776Snsouch 10938776Snsouch#define RB_HEAD_WRAP_CNT_MAX ((1 << 11) - 1) 11038776Snsouch#define RB_HEAD_WRAP_CNT_OFF 21 11138776Snsouch#define RB_HEAD_OFF_MASK ((1U << 21) - (1U << 2)) 11238776Snsouch#define RB_TAIL_OFF_MASK ((1U << 21) - (1U << 3)) 11338776Snsouch#define RB_TAIL_SIZE_MASK ((1U << 21) - (1U << 12)) 11438776Snsouch#define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \ 11538776Snsouch I915_GTT_PAGE_SIZE) 11638776Snsouch 11738776Snsouch#define PCH_GPIO_BASE _MMIO(0xc5010) 118162234Sjhb 119162234Sjhb#define PCH_GMBUS0 _MMIO(0xc5100) 120162234Sjhb#define PCH_GMBUS1 _MMIO(0xc5104) 12138776Snsouch#define PCH_GMBUS2 _MMIO(0xc5108) 12240785Snsouch#define PCH_GMBUS3 _MMIO(0xc510c) 123162234Sjhb#define PCH_GMBUS4 _MMIO(0xc5110) 124162234Sjhb#define PCH_GMBUS5 _MMIO(0xc5120) 12552776Snsouch 126162234Sjhb#define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i) * 4) 127162234Sjhb#define TRNULLDETCT _MMIO(0x4de8) 128162234Sjhb#define TRINVTILEDETCT _MMIO(0x4dec) 129162234Sjhb#define TRVADR _MMIO(0x4df0) 13052776Snsouch#define TRTTE _MMIO(0x4df4) 13152776Snsouch#define RING_EXCC(base) _MMIO((base) + 0x28) 13252776Snsouch#define RING_GFX_MODE(base) _MMIO((base) + 0x29c) 13340785Snsouch#define VF_GUARDBAND _MMIO(0x83a4) 134162234Sjhb 135162234Sjhb#define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4) 13640785Snsouch 137162234Sjhb/* XXX FIXME i915 has changed PP_XXX definition */ 13838776Snsouch#define PCH_PP_STATUS _MMIO(0xc7200) 139162234Sjhb#define PCH_PP_CONTROL _MMIO(0xc7204) 14038776Snsouch#define PCH_PP_ON_DELAYS _MMIO(0xc7208) 14143975Snsouch#define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 14243975Snsouch#define PCH_PP_DIVISOR _MMIO(0xc7210) 143162234Sjhb 144162234Sjhb#endif 145162234Sjhb